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Design of CMOS ring oscillator

PER FINNSTAM & MIKAEL SÖDERLUND

Circuit Design Group Department of Signals and Systems Chalmers University of Technology Göteborg, Sweden, 2005 EX049/2005

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Design of CMOS ring oscillator

Master’s Thesis by

Per Finnstam & Mikael Söderlund 2005

Department of Signals and Systems Chalmers University of Technology

Göteborg

Performed at Ericsson AB

Mölndal

Supervisor: Kjell Larsson Ericsson AB

Examiner: Lena Peterson Department of Signals and Systems Chalmers University of Technology

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Abstract

In this thesis we evaluate the ring oscillator implemented in CMOS. This evaluation is done by exploring the ring oscillator both in theory and practice. We have designed a VCO containing a 7-stage differential ring oscillator. It has been designed from hand calculation and verified by simulations on both schematic and layout level in a 0.5-µm process. The target performance of the VCO is a centre frequency of 200 MHz and a phase-noise requirement of –100 dBc @100 kHz. The designed ring oscillator, without the bias replica circuit meets the target performance. However, the complete VCO does not meet the target performance due to the poor noise performance of the bias replica circuit.

The implemented VCO was compared with an existing LC oscillator with almost the same centre frequency and phase-noise requirements. The result shows that the major trade off between the ring oscillator and LC oscillator is in area and power consumption. That is, the ring oscillator consumes more power but requires less area.

Since finer process geometries allows smaller device area to be used, the designed VCO was scaled into a 0.25-µm process. This redesign showed no great benefits with finer processes since minimum channel length generates significantly more noise of the MOSFET device.

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Preface

This Master’s Thesis is the final requirement for us to receive our Master of Science Degrees in Electrical Engineering from Chalmers University of Technology. The thesis project has been carried out during the spring of 2005 at the department for microwave radio design, JT/DR, at Ericsson AB in Mölndal.

We would like to thank our supervisor Kjell Larsson at Ericsson AB for his support during this project and also our examiner Lena Peterson at the department of Signals and Systems at Chalmers University of Technology.

We would also like to thank all other staff at Ericsson AB that has helped us during this time.

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Contents 1 Introduction ............................................................................................7 2 Background theory ................................................................................8

2.1 Clock generation ........................................................................8 2.2 Oscillation...................................................................................8 2.3 Types of CMOS Oscillators........................................................9 2.4 Phase noise, timing jitter of ring oscillators ..............................10 2.5 MOSFET - Devices ..................................................................14

3 Ring oscillators ....................................................................................19 3.1 General properties of ring oscillators .......................................19 3.2 Topologies................................................................................20

4 Differential VCO....................................................................................24 4.1 VCO - structure ........................................................................24 4.2 Load element ...........................................................................24 4.3 Voltage-swing consideration ....................................................28 4.4 Phase noise in Differential delay cells......................................29 4.5 Bias replica circuit ....................................................................31

5 Design ...................................................................................................33 5.1 Target performance..................................................................33 5.2 VCO- Core ...............................................................................33 5.3 Bias replica circuit ....................................................................41 5.4 Buffer stage..............................................................................42 5.5 Design summary ......................................................................44

6 Schematic simulations ........................................................................46 6.1 Performed simulations .............................................................46 6.2 Simulation results and test benches ........................................47 6.3 Simulation summary.................................................................52

7 Layout ...................................................................................................54 7.1 Floor plan .................................................................................54 7.2 Layouts.....................................................................................54 7.3 Layout simulation .....................................................................54

8 Comparison with a LC oscillator ........................................................56 8.1 LC oscillator .............................................................................56 8.2 LC vs. ring oscillator.................................................................56

9 Process Scaling ...................................................................................58 9.1 General consideration of process scaling ................................58 9.2 Redesign of delay cell in 0.25-µm process ..............................59 9.3 Simulations...............................................................................60

10 Results ..................................................................................................63 11 Discussion and conclusions...............................................................64 12 Outlook..................................................................................................65 References .....................................................................................................66

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Terminology

ASIC Application Specific Integrated Circuit MOSFET Metal Oxide Silicon Field Effect Transistor CMOS Complementary Metal Oxide Silicon VCO Voltage Controlled Oscillator OP-Amp OPerational Amplifier PLL Phase Locked Loop PD Phase Detector LPF Low Pass Filter SNR Signal to Noise Ratio

Constants and quantities

mg Transconductance of a MOS - device

k Boltzmann constant, 231038.1 −⋅ J/K q Charge of an electron T Absolute temperature, in Kelvin dBc decibel relative carrier

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1 Introduction

The MINI-LINKTM system is a product developed at Ericsson AB for digital microwave communication. The standard communication protocol used in MINI-LINKTM requires a digital signal-processing block. A well-defined ordering for switching events, i.e., low jitter, is crucial for the performance of a digital signal-processing block. This requirement makes the clock-generation block a critical part of high-performance digital circuits.

The most common clock-generating block at Ericsson AB is based on a voltage-controlled oscillator, VCO, with LC tank. The implementation of a VCO allows for compensation of process and temperature variations. A major drawback of the LC tank is the large area it consumes when implemented monolithically or the need for external components. To achieve a higher level of integration on an ASIC with monolithic oscillator a different topology has to be used. This is the reason for investigating the performance of the ring oscillators.

In this thesis project we investigated the properties of the ring oscillator implemented in CMOS technology. We have designed and laid out a ring oscillator based on a 0.5-µm BiCMOS process offered by Philips, using Cadence Analog Artist designing tool. Due to the time limit of this project the VCO has not been manufactured. The verification is performed only by simulations on both schematic and layout level.

The theory of ring oscillators has been reviewed to gain insight in designing low jitter VCO:s. The VCO design is based on hand calculations and is verified with simulations of both schematic and layout. The focus of the design is on the ring oscillator. The layout simulation results of the implemented VCO are compared to the performance of an existing LC- oscillator.

Finer process geometries allow components to consume less area. This possibility of area reduction of the VCO is explored by scaling the designed VCO into a 0.25-µm process. Other aspects of process scaling are also be considered.

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2 Background theory

This chapter introduces oscillators and their major types of implementation. It also gives theory and calculation models of phase noise [1] and MOSFET-devices [2].

2.1 Clock generation

Almost all digital circuits are dependable on at least one clock source, which generates a rail-to-rail square wave. The most common system for clock generation in Application specific Integrated Circuits, ASIC, is made by a component knows as Phase Locked Loop, PLL. The simple PLL, presented in figure 2.0, consists of a Phase Detector, PD a Low-Pass Filter, LPF and a Voltage Controlled Oscillator, VCO. Once the PLL has locked, any change in relative phase between the reference and output signal is detected by the phase detector. The feedback loop ensures that the VCO control voltage is changed to keep the phase difference constant and hence the output frequency constant.

PD LPFfref

fout=N⋅fref

VCO

÷N

Figure 2.0 Simple PLL system for clock generation

2.2 Oscillation

An oscillator is a circuit that produces a periodic signal, without any specific input signal except internal noise. An oscillator can be viewed as a feedback system, figure 2.1 with a transfer function of.

)(1)(sH

sHVV

in

out

+= (2.1)

As can be seen from equation 2.1 if H(s)= -1 then the gain would approach infinity, which results in infinity amplification of the noise component at ωo. For oscillation at one specific frequency two criteria are stated. The first criterion is that the total phase shift around the loop is 180°. The second criterion is that the feedback system amplifies its own noise at the frequency of oscillation ωo. These criteria mean that the returning signal is a negative replica of the input signal, which will give a larger difference between the input signal and the feedback signal when subtracting. The circuit is said to regenerate, see figure 2.1.

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+ H(s) +

-

Vin Vout

Figure 2.1 Feedback system which regenerates.

At some point the amplitude of the regenerating feedback system will be limited and the Barkhausen criteria of a gain=1 is fulfilled and gives an stable oscillation.

In many applications it is desirable to have the ability to tune the oscillator to different frequencies. The required VCO tuning range is mainly due to two factors. First, the tuning range must be large enough to compensate for the change in VCO centre frequency due to process and temperature variations. Second, any additional tuning required by the intended application must be added.

2.3 Types of CMOS Oscillators

There are two major types of implementation for CMOS oscillators: LC oscillators and ring oscillators.

2.3.1 LC oscillator

An LC oscillator is a resonance circuit. An inductor in parallel with a capacitor and a parasitic resistance constitute the resonator, also known as the LC tank. Electromagnetic oscillation occurs in the LC tank when energy is transferred between the capacitors and the inductor.

L C

LC tank

GR-GA GR

Active Network

Figure 2.2 A simple LC oscillator model.

Part of the stored energy is dissipated in GR when the LC tank oscillates. An active network is then introduced in the circuit to compensate for this loss. To ensure continuous oscillation is the active network is designed to generate a negative admittance greater than GR so that the total resistance in the circuit is negative. The oscillation frequency is set by the tank inductance and capacitance value.

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2.3.2 Ring oscillator

Another way to implement an oscillator is the ring oscillator. A ring oscillator consists of a number of amplifiers in a feedback loop, figure 2.3.

Amplifier stage N

-A -A -A -A -A

Figure 2.3. Ring oscillator with N number of stages

To get the ring oscillator to oscillate there needs to be at least three amplifiers, this to fulfil the first criterion of a sufficient phase shift of 180°. The second criterion for oscillations is meet if the closed loop gain is greater than 1.

2.4 Phase noise, timing jitter of ring oscillators

The interested reader is referred to Hajimiri and Lee [1] for a more detailed description.

2.4.1 Definition and the influence of timing jitter in A/D converters

All oscillators inhibit a non-wanted effect of uncertainty of where in time the clock edges will occur, with respect to the expected time. The shadowed region in figure 2.4 shows the time window in which the clock edge will occur; this region is known as the timing jitter.

∆t

Figure 2.4 definition of timing jitter in oscillators

Since the timing jitter is in the picoseconds range a direct time measurement is hard to establish. Instead the jitter usually is presented in the frequency domain and is then referred to as phase noise.

When sampling an analogue signal it is in some applications, crucial to maintain a high signal-to-noise ratio, SNR, of the sampled signal. Any uncertainty in the sampling process, due to jitter of the clock signal will deteriorate the SNR of the sampled signal. The error of the individual sample is among other noise sources directly proportional to the timing jitter introduced by the oscillator. Equation 2.2 shows the obtained SNR when sampling an analogue signal with frequency f and with a timing jitter of ∆t.

)2log(20 tfSNR ∆⋅⋅⋅−= π (2.2)

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From equation 2.2 it is obvious why it is important to reduce the timing jitter of an oscillator, which is used to clock analogue-to-digital converters.

2.4.2 Phase noise

The output from a non-ideal oscillator, i.e., a real oscillator, can be expressed as followed:

))(()( ttSinVtV oscampout φω += (2.3)

where the parameter φ(t) is a stochastic process of the phase due to various noise sources. The power spectral output from the non-ideal oscillator does then not consist of a single peak at ωosc. Instead two sidebands are introduced due to the stochastic process φ(t). The performance of an oscillator is among others measured as phase noise, which is expressed as:

⎥⎦

⎤⎢⎣

⎡ +=

carrier

sideband

PdP

dL)(

log10)( 0 ωωω (2.4)

where Psideband denotes the sideband power of the frequency region ωosc + dω and Pcarrier is the power of the wanted output signal.

Figure 2.5 shows a typical plot of the spectral phase-noise sideband, where dω is the offset frequency from the carrier.

Log(dω)

L{dω} [dBc/Hz]

1/f3

1/f2

ω1/f3

Noise floor

Figure 2.5 Spectrum of phase-noise sideband

As can been seen in figure 2.5 the phase-noise sideband can be divided into two regions.

First is the 1/f2 region, which is due to the thermal noise in the MOS devices in the oscillator. The second region, 1/f3 is due to up conversion of low-frequency noise, such as flicker noise from MOS devices. The intercept point of the 1/f2 and 1/f3 asymptotes is referred as the ω1/f

3 corner.

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2.4.3 Impulse Sensitivity Function

The impulse sensitivity function, ISF, which is denoted by Γ(x), is a function that describes how sensitive the oscillator is to an impulse noise source and hence how large the total phase shift due to the impulse would be.

The ISF is determined by applying an impulse noise source at one of the nodes in the ring oscillator. Figure 2.6 shows a ring oscillator with a noise source at one of its three nodes.

Figure 2.6 Ring oscillator with a noise source

When the noise source injects a current into the node it will cause an instantaneous change in the voltage at the node. Figure 2.7 shows the influence of the injected current when it is injected at the peak and in the transition region.

V

ns

ns

Time

Nod

e V

olta

ge

Figure 2.7 Result of injection of current in peak and transition region

As can be seen in figure 2.7 a current injection in the transition region would yield a phase shift of the output signal. The introduced phase shift is proportional to the amount of current injected by the noise source. But an injection at the peak would cause no change in the phase. As can be understood from figure 2.7 the node is most sensitive to noise in the transition region.

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It can be showed [1] that the impulse sensitivity function Γ(x) for a ring oscillator can be approximated by two triangles as shown in figure 2.8.

2π

2π

ƒ(x)

Γ(x)

ƒ’rise -ƒ’fall

1/ƒ’rise

2/ƒ’rise 1/ƒ’fall

2/ƒ’fall

Figure 2.8 Approximate ISF for a ring oscillator with asymmetric rise and fall times

The phase-noise performance of the ring oscillator is determined by the Fourier series expansion of the ISF. The amount of upconverted noise such as flicker noise is governed by the parameter dcΓ . White noise due to Thermal noise near the oscillation frequency and multiples of the oscillation frequency folds down into the 1/f2 region and is governed by the parameter 2

rmsΓ .

The approximate Γ2rms value for an asymmetric rise and fall time can be

calculated to:

)1('1

32 3

3

max

2 Af

rms +⎟⎟⎠

⎞⎜⎜⎝

⎛=Γ

π (2.5)

Where A denotes single ended symmetry, that is the ratio of the rising and falling slew rate at one node:

fall

rise

ff

A''

= (2.6)

The Γdc value can be calculated from figure 2.8 and is given by

⎟⎠⎞

⎜⎝⎛+−

=ΓAA

Ndc 112

2

π (2.7)

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2.4.4 Phase noise calculation models

The total phase noise of an oscillator is calculated by applying a noise current source simultaneously at each node in the ring oscillator. But if the noise sources are assumed to be uncorrelated each node can be viewed separately and summed. The phase noise in the two regions 1/f2 and 1/f3 is modelled by the set of equations below, where N denotes the total number of nodes in the ring oscillator.

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛⋅

∆⋅

Γ=

−

Nd

fiq

dL nrms2

2

max2

2

2/

log10)(ω

ω (2.8)

Equation 2.8 is the model for prediction of the phase noise in the 1/f2 region. The model for prediction of phase noise in the 1/f3 region is presented in equation 2.9

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛⋅⋅

∆⋅

Γ=

−

Ndfd

fiq

dL fndc /12

2

max2

2

2/

log10)(ω

ωω (2.9)

In equations 2.8 and 2.9 fin ∆−

/2 denotes the spectral current density, due to thermal noise of the used devices and f/1ω denotes the flicker noise corner of the used devices.

To calculate the 3/1 fω corner in the phase-noise spectrum, equation 2.8 is set

equal to equation 2.9 and solved for df. We then arrive at the following expression.

)1()1(

23

2

2

/1/1 3AA

AN

ff ff +−−

⋅⋅= (2.10)

As can be seen from equation 2.10, implementing as much symmetry as possible of the ISF in each delay cell one may reduce the upconversion of noise which folds into the 1/f3 region. Hence the 1/f3 corner will decrease. Equations 2.10 also propose that it is possible to reduce the 1/f3 corner by increasing the number of delay cells used.

2.5 MOSFET - Devices

The Metal Oxide Silicon Field Effect Transistor, MOSFET is the cornerstone in Complementary Metal Oxide Silicon, CMOS circuits. In the resistive channel between the source, S and the drain, D runs a current that is controlled by the voltage over the gate, G, figure 2.9. There are two types of MOSFETs, and they are NMOS and PMOS, the symbols can be seen in figure 2.10. The difference between them is if the holes or the electrons carry the channel current. In this presentation of the MOSFET the focus will be on the NMOS transistor.

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2.5.1 MOS structure

Figure 2.9 shows a simplified structure of the two MOSFET devices. The oxide layer is made of silicon dioxide; it insulates the gate from the substrate. The poly consists of a heavily doped conductive piece of polysilicon. The current runs from drain to source through an inversion channel created when a voltage is put on the gate that is greater than the threshold voltage. When inversion occurs electrons (or holes for PMOS) from the bulk are attracted to the gate, the channel is formed and the transistor can conduct current between drain and source.

n-type n-type p-type substrate (bulk)

oxide poly Source

Gate

Drain

resistive channel (n-type)

n-type substrate (bulk)

oxide poly Source

Gate

Drain

resistive channel (p-type)

(a) (b)

p-type p-type

Figure 2.9 (a) Structure of a NMOS device (b) Structure of a PMOS device

2.5.2 MOS I/V Characteristics

The current, ID that flows through the transistor is set by a number of variables that can be seen in figure 2.10.

V G S

V D S

_

+

+

_

G a te

S o u r c e

D ra in ID

W /L

V S G

V S D

_

+

+

_

G a te

S o u rc e

D ra in

I D W /L

(a ) (b )

Figure 2.10 (a) Symbol for NMOS device (b) Symbol for PMOS device

The current through the transistor can be calculated. But because of nonlinearity there are two major regions in which the transistor operates. Each region has different equations to calculate the current through the transistor. The regions are the saturation and the linear region. In which region the transistor operates is determined by voltages Vgs, Vt and Vds, see equations 2.11 and 2.12.

)(2

)(2

THGSDSDS

DSTHGSoxnD VVVV

VVVL

WCI −>⎥⎦

⎤⎢⎣

⎡−−= µ (2.11)

)()( 2max, THGSDSTHGSoxnD VVVVV

LWCI −≤−= µ (2.12)

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Equation 2.11 is used when the transistor is in the linear region, equation 2.12 is used when the transistor is in saturation. The mobility and the oxide capacitor, µCox is a parameter set by the process. The two equations above neglect short channel effects of the MOSFET, which makes the equations an approximation of the current.

These equations are the same for PMOS transistors but the polarity is changed for the variables.

2.5.3 MOSFET Small-Signal model

In analogue circuits it is essential to make calculations for small changes in the signal. The small-signal model is a description of how the small-signal parametric current changes around a bias point. The model is the same for different bias points but the values for the small-signal parameters depend on the bias point. Figure 2.11 shows the small signal model of an MOSFET device.

+

_VGS

gmVGS ro

D

CGS

CDB

CGD

gmbVSB

G

+

_ VBS

S

B

Figure 2.11 Small signal model of an MOSFET device

In the model presented in figure 2.11 ro represent the output resistance and determined by the channel-length modulation. The current sources, gm*VGS and gmb*Vsb represent the small signal currents going through the transistor.

The transconductance, gm is defined as the change in the drain current divided by the change in the gate-source voltage. It denotes the sensitivity in the device and is called transconductance. A MOSFET operating in saturation has a transconductance that can be expressed as equation 2.13 or 2.14.

)(,

THGSoxnconstVGS

Dm VV

LWC

VI

gDS

−⇒∂∂

= µ (2.13)

Doxm IL

WCg )(2µ= (2.14)

In a transistor there exists capacitance between the terminals, which are important for the small-signal model. The capacitance can be denoted to the most significant capacitors CGD, CGS and CDB shown in figure 2.11. Which is determined by the length of the channel and the width of the device.

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2.5.4 Noise sources in MOSFET

The largest noise contributions in a MOSFET transistor are thermal and flicker noise.

2.5.4.1 Thermal noise

The channel of the MOSFET may almost be viewed as a homogeneous resistor even if the channel is more conductive near the source, than at the drain. This simplifies the thermal noise of the MOSFET to:

γ⋅⋅⋅⋅= msatd gTki 42, (2.15)

Where γ depends of the operation point of the device but could be approximated to 2/3 in the saturation region and to 1 in the linear region.

2.5.4.2 Flicker noise

Flicker Noise, 1/f noise is the dominant noise source in MOSFET devices at low frequencies. This noise is introduced because of extra energy states in the surface between gate oxide and silicon substrate. These energy states randomly traps and then releases charge carriers, which generates flicker noise in the drain current.

The flicker noise is modelled by equation 2.16

fCLWKv

oxn ⋅⋅⋅

⋅=2 (2.16)

[ ] [ ][ ] [ ]FVKC

L

ox2

2 constant dependent -Process,mFecapacitanc oxide Gate

mwidthW, mLength

==

==

Since the MOSFET exhibits two types of noise sources, one frequency dependent and the other constant over frequency. The spectral density of the two different noise sources could be plotted together. Figure 2.12 shows the typically plot for the spectral density for a MOSFET device.

fC f (log scale)

−

V n

2log20

1/f Corner

Thermal Flicker

Figure 2.12 Concept of flicker noise, 1/f corner frequency

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The 1/f corner frequency for a MOSFET device is found at the frequency where the flicker noise is equal to the thermal noise; analytically the 1/f corner frequency is found by setting equation 2.16 equal to 2.15 and solving for f. This procedure yields the following expression for the 1/f corner frequency:

kTg

LWCKf m

OXC 8

3⋅⋅

= (2.17)

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3 Ring oscillators

This chapter will explore some properties of ring oscillators. These properties are frequency of oscillation, small-signal gain and topologies.

3.1 General properties of ring oscillators

The ring oscillator, as mentioned in chapter 2, comprises N amplifiers connected in a feedback loop. Since each amplifier stage acts as an inverter it will just delay the signal with time td, and hence it will be referred to as a delay cell.

3.1.1 Frequency of oscillation

The large-signal frequency at which the ring oscillator will oscillate at is determined by:

dosc tN

f⋅⋅

=2

1 (3.1)

where N denotes the number of stages used. The number of stages used is mainly determined by the power dissipation and the phase-noise performance.

3.1.2 Start-up and oscillation criteria

The transfer function for a ring oscillator with the number of stages set to N can be shown to be [2]:

N

p

N

sA

sH)1(

)( 0

ω+

= (3.2)

It comprises the transfer functions of the individual delay cells.

One of the criteria for oscillation is a phase shift of 180°, that is each stage contributes with 180°/N degrees of phase shift. The frequency at which this occurs is given by:

⎟⎟⎠

⎞⎜⎜⎝

⎛=⇒=⎟

⎟⎠

⎞⎜⎜⎝

⎛−

NN poscp

oscoo 180tan180tan 1 ωω

ωω

(3.3)

The other criterion for oscillation is a loop gain greater than 1 at ωosc . Thus one can calculate the minimum voltage gain per delay cell by inserting the oscillation frequency expression 3.3 into the gain equation found from the transfer function 3.2 and solving. This calculation yields the following expression for the minimum voltage gain of each delay cell:

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2

0180tan1 ⎟⎟

⎠

⎞⎜⎜⎝

⎛+=

NA

o

(3.4)

To ensure start-up and oscillation the gain should be chosen with margin above the minimum gain due to process and temperature variations.

It is worth noting that the small-signal frequency of oscillation, as expressed by equation 3.3, is not necessarily equal to the large-signal frequency of oscillation. This discrepancy arises because the small-signal frequency is determined by small-signal parameters such as the output resistance and capacitance of each cell whereas the large-signal frequency is determined by the equivalent resistance of the load and the capacitance of each cell. This difference in oscillation frequency will make the oscillator start oscillate at the small-signal frequency but as the amplitude grows and the circuit becomes more nonlinear the frequency will shift to the large signal frequency.

3.2 Topologies

There are two main topologies for the ring-oscillator delay cells. The topologies are the differential and the single-ended one; their implementations can be seen in figure 3.1.

a)

b)

N

+ + + + - - - -

- - - - + + + +

Figure 3.1 (a) Implementation of a differential topology. (b) Implementation of a single-ended topology.

3.2.1 Single-ended topology

The basic single-ended topology consists of CMOS inverters. The frequency is set by the current consumption and capacitance at each node and translates to [1]:

max

2

821

qLNVCW

tNf oxeffeff

DC ⋅⋅⋅⋅

∆⋅⋅⋅≈

⋅⋅=

ηµ

(3.5)

where pneff WWW += , pn

ppnneff WW

WW+

⋅+⋅=

µµµ , maxq =maximum charge in

the output node, V∆ =gate overdrive in the middle of transition, =η const., N=number of stages

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Equation 3.5 has the transistor channel length, L, of the transistor in the denominator. Consequently, the maximum frequency is process-dependent and increases when the transistors are made shorter.

In a ring oscillator with single-ended topology the gain requirement is always fulfilled since the CMOS inverter is a high-small-signal-gain stage. To ensure oscillation, the single-ended topology has to be implemented with a odd number of cells because each delay cell has a large-signal phase shift of 180°.

Current is consumed in CMOS inverters when the output node capacitances are charged and discharged. At an input step the capacitances is charged/discharged by a constant current generated by the transistor that is currently on. Consequently, a lower charging current would cause a longer transition time, that translate to a longer delay. This control is implemented by adding two transistors, figure 3.2. With this modification the delay in the cell, and thereby the frequency of oscillation, can be controlled with a voltage. This type of delay cell is called current-starved inverter.

UNMOS

UPMOS

Vin Vout

Figure 3.2 Current-starved inverter

If each cell is designed to be as symmetrical as possible, that is sizing of the NMOS and PMOS devices is done to achieve identical rise and fall times, the phase noise for a single-ended ring oscillator in the 1/f2 region can be expressed as equation 3.6 [1]:

2

20

38)(

ωω

ηω

∆⋅⋅⋅

⋅=∆

charVVdd

PkTL (3.6)

where charV =Gate voltage overdrive, ω∆ =offset frequency, 0ω =centre frequency, P =power dissipation in the load device.

Note that the expression does not depend on the number of stages.

3.2.2 Differential topology

The differential topology comprises a load and a NMOS differential pair, see figure 3.3. The delay in the cell is set by the charge in each node and the current trough the load. The load can consist of a resistor for fixed frequency or PMOS devices, which makes the oscillator tuneable with a voltage. The PMOS load is usually implemented as symmetric or cross-coupled.

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The frequency for a ring oscillator with differential topology can be expressed as equation 3.7.

p

poxptail

dC LqN

VtpVctrlWCqN

ITN

f⋅⋅⋅⋅

−⋅⋅⋅≈

⋅⋅⋅=

⋅⋅=

max

2

max 2)(

221

ηµ

η (3.7)

As can be seen in equation 3.7 the maximum frequency of oscillation is also in the differential case process dependent and increase when the transistors are made shorter.

Vin+ Vin-

Vout+ Vout-

Vdd

Itail

RL RL

Figure 3.3, A differential cell with symmetric load.

The phase noise for a differential ring oscillator in the 1/f2 region can be denoted by [1]

2

20

38)(

ωω

ηω

∆⋅⎟⎟⎠

⎞⎜⎜⎝

⎛⋅

+⋅⋅⋅⋅

≈∆tailL

DD

char

DD

IRV

VV

PkTNL (3.8)

Where Vchar=Gate voltage overdrive of the NMOS-device

As can be seen in expression 3.8 the phase noise depends on the number of delay cells used, if the power dissipation is fixed.

3.2.3 Single-ended vs Differential

When the phase-noise expressions for a single-ended ring oscillator, equation 3.6, and a differential ring oscillator, equation 3.8, are compared, it can be seen that the differential ring oscillator has N(1+Vchar/(RL*Itail)) times higher phase-noise level than the single-ended ring oscillator, with equal power dissipation, frequency and number of stages. The single-ended topology dissipates power on a per transition basis only and therefore has a better phase noise for a given power dissipation. The difference in phase noise becomes even larger when the number of stages increases.

Still, in digital circuits differential ring oscillators are often preferred because they have much better common noise rejection of substrate-coupled noise than its single-ended counterpart [1], even if the single-ended topology has a superior phase noise. Differential ring oscillators also have a lower noise injection into other circuits on the same chip [1].

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Another advantage of the differential ring oscillator over the single ended is the possibility to implement it with an even number of cells. Thus, it is possible to generate quadratic signals with the differential ring oscillator.

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4 Differential VCO

Since the VCO is to be implemented among digital components a differential topology is to be investigated further in this chapter.

4.1 VCO - structure

The differential VCO comprises three major building blocks: The bias-replica circuit, the ring oscillator (VCO core), and a buffer stage. The feedback-replica bias sets the current through the delay cells and thereby the frequency. The buffer stage converts the differential signal from the ring oscillator into a single-ended rail-to-rail switching output signal. Figure 4.1 shows the block diagram of the VCO structure.

Bias- Replica

+ Bufferstage VCO-Core

Output Vbias

VCTRL

Figure 4.1 Block diagram for the structure of the VCO

4.2 Load element

As mentioned earlier, the VCO core, shown in figure 4.1, comprises a number of delay cells each with a variable load. There are several possible implementations for this load.

4.2.1 Symmetric load

A load element based on a symmetric load is presented in figure 4.2. The load element consists of a pair equally sized PMOS devices, one biased at Vctrl and the other one diode connected.

Vctrl

Vdd

ID

(+)

(-)

Vdrop (-)

(+)Vsw

M1 M2

Figure 4.2 Implementation of symmetric load element in PMOS

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The biased PMOS device swings from the linear region into saturation as the load current increases and hence the voltage drop Vdrop increases towards Vctrl if the load is properly designed. The symmetric I-V characteristics are achieved by sizing the devices so that at the end of the swing, where both devices are in saturation and biased at Vctrl, they each carry half of the current drawn from the load. The aspect ratio of the devices used in the load element is found from equation 4.1.

22,1 )(

21

2 TPCTRLoxD VVARCI

−⋅⋅= µ (4.1)

Figure 4.3 shows the I-V characteristics at two different Vctrl voltages for the symmetric load designed for a total current of 400uA at a bias voltage of 1V. The dashed lines show the equivalent resistance for the load, which could be approximated by:

D

SWLOAD I

VR = (4.2)

Figure 4.3 I-V characteristics for symmetric load

4.2.2 Cross-coupled load

The symmetric load is modified into a cross-coupled load by adding two devices. The added devices are cross-coupled between the nodes in the differential cell. Figure 4.4 shows the cross- coupled load element.

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Vctrl

Vdd

ID/2

Vdrop

ID/2

M1

M3

M2

Figure 4.4 Implementation of cross- coupled load.

The design of the cross-coupled load is based on the symmetric load designing method. Once device M1 has been determined by equation 4.1 devices M2 and M3 is sized to give maximum single ended symmetry which archived when [5].

132 5.0 ARARAR == (4.3)

The advantage of the cross-coupled load compared with the symmetric load is that the cross-coupled load should yield more single ended symmetry, according to Betancourt-Zamora and Lee [5]. This symmetry in turn yields less upconversion of low-frequency noise and hence a lower ω1/f

3 point in the phase-noise spectrum.

The single-ended symmetry of both types of loads, symmetric and cross-coupled can be shown by their ISF, which are presented in figure 4.5. Since the single-ended symmetry is quite hard to predict with hand calculations the ISF is simulated for a 7-stage free-running oscillator at 200 MHz.

Figure 4.5 Simulated ISF for symmetric load and cross-coupled load.

Table 4.1 shows the simulated symmetry factor and calculations of the ω1/f3

corner frequency for the two different loads. ω1/f is assumed to be 1 MHz.

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Table 4.1 Symmetric load vs. cross coupled load

The symmetry A in table 4.1 is calculated from equation 2.6. As can be determined from figure 4.5 and table 4.1 the difference in symmetry between the symmetric load and the cross-coupled load is very small.

4.2.3 Noise analyses of symmetric load

The thermal noise of the load devices, which is modelled by equation 2.15, shows strong dependence on the transconductance of the individual devices in the load. Because the voltage drop across the load will vary from zero to Vctrl the transconductance of the devices will vary accordingly and hence the thermal noise will vary with the voltage drop.

At equilibrium the voltage drop across the load is Vctrl/2 and the transconductance of both devices is derived from equation 2.13. If Vctrl is larger than 2Vtp then device M2 will be in saturation, which yields γ=2/3, else γ≈1. Device M1 will be in linear region, and hence γ≈1. Therefore the total thermal noise at equilibrium is,

22112 44 gmkTgmkTin γγ += (4.4)

At one end of the swing, where Vdrop is close to zero device M1 will be in the linear region and M2 in subthreshold region. The noise current spectral density is given by equation 4.4, with the modification of γ2=1.

At the other end of the swing, where Vdrop is equal to Vctrl both devices will be in saturation and hence the current spectral density is given by.

12

344 gmkTin = (4.5)

Figure 4.6 shows an approximation of how the current spectral density varies with the voltage drop across the load for different Vctrl values.

Load Type

Symmetry A

ω1/f

3 Corner

frequency (kHz)

Symmetric Load 0.71

23

Cross coupled load 0.74

17.9

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Figure 4.6 Variation of current noise spectral density with voltage drop across the load.

As can bee seen out of figure 4.6 a lower voltage swing across the load yields a lower noise current spectral density. To keep the phase-noise models relatively simple, the noise current spectral density at each node will be approximated with the highest value, i.e. at the end of the swing, where Vdrop=Vctrl.

4.3 Voltage-swing consideration

The control voltage Vctrl sets the oscillation amplitude of the differential ring oscillator.

The optimised upper level of the voltage swing is set by the criterion that the NMOS differential pair should remain in saturation throughout the whole swing. This limitation of the voltage swing would yields the best single-ended symmetry performance. Therefore, the voltage swing should not exceed the threshold of the NMOS device and is bound by.

THnCTRL VV ≤ (4.6)

At oscillation the entire tail current is steered to one side, yielding the maximum gate voltage and minimum drain voltage of the NMOS device. At this point the NMOS device goes out of saturation if the voltage swing is larger than the threshold of the NMOS device. The threshold of the NMOS devices is determined by,

)22( FSBFTHOTH VVV φφγ −++= (4.7)

Where Vth0 is the zero bulk-effect threshold, φF Fermi level, Vsb source-bulk potential, γ=body effect.

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Since the bulk of the NMOS device in figure 5.1is tied to ground and the source potential of the device is not at ground, a body effect on the threshold will be introduced and hence the threshold will be raised somewhat over the nominal threshold with no body effect. By combining equations 4.7 and 3.1, setting Vctrl=Vtn and using some approximations one can show [6] that the maximum voltage swing which still keeps the differential pair in saturation is determined by.

θθ+⋅+

=1

0TNCTRL

VVddV (4.8)

Where

n

F

γφ

θ*22

= (4.9)

As can be seen in the equations above the optimised swing is a process- dependent variable. A voltage swing higher than predicted by 4.8 may still be used but since the NMOS-devices fall out of saturation at the end of the swing the single ended symmetry will be slightly worse with larger swings.

4.4 Phase noise in Differential delay cells

With the use of the preceding analyses and of the phase noise in section 2.3 phase noise in the f1/f^2 region for a differential delay cell with symmetric load can be derived. Using equations 2.8, 2.5, 2.15, 4.5 and 5.1 we arrive at an expression for the phase noise, which expressed in design parameters evaluates to:

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎠⎞

⎜⎝⎛

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅

−+⋅

⋅⋅⋅

+

+⋅=

201)/(

*3

163

)1(

31

10)(df

f

VtpVctrlTAIL

I

LWCoxn

TAILI

TK

A

ALogdfL

µ (4.10)

We derive the phase noise in the f1/f^3 region is similar using equations 2.9, 2.7, 2.15, 4.5, and 5.1 which evaluates to:

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎠⎞

⎜⎝⎛

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅⋅

−+⋅

⋅

⋅⋅⋅

+

+⋅=

df

cf

df

f

VtpVctrlTAIL

I

LWCoxn

TAILI

TK

A

ALogdfL

201)/(

3

163

)1(

31

10)(µ

(4.11)

where fc denotes the f1/f^3 corner frequency point and is found by equation 2.10. As can be seen in equations 4.10 and 4.11 the low phase noise favours a small NMOS device and a high voltage swing.

The phase noise in the 1/f3 region is quite hard to predict because it depends on where the 1/f3 point in the phase-noise spectrum occurs. The1/f3 point depends in turn on how symmetric the circuit becomes. The two phase-noise equations presented above assume that ideal current biasing is used. Hence the noise from the bias replica and biasing device is not included in these models.

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4.4.1 Number of stages Vs. Phase noise

As can be seen from equation 4.10 the phase noise in the 1/f2 region does not directly depend on the number of stages used. But if the design is to be made with only parasitic capacitances more stages would yield a smaller NMOS device and hence less thermal noise. On the other hand if the total power dissipation is fixed then the tail current through each cell would decrease with increasing number of stages, giving a higher phase noise in this region. Figure 4.7 shows prediction of the phase noise for a VCO with different number of stages calculated at 200 MHz and with a total power dissipation of 80 mW.

Figure 4.7 Prediction of phase noise for different number of stages, with fixed power dissipation.

As a result of using parasitic capacitances only the NMOS differential pair has to increase in size while the number of stages decreases to achieve the correct frequency. The enlargement of the NMOS pair results in higher thermal noise and almost cancels out the effect of the additional tail current. Thus, the noise in the 1/f2 region almost stays constant.

If the process at hand has a high flicker noise corner an increase in number of stages would, as can be seen in figure 4.7, reduce the 1/f3 corner frequency of the phase-noise spectra and lower the phase noise in the 1/f3 region.

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4.4.2 Tuning range vs. Phase noise

The individual delay cells are optimised for symmetry, hence with respect to the voltage swing, which holds the differential pair in saturation. As can be seen in equation 4.10 a large swing would result in less thermal noise of the load and a smaller area. But since symmetry is desired one would like to keep the NMOS – devices in or close to saturation which bounds the swing to that of equation 4.8. If a large tuning range would be implemented (given the same tail current), the voltage swing has to decrease, and hence both area and thermal noise of the load would increase. Figure 4.8 shows how the thermal noise density varies with tuning range, with the criterion of keeping the NMOS devices close or in saturation throughout the whole swing and having a gain of 2.5 at the centre tuning voltage.

Figure 4.8 Tuning range Vs. current noise spectral density due to thermal noise.

As can be seen in figure 4.8, an 80% tuning range would increase the current noise spectral density around 40%, compared with zero tuning.

4.5 Bias replica circuit

The main purpose of the current-source bias circuit is to ensure the correct behaviour of the symmetric load in each cell. That is when the control voltage is changed the current also has to be changed, so the voltage drop across the load always stays at the level of Vdd -Vctrl. Since the bias circuit implements this it will also reduce the effect of supply noise since the current and voltage swing will be held constant.

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+ -

VCTRL

Vdd

VCS

Figure 4.9 Circuit diagram of the current source bias replica

The current source bias is based on two components, as figure 4.9 shows. It includes a replica of a half delay cell and an operational amplifier. The amplifier will adjust the gate voltage of the current source device driving more or less current through the load until the voltage drop across the load is equal to Vctrl. Since this is a feedback circuit the demands on the OP Amp is an adequate phase margin and high gain. The high gain is necessary to reduce the regulation error. A high phase margin is crucial for the closed loop time response of the feedback. The closed-loop time response of two different phase margins is showed in figure 4.10.

t

t

PM=60°

PM=45°

y(t)

y(t)

Figure 4.10 Closed loop time response for two different phase margins

As can be seen in figure 4.10 the adequate phase margin should be around 60° to suppress overshoot.

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5 Design

The design performed in this chapter is based on differential VCO with symmetric load. The design is made in a 0.5-µm process offered by Phillips.

5.1 Target performance

The following target performance is set for the VCO

• Phase-noise requirements as in table 5.1

Frequency offset [Hz]

VCO phase noise [dBc/Hz]

1k -45

10k -75

100k -100

1MHz -120

Table 5.1 Phase-noise requirements

• Phase-noise requirements should be met over process variations and temperature range of –40° to 70°.

• Centre frequency of 200 MHz and a tuning capability for tuning in 200 MHz independent of temperature and process variation.

• As low power dissipation as possible.

5.2 VCO- Core

The delay cell will be implemented with symmetric load rather than the more complex cross –coupled load because the cross –coupled load showed no major advantages over the symmetric load. The symmetric load is also easier to implement and do reliable phase-noise prediction for.

The delay cell to be designed is presented in figure 5.1. It consists of two identical symmetric load elements, device M4 and M5 makes up one load element. The differential pair is made up by devices M1 and M2. The current biasing is made by device M3.

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Vdd

Vbias

M1 M2

M3

VIN+ VIN-

GND

ITAIL

Vctrl Vsw M5 M4

Figure 5.1 Circuit diagram of a single delay cell

The design of the delay cell is made in the following steps

• Determine the tuning range and hence the voltage swing across the load

• Determine the total power dissipation of the VCO core

• Gain consideration

• Sizing of current source bias device

Once the tail current and the voltage swing is determined with respect to tuning range and phase-noise requirement the load is sized. The differential pair is then sized either from the need for additional capacitance at each node or by the minimum voltage gain required, if external capacitances are to be added. However, in this design we will only use the parasitic capacitances.

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5.2.1 Tuning range and voltage swing

The frequency of oscillation, expressed in designing parameters is evaluated from section 3.1 and is found to be:

LSW

TAIL

LLC CVN

ICRN

f⋅⋅⋅

=⋅⋅⋅

=22

1 (5.1)

As stated in section 4.3 the upper limit on the voltage swing which keep the NMOS- device pair in, or close to saturation is bound by equation 4.8. This evaluates the voltage swing to somewhat over 1.1V in the process at hand. The centre voltage which implements a 45% tuning range is found by deriving expression 5.1 to fmax/fcent and solving for Vsw. This calculation gives a centre voltage of 1V.

The tuning characteristic is found in equation 5.1, which implies that the resistance of the load changes with the tail current and the voltage swing. Hence the frequency will change. Figure 5.2 shows the tuning characteristics of the differential VCO at nominal process values and at different temperatures. The voltage swing Vsw is swept from 0.9 – 1.1 V.

Figure 5.2 Tuning characteristics, nominal process

As the process variations will introduce more or less capacitance at each node and some variations in the threshold voltages the centre frequency will differ between the process corners. Figure 5.3 shows the tuning characteristics at nominal and the two process corners.

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Figure 5.3 Tuning characteristics at the two process corners.

As can be seen from figures 5.2 and 5.3 the tuning characteristics is almost linear. The frequency of 200 MHz is reachable in both process corners.

5.2.2 Power dissipation

As can be seen in equation 4.10 the phase noise in the 1/f2 depends strongly on the tail current through each cell. Figure 5.4 shows prediction of the phase noise for different tail currents calculated with a centre frequency of 200 MHz and with 7 stages.

Figure 5.4 Prediction of phase noise vs. tail current

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As can be seen in figure 5.4 a tail current of 2 mA/cell would be enough to fulfil the requirement at nominal process values. Due to process variations the total current drawn by the ring oscillator will change to met the noise target. This current variation will affect the phase-noise performance. Figure 5.5 shows prediction of phase noise at the three process corners, nominal, high and low process.

Figure 5.5 Prediction of phase noise due to process variations.

As can be seen in figure 5.5 due to process variations the phase noise at 100 kHz offset could vary ≈±3 dBc from the nominal process corner. To ensure that the phase-noise requirement is fulfilled at the high process corner the nominal current through each cell is chosen to 4 mA.

Since the design is to be made with only parasitic capacitances more stages would, as mentioned in section 4.4.1, give both less thermal noise and a lower 1/f3 interception point in the phase-noise spectrum. Figure 5.6 shows the phase-noise spectra for a VCO with different number of stages calculated at 200 MHz and with a tail current of 4 mA/stage.

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Figure 5.6 Prediction of phase noise for a VCO at 200 MHz with different number of stages and with 4 mA/stage.

As can be seen in figure 5.6, seven stages are enough to fulfil the requirement.

The phase-noise model predicts higher phase noise as the frequency grows. But the topology of differential delay cells with symmetric load also increases the tail current through each cell with output frequency. This increase in current makes the phase noise almost constant over the tuning range. Figure 5.7 shows the prediction of phase noise for a differential ring oscillator at different offset frequencies over the tuning range.

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Figure 5.7 Phase noise vs. output frequency

As stated in section 4.2.1 the sizing of the load is made once the tail current and the voltage swing have been determined. The tail current is set to 4 mA at a Vctrl of 1 V. This gives, according to equation 4.1, an aspect ratio of the load devices of 5.0/367 . This rather wide transistor is needed to get the proper phase-noise performance.

5.2.3 Delay cell gain

The minimum voltage gain in each cell, which was derived in section 3.1, is found from equation 3.4. But since the oscillator is to be tuneable the gain will vary in each cell with the frequency of oscillation and hence the gain in each cell has to be somewhat higher than the gain found by equation 3.4 to ensure oscillation throughout the whole tuning range. The process and temperature variations will also influence the gain in each cell and have to be accounted for. As stated in chapter 4 one would like to keep the NMOS device and hence the voltage gain as small as possible to reduce the thermal noise.

As stated in section 3.1 the transfer function of the delay cell is found to be

)1(

)( 0

p

sA

sH

ω+

= (5.2)

The low-frequency small-signal voltage gain, Ao, and the associated pole, ωp, of a delay cell are derived by the use of the small-signal MOSFET models presented in section 2.5. It can be shown [2] that the low-frequency voltage gain is approximated to:

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ItailVctrlgA mn≈0 (5.3)

The pole of the delay cell is found approximately by:

LLOAD

p RC1

≈ω (5.4)

Since the load has been designed, and thereby the voltage swing and the tail current set, the NMOS differential pair has to contribute with the remaining capacitance at the output node. The individual sizing of the NMOS differential pair is found by solving equation 5.1 for the needed capacitance and then finding the aspect ratio. In our design it is:

5.0

143=

n

n

LW

Figure 5.8 shows the small-signal voltage gain of a delay cell designed with the centre frequency at 1 V and a tuning range of 45% and with seven stages.

Figure 5.8 Small-signal voltage gain vs. frequency for high, low and mid tuning.

As can be seen in figure 5.8 the gain is slightly higher than 3 for the centre frequency even though the criterion states a gain equal to 1.2. This increase in gain is made to ensure oscillation over process and temperature variations and frequency tuning. Figure 5.9 shows the gain due to process variations at high tuning, i.e. Vctrl=1.1 V.

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Figure 5.9 Small-signal voltage gain at the different process corners and at high tuning.

As can be seen in figure 5.9 the small-signal voltage gain is well above the minimum voltage gain, determined to be 1.2, throughout the tuning range.

5.2.4 Current bias device

The current bias is implemented with NMOS transistor and is designed to set the tail current through the delay cell. Since the biasing device is not included in the phase-noise calculation models of the VCO one would like to keep the thermal noise as small as possible which gives a high voltage overdrive. The flicker noise should also be held down which due to equation 2.16 favours a long channel. The device is sized to

3

150=

n

n

LW

The circuit diagram of one delay cell is found in figure E.1 in appendix E. The circuit diagram for the ring oscillator is found in figure E.2 in appendix E.

5.3 Bias replica circuit

The purpose of the bias replica circuit is to adjust the current trough each delay cell. It comprises two components, an op amplifier and a half delay cell. The circuit diagram of the bias replica circuit is found in figure E.4 in appendix E.

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5.3.1 Op Amplifier

Since this thesis does not focus on building a perfect OP-Amp, an existing one will be used [7].

The Operational Amplifier at hand is a two-stage OP. It consists of two stages in cascade, see figure 5.10. The first stage is a differential stage for high gain and the second is a common-source stage for high swing on the output.

Vin Vout

High Gain High Swing

Stage 1 Stage 2

Figure 5.10 Block diagram of the OP-Amp

The phase margin of the OP- Amp is adjusted by changing the capacitance of component C in the schematic of the OP-Amp, showed in figure 5.11. Simulations showed that a capacitance of 4 pF is needed to ensure a sufficient phase margin.

Figure 5.11 Circuit diagram of the used OP-Amp

The price paid for the adequate phase margin is a lower bandwidth of the OP-Amplifier. But the application doesn’t require a high bandwidth since the settling time of the feedback isn’t a crucial design issue of the VCO.

The circuit diagram for the used OP-Amp is found in figure E.3 in appendix E

5.4 Buffer stage

The main purpose of the buffer stage is to convert the output signal from the VCO core to a rail-to-rail switching signal with a duty cycle of 50%. This is to be achieved by the use of a two-stage buffer, shown in figure 5.12.

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Input Stage Inverter stage Biasing

Vp

Figure 5.12 Two-stage buffer to achieve rail-to-rail switching.

The buffer stage is designed to get the right function. No consideration of the noise performance were taken.

5.4.1 Input stage

An active current mirror makes the input stage, which serves both as a differential to single-ended converter and an amplifier. If the amplification is greater than 5 the output signal will be cut by vdd and Vp, which gives a well defined output common mode level, independent of the input signal level. The small-signal transfer function of an active current mirror is given by [2]:

)/1)(/1(

)/2(

21

20

pp

pV ss

sAA

ωωω++

+= (5.5)

Where Ao is found by:

)||( 07012,10 rrgA m= (5.6)

The two poles associated with the active current mirror and equation 5.5 could be shown to be found by:

Lp Crr

W)||(

1

07011 ≈ (5.7)

E

mpp C

gW ≈2 (5.8)

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Since the amplifier has to work at relatively high frequencies, one would like to keep the poles relatively high and hence the output capacitance as small as possible. Therefore the NMOS differential pair is chosen to a minimum length. The same reasoning is used for the PMOS current mirror. Figure 5.13 shows the small-signal voltage gain versus frequency for the active current mirror at the nominal process corner.

Figure 5.13 Small signal voltage gain vs. frequency for the active current mirror.

5.4.2 Inverter stage

The inverter is designed to make the output signal fully rail-to-rail switching, since the input stage only switch from Vp to Vdd. The output common mode of the input stage is well defined and is to be found by simulations. The inverter is designed to have a transition level equal to the output common mode of the input stage. The PMOS device is then found by solving equation 5.9 for Wp.

22 )(5.02

1)(5.08.0

21

TppxoTnnox VVcmVddWpCVVcmC −−⋅=−⋅ µµ (5.9)

5.5 Design summary

The design of the VCO has been done with symmetric load and to fulfil the target specifications, section 5.1. The circuit diagram of the complete VCO is found in figure E.5 in appendix E.

5.5.1 Calculated performance

Table 5.2 summaries the calculated performance of the designed VCO core.

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Phase Noise (dBc) Process Corner

1kHz 10kHz 100kHz 1MHz

Power (mW)

Gain / Stage

Low -51.5 -81.5 -105.5 -126.5 134

Nominal -48.5 -78.1 -103.8 -123.8 92.4 3.5

High -46 -76 -101.2 -121.6 64.7

Target pref. -45 -75 -100 -120

Table 5.2 Calculated performance of the VCO core

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6 Schematic simulations

This chapter will present simulation results and used test benches for the designed VCO. All simulations in this chapter have been performed using Cadence IC 446 and Phillips MOS model 11.

6.1 Performed simulations

The simulations performed in this chapter are made at three different temperatures, -40, 27 and 70 degrees. The simulations are also made at three different process corners, low, nominal and high, if nothing else is stated. The simulations performed are:

• Delay Cell

o Gain

• OP-Amp

o Gain, phase

o Settling time

• Buffer stage

o Gain

• VCO Core

o Phase Noise

• VCO

o Tuning characteristics

o Power dissipation

o Output waveform

o Temperature drift

o Phase noise

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6.2 Simulation results and test benches

The different simulations require different test benches. All simulation results can be found in appendix A.

6.2.1 Delay cell

The gain of the delay cell has been simulated with the test bench presented in figure 6.1.

Figure 6.1 Test bench for gain simulations of the delay cell

The input common mode of the delay stage and Vctrl has been set to simulate the different tuning settings. The three settings are Vinc= 2.7, 2.8 and 2.9. The simulated gain vs. frequency at the different tunings of the delay cell is found in figures A.1 to A.3 in appendix A. The simulation results of the small-signal gain is almost as predicted by the calculations at nominal process and 27 deg. It is also worth noting that the gain seems to be quite low at the high process corner and at low tuning. This should not be seen as critical since the tuning voltage at high process has to be in the upper region to achieve the intended frequency range.

6.2.2 Bias Replica circuit

The gain and phase transfer function of the OP-Amp in the bias replica has been simulated with the test bench presented in figure 6.2.

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Figure 6.2 Test bench for gain and phase simulations of the OP-Amp.

The bias point of the OP-Amp is found at the differential voltage, which yields an output voltage of Vdd/2. The resulting gain and phase plot is found in figure A.4 in appendix A. From the results one could see that an adequate phase margin has been obtained.

The settling time of the bias replica is found by applying a step as the control voltage and note the output response. The resulting step response is seen in figure A.5 in appendix A. The step response is made with the entire VCO- core as load. Since the phase margin of the OP-Amp is enough the step response shows no overshoot.

6.2.3 Buffer stage

The gain of the first stage, the current mirror has been simulated with the test bench presented in figure 6.3

Figure 6.3 Test bench for gain simulations of the buffer stage

where the input common-mode voltage has been set to simulate different tuning settings. The output node where the gain is noted is at the output pin Stage_1 in figure 6.3. The simulated gain vs. frequency at different tunings of the buffer stage is seen in figures A.6 to A.8 in appendix A. From the results one could se that the minimum gain at 200 MHz is around 4.5, which is enough to get it working properly.

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6.2.4 VCO Core

The simulations of phase noise for the VCO core is simulated with the test bench presented in figure 6.4.

Figure 6.5 Test bench for VCO core phase noise.

The biasing voltage of each delay set is manually by a voltage source. This voltage and the control voltage are found by attaching the bias replica and tune in a frequency of 200 MHz. The two voltage levels is then noted and used to perform the phase-noise simulation. The resulting phase noise for the VCO core is seen in figures A.9 to A.11 in appendix A. Figure 6.6 shows the phase noise at the nominal process corner for the VCO core. The simulation results of the phase-noise performance showed that the target performance is meet both over process and temperature variations.

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Figure 6.6 Simulated phase-noise performances at 200 MHz and nominal process.

A difference of ≈1 dBc @1MHz is noted as the difference between calculations and simulations, in the 1/f2 region. The 1/f3 region differs ≈3 dBc @1kHz, this since the modelling of this region depends on variables that are quite hard to model by hand calculations.

6.2.5 VCO

All simulations performed on the complete VCO are made with the test bench presented in figure 6.7

Figure 6.7 Test bench for the simulations of the VCO.

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6.2.5.1 Tuning characteristics, power dissipation

The control voltage is swept over the tuning range and the output frequency and the power dissipation is noted. The tuning characteristics and power dissipation is seen in figures A.12 to A.17 in appendix A. It is worth noting that the centre frequency, 200 MHz was intended to be at a control voltage of 1 V, instead the frequency at Vctrl=1 V was found to be 205.5 MHz. This is due to some approximations made when modeling the capacitance at each node.

6.2.5.2 Output waveform

The output waveform is simulated with the same test bench as in figure 6.7.

The control voltage is set to the ends of the tuning range and the output waveform of the buffer stage is noted at pin Out in figure 6.7. The waveform is found in figure A.18 in appendix A. The simulated duty cycle is 47.1% at the nominal process corner.

6.2.5.3 Temperature drift

The simulations of temperature drift are made by setting a fixed voltage at pin Vctrl and then sweeping the temperature. The result of the temperature drift is found in figure A.19 in appendix A.

6.2.5.4 Phase noise

The total phase noise of the VCO is simulated with the test bench presented in figure 6.7.

The result of the total phase noise is presented in figure 6.8.

Figure 6.8 Phase-noise performance for the complete VCO

It is worth noting from figure 6.8 that the phase noise for the entire VCO is about 20 dBc higher with the feedback replica than without.

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6.2.5.5 Phase noise vs. tuning

The phase noise vs. different tunings, different output frequency is found in figure A.20 in appendix A. The simulation results shows that the phase noise at different frequency offsets stays almost constant over the tuning range.

6.3 Simulation summary

The simulations performed in this chapter correspond quite well with the calculated values. The major difference is in the phase noise for the complete VCO. Comparing the phase noise of the VCO core figure 6.6 and the phase noise for the complete VCO figure 6.8 we note a great difference between them. This difference in phase-noise performance arises since the calculations model only models the VCO core and does not include the biasing replica circuit, which in simulations showed to introduce a significant change to the phase noise. This is partly due to poor noise performance of the OP-Amp used and secondly due to high flicker noise from the symmetric load in the biasing replica circuit. Table 6.1 summarises the performance of the simulated VCO.

Table 6.1 simulated performances for the VCO core

Notes for simulation conditions

Conditions Simulated Parameter

min typ max

Unit

Centre Frequency

[1] 205.5 MHz

Phase Noise @100kHz

Fcent=200 MHz [2]

-99 -103 -106 dBc

Tuning Sensitivity

[3] 438.3 716.3 1235 MHz/V

Frequency temp drift

[4] 49.9 kHz/ deg C

Tuning settling time

[5] 306 nsec

Tuning Range

Fcent =200 MHz [6]

130 270 MHz

Power dissipation

Fcent =200 MHz [7]

70 96.25 130 mW

Duty Cycle Fcent = 200 MHz [8]

45.6 47.1 48 %

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[1] Nominal process, temperature = 27°. Vctrl = 1 V

[2], [7] For the VCO core, bias replica not included.

[3] Nominal process, temperature = 27°.

[4] Nominal process and Vctrl = 1 V

[5] Nominal process, temperature 27°. Vctrl step 0.9-1.1 V

[6] Range between the intended tuning voltages, 0.9 – 1.1 V at nominal process

[8] VCO tuned by Vctrl to 200 MHz

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7 Layout

This chapter describes the layout of the designed VCO in chapter 5. The layout in this chapter is also simulated.

7.1 Floor plan

The three major parts of the layout are the buffer stage, bias replica and the VCO core. The parts are placed in layout as in figure 7.1. Each part has the supply voltage in the upper section and gnd in the lower and the signal flow is implemented from left to right. Connections are drawn in Metall1 and 2 were Metal 2 has a width of 1.6 µm and Metal 1 a width of 1.2 µm. The input and output signals of the complete VCO are drawn in metal layer 3. The supply wire is dimensioned the general rule of 1 µm/mA. Around the design is a ring of gnd (with substrate contacts) and voltage supply (vdd) (20 µm).

Bias Replica

Vbias

Vctrl

Output Buffer -stage

Delay -cell

Delay -cell

Delay -cell

Delay -cell

Delay -cell

Delay -cell

Delay -cell

VCO core

Figure 7.1 Floor plan of the VCO

7.2 Layouts

The layout of the delay cell is designed to be as symmetric as possible this to make cascading easier, see figure B.1 in appendix B. The transistors are striped to get a smaller design. The capacitance on the output node will be affected when the transistors are divided into stripes. A capacitor is added to each output node to compensate for this loss in capacitance. The width of the PMOS devices, Wp, is striped 20 times and the width of the NMOS devices, Wn, is striped 10 times. This will generate a calculated capacitance added on each output node of 450 fF.

The layout of the remaining blocks in figure 7.1 is found in figures B.2 – B.5 appendix B where figure B.5 in appendix B shows the layout of the complete VCO.

7.3 Layout simulation

All simulations on the layout are carried out as in chapter 5. All simulation results of the layout are found in figures C.1 – C.20 in appendix C.

The simulations on layout performed in this chapter matched rather well with the results in chapter 6. The mismatch in all simulation results can be related to the capacity added on wires and nodes in layout. Table 7.1 summaries the performance of the simulated VCO after layout.

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Simulated Parameter Condition

min typ max

Unit

Centre Frequency [1] 191.5 MHz

Phase noise @100 KHz

Fcent=200 MHz [2]

-101 -103 -104 dBc

Tuning sensitivity [3] 651 MHz/V

Frequency drift [4] 43.6 kHz/deg C

Tuning settling time

[5] 281 nS

Tuning range Fcent =200 MHz [6]

130 290 MHz

Power dissipation Fcent=200 MHz [7]

73 99 132 mW

Duty Cycle Fcent=200 MHz 46 47.2 47.4 %

Table 7.1 Summary of Layout performance of the VCO

[1] Nominal process at a temperature of 27°. Vctrl at 1 V

[2] For the VCO core, bias replica not included.

[3]Nominal process and Vctrl at 1 V

[4] Nominal process and Vctrl=1 V

[5] Nominal process, step response 0.9-1.1 V

[6] Range between the intended tuning voltage

[7] For the VCO core, bias replica not included

As can be seen from the results the phase noise is somewhat better than the schematic. This improvement of the phase noise is due to lowered centre frequency in the layout. Which results in a higher tuning voltage and hence higher power consumption.

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8 Comparison with a LC oscillator

The design developed in this thesis will be compared to an existing LC oscillator. The comparison is in terms of area, phase noise, tuning range and power dissipation.

8.1 LC oscillator

The comparison is based on simulations of the layout on the ring oscillator, without buffer and bias replica and the schematic of a LC VCO core.

The LC VCO core is build up by a LC oscillator. The LC oscillator, with bipolar transistors, is implemented as a cross-coupled differential pair with a parallel resonator connected between the collector nodes, as figure 8.1.

CL L

Itail

Q1 Q2

Figure 8.1 LC topology

The LC VCO core generates a signal between 270 and 900 MHz. The comparison in is made when the VCO centre frequency is fixed at 270 MHz. The phase-noise requirements for both the VCO cores are in table 5.1.

8.2 LC vs. ring oscillator

In regards of area the CMOS VCO core has an advantage against the LC oscillator because it can be implemented on a much smaller area. In the LC VCO core the inductor is implemented off chip and is two times bigger than the design for the CMOS VCO core developed in this thesis. The area for the LC VCO core would be about 45 times bigger than the CMOS VCO if it were implemented monolithically.

The LC oscillator has a lower power dissipation as can be seen in table 8.1.

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LC VCO core CMOS VCO core Parameter

min typ max min typ max

Unit

Nominal frequency [1] 287 200 MHz

Phase noise @100 kHz [2]

-113 -103 dBc/Hz

Tuning range [2] 262 316 130 280 MHz

Power dissipation [2] 4 99 mW

Area [1] 0.44 0.19 mm2

Tuning Sensitivity [1] 3.9 19.5 651 MHz/V

Table 8.1 Comparison between a LC VCO core and a CMOS VCO core

Notes:

[1] LC (inductor off chip): Vtune=2 V, Lres=5.6 nH, VtuneN=(1,0,0), t=27 deg C, nom.proc. Itail=0.5 mA; CMOS: Vctrl=1.01 V, Itail=4 mA, N=7, t=27 deg C, nom.proc.

[2] LC core Fcent=287, VCO core Fcent=200 MHz

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9 Process Scaling

In this chapter we discuss process scaling and present a scaled version of the VCO. The VCO is to be scaled from a 0.5-µm process to a 0.25-µm process.

9.1 General consideration of process scaling

The most obvious advantage of the process scaling is the ability to implement an oscillator with higher frequency. This higher frequency is due to the decrease in channel length and the maximum frequency of a ring oscillator as stated in section 3.2 increases with smaller channel length. The other major advantage is the possibility of a decrease in device area due to the smaller minimum channel length.

The thermal noise of the device, equation 2.15, is dependent of the transconductance of the device. Each cell in the scaled version almost consumes the same tail current as before. Consequently, the transconductance almost stays the same, which yields no great difference in the thermal noise of the devices.

The other noise source is the flicker noise. As predicted by the theory of MOSFET devices, section 2.5, the flicker noise corner frequency is inversely proportional to W*L. This relationship means that the flicker noise corner of each device is quite process dependent, if the minimum channel length is used. When scaling from 0.5-µm to 0.25-µm processes the flicker noise corner would approximately be 2-3 times larger and would get even higher with finer processes. This decrease in channel length would result in a higher 1/f3 corner frequency in the phase-noise spectrum for the VCO core. Figure 9.1 shows the phase-noise spectrum for a VCO core at 200 MHz designed in the 0.5-µm processes and the scaled version with the same number of stages, with same symmetry and with the same power dissipation in the 0.25-µm processes.

Figure 9.1 Phase-noise spectrum for 0.5-µm processes and with a scaled version

As can be seen in figure 9.1 the phase noise in the 1/f3 region is about 5dBc higher in the scaled version due to the higher flicker noise corner of the devices.

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9.2 Redesign of delay cell in 0.25-µm process

In a process scaling the supply voltage is often also scaled down. This implies that the maximum voltage swing, derived in section 4.3 will decrease as the supply voltage decreases. In the 0.25-µm processes the centre voltage swing is calculated to be 0.85 V.

As can be seen in figure 9.1 the 1/f3 corner frequency in the phase-noise spectra increased significant and has to be reduced by the use of more stages and a higher tail current. As an example one could use 10 stages and a tail current of 7 mA to fulfil the requirement. Figure 9.2 shows the prediction of the phase noise for the 0.25-µm VCO at 200 MHz in the three process corners.

Figure 9.2 Prediction of phase noise for a VCO core in the 0.25-µm process.

As can be seen in figure 9.2 the prediction of the phase noise states it will hold for the demands if one uses 10 stages with a tail current of 7 mA in each stage. It is worth noting that the process scaling required larger power dissipation and a larger chip area, when minimum channel length is used.

Instead the flicker noise corner frequency of the individual devices should be kept the same. Which would achieve almost the same 1/f3 corner frequency in the phase-noise spectra. This is done by diverge from the minimum channel length of 0.25-µm and use the same channel length as the 0.5-µm process.

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Since the channel length is longer the threshold voltage will increase somewhat allowing a higher centre voltage swing than 0.85 V, which was calculated above. Instead, the centre voltage is about 0.9 V. Since the centre voltage swing is somewhat lower and µCox has decreased with a longer channel the individual devices will be somewhat larger. But the thermal noise is almost the same, which yields the same tail current through each stage. The delay stage is designed in the 0.25-µm process with a tail current of 4 mA and 7 stages. Table 9.1 shows the size of the devices of the delay cell in both processes.

Devices 0.25-µm process W/L

0.5-µm process W/L

Load device 463/0.5 367/0.5

Differential device 198/0.5 143/0.5

Table 9.1 Sizing values.

As can bee seen in table 9.1 both the load and the differential pair size have increase compared to the 0.5-µm process, due to the lower value of µCox. But since the supply voltage is lowered to 2.5 V in the 0.25-µm process the VCO core consumes less power.

9.3 Simulations

The simulations of the scaled version of the VCO core are made in Cadence IC 5033.

9.3.1 Scaled version

The simulations of the scaled VCO core with minimum channel length is made with ideal current biasing. The test bench is the same as in chapter 6.2 the result is presented in figure 9.3.

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Figure 9.3 Phase-noise simulations of the VCO core with minimum channel length: 0.25-µm.

As can be seen in the phase-noise spectrum of the scaled version the 1/f3 corner is higher and hence the phase noise is about 5 dBc @1kHz higher compared to the VCO core implemented in the 0.5-µm process, figure 6.6. This is as stated above, due to the higher flicker noise in each individual device used.

9.3.2 Redesigned

The simulations of the redesigned VCO core are made as in section 6.2.4.

The simulation results of the phase-noise spectra for the redesigned VCO – core is found in figures D.1 – D.3 appendix D. The simulation results of phase noise for the redesigned VCO core fulfil the target requirements at the nominal and low process corner and almost at the high process corner. Figure 9.4 shows the simulated phase-noise spectra of the VCO core at nominal process.

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Figure 9.4 Phase-noise simulations of the redesigned VCO core with a channel length of 0.5-µm, nominal process.

As can be seen from figure 9.4 the simulated phase noise is somewhat higher compared to the 0.5-µm processes. This is due to the larger NMOS –device and the lower voltage swing used. But the 0.25-µm process still consumes less power since the supply voltage is lowered.

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10 Results

We have in this thesis designed a fully rail-to-rail switching differential VCO with symmetric load. The design has been implemented in a 0.5-µm process. Simulations of schematic and layout have been performed to verify the calculations made with calculation models of the VCO core. Table 10.1 is a summary of the phase-noise performance at nominal process. Calculations and simulations proved to match quite well. The phase-noise requirement of –100 dBc @100 kHz at a centre frequency of 200 MHz was reached in both process corners of the VCO core. However, the complete VCO showed a phase noise of -80 dBc @100 kHz, which is 20 dBc under the requirement. The power dissipation of the VCO ranges from 70 to 130 mW depending on process parameters.

Phase noise (dBc), 200 MHz Type, nominal process

Centre Freq. (MHz)

1 kHz 10 kHz 100 kHz 1 MHz

Power (mW)

Target Pref. 200 -45 -75 -100 -126.5

Calculations 200 -48.5 -78.1 -103.8 -123.8 92.4

Schematic 205.5 -50.6 -78 -103 -123 96.3

Layout 191 -51 -79 -103 -123 99

Table 10.1 Summary of the performance of the ring oscillator

The designed VCO was scaled down to a 0.25-µm process. At first the VCO was implemented with minimum channel length, which resulted in larger area and power dissipation to fulfil the target performance. Instead the implementation was made with a channel length of 0.5-µm, just like the preceding. Simulations showed a lower µCox which result in larger area dissipation than the 0.5-µm process. The phase-noise requirements was met in the low and nominal process corner.

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11 Discussion and conclusions

The feedback –replica showed to add a significant amount of phase noise to the VCO. This is partly due to the poor noise performance of the OP-amp and the high flicker noise of the load in the bias replica. The designed buffer stage showed small margin to work correctly at 200 MHz.

The ring oscillator compared to an LC oscillator with the given phase-noise requirement consumes around half the chip area and has no need for any external components. But the trade off is made in power dissipation. The LC oscillator consumes about 25 times less power. If the phase-noise requirement where lower it would result in an even smaller ring oscillator.

The advantage of a process scaling with respect to area decrease in digital components showed not to be possible with the ring oscillator. This since the flicker noise from each individual device is a function of the channel length. A smaller channel yields higher flicker noise and would result in the need for larger power dissipation and more area. Instead the channel length should not be scaled with processes. Therefore the area used by the ring oscillator does not scale with processes.

The designed VCO was made with minimum channel length and had to have 7-stages to reduce the flicker noise. One could reduce the flicker noise from each individual device instead by widening the channel and thereby reduce the design with 3-4 stages and achieve lower power dissipation.

The major design principles for achieving a low jitter ring oscillator, except power dissipation consists of a good single ended symmetry. A Low gain to keep the NMOS differential pair as small as possible and low flicker noise from each individual device. These three criteria would keep both the 1/f2 region and the 1/f3 region in the phase-noise spectra as low as possible.

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12 Outlook

Our simulations showed that the bias replica circuit added a significant amount of phase noise to the VCO. Therefore, the bias replica circuit has to be further improved to reach the target performance. Which can be done by improving of the noise performance of the OP amplifier in the bias replica circuit. The buffer stage may also be improved to give a higher safety margin to failure.

Further improvements of the VCO could be made by redesigning the ring oscillator with a longer channel length of the MOSFET devices. The NMOS differential pair could be redesigned from the perspective to achieve as low gain as possible and introduce capacitors at each node to set the frequency.

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References [1] Hajimiri Ali, Lee Thomas H. : The design of low noise oscillator,

Kluwer Academic Publishers Group, 2000, ISBN 0-7923-8455-5

[2] Razavi Behzad : Design of analog CMOS integrated circuits, McGraw Hill, 2001, ISBN 0-07-118815-0

[3] Van der Tang Johan, Kasperkovitz Dieter, van Roermund Arthur : High-frequency oscillator design for integrated transceivers, Kluwer Academic Publisher group, 2003, ISBN 1-4020-7564-2

[4] Rabaey Jan M, Chandrakasan Anantha, Nikolic Borivoje : Digital integrated circuits a design perspective, second edition, Prentice Hall, 2003, ISBN 0-13-120764-4

[5] Betancourt-Zamora. R, Lee.T: (1998) Low phase noise CMOS ring oscillator VCOs for frequency synthesis. URL: smirc.stanford.edu/papers/iwdmic98p-raf.pdf (2005-02-04)

[6] Srinivasan,V.: (2002) Timing jitter in symmetric load ring oscillators and the estimation of aperture uncertainty in A-D. Examnesarbete 2002. URL: idserver.utk.edu/?id=200300000001656 (2005-02-25)

[7] Bernier, Marc. Mathcad: An operational amplifier for a CMOS VLSI design. URL:http://www.mathcad.com/Library/LibraryContent/MathML/opamp.htm, (2005-03-17)

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Appendix

A Schematic simulation results

B Layout of VCO

C Layout simulations results

D Schematic simulations results, 0.25-µm process

E Schematics of the VCO

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Appendix A

Figure A.1 Gain of the delay cell vs. frequency at nominal process

Figure A.2 Gain of the delay cell vs. frequency at high process

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Figure A.3 Gain of the delay cell vs. frequency at low process

Figure A.4 Gain and phase function of the OP-amp, nominal process

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Figure A.5 Step response of the bias replica circuit, loaded by the VCO- core, nominal process

Figure A.6 Gain of the active current mirror in the buffer stage, nominal process

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Figure A.7 Gain of the active current mirror in the buffer stage, low process

Figure A.8 Gain of the active current mirror in the buffer stage, high process

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Figure A.9 Phase-noise performance of the VCO core, nominal process

Figure A.10 Phase-noise performance of the VCO core, low process

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Figure A.11 Phase-noise performance of the VCO –core, high process

Figure A.12 Tuning characteristics of the VCO, nominal process

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Figure A.13 Power dissipation vs. tuning voltage of the VCO, nominal process

Figure A.14 Tuning characteristics of the VCO, low process

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Figure A.15 Power dissipation vs. tuning voltage of the VCO, low process

Figure A.16 Tuning characteristics of the VCO, high process

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Figure A.17 Power dissipation vs. tuning voltage of the VCO, high process

Figure A.18 Output waveform of the VCO at worst-case gain of the buffer stage

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Figure A.19 Temperature drift of the VCO, nominal process

Figure A.20 Phase noise at different offset frequency vs. tuning voltage

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Appendix B

185 µm

70 µ

m

Figure B.1 Layout of delay cell

735 µm

Figure B.2 Layout of VCO core

147

µm

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100 µm

238 µm

Figure B.3 Layout of Bias Replica

18 µ

m

19 µm

Figure B.4 Layout of buffer stage

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845 µm

233 µm

Figure B.5 Layout of VCO

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Appendix C

Figure C.1 Gain of the delay cell vs. frequency at nominal process

Figure C.2 Gain of the delay cell vs. frequency at high process

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Figure C.3 Gain of the delay cell vs. frequency at low process

Figure C.4 Gain and phase function of the OP-amp, nominal process

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Figure C.5 Step response of the bias replica, loaded by the VCO core, nominal process

Figure C.6 Gain of the active current mirror in the buffer stage, nominal process

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Figure C.7 Gain of the active current mirror in the buffer stage, low process

Figure C.8 Gain of the active current mirror in the buffer stage, high process

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Figure C.9 Phase-noise performance of the VCO core, nominal process

Figure C.10 Phase-noise performance of the VCO core, low process

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Figure C.11 Phase-noise performance of the VCO core, high process

Figure C.12 Tuning characteristics of the VCO, nominal process

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Figure C.13 Power dissipation vs. tuning voltage of the VCO, nominal process

Figure C.14 Tuning characteristics of the VCO, low process

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Figure C.15 Power dissipation vs. tuning voltage of the VCO, low process

Figure C.16 Tuning characteristics of the VCO, high process

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Figure C.17 Power dissipation vs. tuning voltage of the VCO, high process

Figure C.18 Output waveform of the VCO at worst-case gain of the buffer stage

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Figure C.19 Temperature drift of the VCO, nominal process

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Appendix D

Figure D.1 Phase-noise performance of the VCO core, nominal process

Figure D.2 Phase-noise performance of the VCO core, high process

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Figure D.3 Phase-noise performance of the VCO core, low process

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Appendix E

Figure E.1 circuit diagram of one delay cell with capacitors to compensate for the striping of the devices.

Figure E.2 Circuit diagram of the ring oscillator

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Figure E.3 circuit diagram of the OP – amplifier

Figure E.4 Circuit diagram of the bias replica circuit

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Figure E.5 Circuit diagram of the complete VCO