Design and Stability Analysis of DC Microgrid with Hybrid ... · proposed to ensure the stability of DC microgrid in all operating modes. The stability of the DC microgrid with controllers

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TSTE.2019.2891255, IEEETransactions on Sustainable Energy

1

Design and Stability Analysis of DC Microgridwith Hybrid Energy Storage System

Srikanth Kotra, Student Member, IEEE, Mahesh K. Mishra, Senior Member, IEEE

Abstract—This paper deals with the design and stability analy-sis of a DC microgrid with battery-supercapacitor energy storagesystem under variable supercapacitor operating voltage. Theconventional design method reported in the literature considersthe rated supercapacitor voltage in the modeling and design ofcontrollers. However, the supercapacitor unit can discharge aslow as 10% of its rated voltage due to self discharge. It is observedthat the conventional method of controller design can potentiallymake the system unstable or introduce ringing in the DC linkvoltage at low supercapacitor voltage. In this work, the sensitivityof DC microgrid stability with respect to supercapacitor voltagevariation is analyzed, an optimal supercapacitor voltage to beconsidered in the design is calculated and a design method isproposed to ensure the stability of DC microgrid in all operatingmodes. The stability of the DC microgrid with controllersdesigned using the proposed method is evaluated with digitalsimulation and experimental studies.

Index Terms—Controller design, DC microgrid, Hybrid energystorage system, Optimal controller design, Stability analysis.

I. INTRODUCTION

THE socio-economic policy reforms along with the de-creased cost of solar and wind technologies have led

to the increased demand of photovoltaic (PV) and windenergy sources in power markets. The local generation andconsumption of energy, which is referred as ‘microgrids’, iseconomical, reliable and efficient [1]. In spite of the microgridadvantages, its intermittent nature has become a challengein its successful proliferation. In general, the battery energystorage systems (BESS) are employed to compensate theoutput power fluctuations of renewable energy sources. Inrecent years, the supercapacitor (Scap) energy storage systemhas gained attention due to its high power density which cansupply transient and fluctuating power [2] to achieve powerbalance and thereby maintain the stability of the system [3].

A low-pass filter based power sharing control strategy isproposed in [3] to increase the life of battery in a hybrid energystorage system (HESS). Various energy management schemesare proposed for PV based microgrid are presented in [4]–[6].The design and analysis of a new control strategy for batteryand supercapacitor based energy storage systems are presentedin [7]. Various two loop control strategies are proposed in [8]–[10] to optimize the charge-discharge of HESS. A dual activebridge based hybrid storage is proposed in [11] to address theintermittent nature of renewables in microgrid. The stability

Manuscript received July 16, 2018; revised October 30, 2018; acceptedDecember 17, 2018. This work is supported by the Ministry of Scienceand Technology, DST India, under the project grant IUSSTF/JCERDC-SmartGrids and Energy Storage/2017.

The authors are with the Department of Electrical Engineering, In-dian Institute of Technology Madras, Chennai 600 036, India. (e-mail:[email protected]; [email protected]).

analysis of a DC microgrid with battery energy storage systemagainst variation of battery voltage is analyzed in [12]. Authorsin [13] used an admittance based model of the network tofind the stability of a DC microgrid. Various applications ofHESS in microgrid are discussed and demonstrated in [14]–[17]. New energy management systems are proposed in [18],[19] to minimize electricity cost of multi-party microgrids. Anew controller design approach is proposed in [20] to achieveDC link voltage stabilization of a DC microgrid with constantpower loads.

Although, the battery-supercapacitor based energy storagesystems are employed in above literature, the modeling, designand stability aspects of microgrid with such storage systemsare not discussed in detail. Instability in DC microgrids canoccur due to various reasons such as dynamic variation ofgeneration and load, changes in system operating conditions,variation in system component values and controller param-eters [21]. In the conventional design reported in [3]–[10],the DC link voltage controller is designed by considering therated supercapacitor voltage. However, the system in practicalcondition may not always operate at rated supercapacitorvoltage. In low supercapacitor operating conditions, the DCmicrogrid voltage control loop with conventional design hasvery low gain margin and phase margin and it can introduceringings in the DC link voltage and may lead to instability ifnot addressed. In this work, a new design method is proposedto ensure sufficient gain margin and phase margin at all valuesof supercapacitor operating voltage to achieve stable operation.The major contributions of this work are:

1) Accurate modeling of DC microgrid with HESS.2) Sensitivity analysis of DC microgrid with supercapacitor

voltage variation.3) Finding the optimal supercapacitor voltage to be consid-

ered in the design such that the DC microgrid is stableat all supercapacitor operating voltages.

4) Designing the DC link voltage controller such that itprovides sufficient gain margin and phase margin at allsupercapacitor operating voltages.

II. SYSTEM CONFIGURATION AND CONTROL STRATEGY

The schematic of the DC microgrid considered in this workis shown in Fig. 1(a). The control strategy proposed in [22]is adapted for the DC microgrid considered in this work asshown in Fig. 1(b). There are four possible operating modesas shown in Fig. 2. The control strategy regulates the DC linkvoltage in all the four operating modes using battery or PVsource. The four operating modes are explained below.

1) Battery Discharging Mode (BDM): In this mode, thePV power is less than the load power and the battery



2

Lpv

Spvvpv

Dpv

Cpv

+

PV source

LB

vB

SB1

SB2

CdB

CB

LSC

SSC1

SSC2

CdSC

CSC

Supercapacitor unit

Battery unit

vsc

ipv

iB iSC

DC loads+

+

+ vdc

(a)

(b)

iavg

vdc

vdcref

iosc

inetve DC link voltage

controllerDC linkvoltage

controller output (iavg)

variationbased PMA

SoCB

impp

iBref

iSCref

iB

ipvref

ipv

PV current

controller

Spv

+ - SB1

SB2

+-

Battey current

controller

iSC

SSC1

SSC2

Scap current

controllerSoCSC

Low-pass filter

+ -

Load relay

Fig. 1. (a) DC microgrid with HESS [9] (b) Control strategy adapted [22].

SoC is within limits. Therefore, the battery dischargesto regulate the DC link voltage.

2) Load Shedding Mode (LSM): In this mode, the PVpower is less than the load power and the battery isfully discharged. Therefore the loads are disconnectedand the available power is used to charge the battery.

3) Battery Charging Mode (BCM): In this mode, the PVpower is more than the load power and the battery SoCis within limits. Therefore, the battery regulates the DClink voltage by charging with the excess power available.

4) PV Off-MPPT Mode (POM): In this mode, the batteryhas fully charged, therefore, the PV is operated in off-MPPT mode to regulate the DC bus voltage.

The DC microgrid performance is analyzed in the above fouroperating modes for conventional and proposed designs atoperating conditions of VSCO set to 112 V, 32 V and 12 V.

III. MODELING OF THE DC MICROGRID

A two loop control strategy is employed with an averagecurrent control loop to control the battery, supercapacitor andPV currents and an outer voltage control loop to regulatethe DC bus voltage as shown in Fig. 1(b). The oscillatorycomponent of the DC link voltage controller output is suppliedby supercapacitor using a low-pass filter [3]. In the conven-tional modeling [5]–[10], it is assumed that the supercapacitoroperating voltage (VSCO) is always within limits and it aloneparticipates in the dynamics of the DC link voltage. However,the supercapacitor voltage can decrease below the lower limitdue to controlled or uncontrolled discharge cycles. As thesupercapacitor operating voltage decreases, the right half planezero (RHZ) in its small signal model moves towards origin.When the RHZ of supercapacitor converter moves closer tothe battery RHZ, both the battery and the supercapacitorconverters equally participate in the dynamics of DC linkvoltage. Therefore, the battery converter model should beincluded in the forward path of voltage control loop.

End

Generate the reference currents to Battery, Supercapacitor and PV converters

SoCB>BL

SoCSC>SH

N

Y

Y

N N iBref = iavg, ipvref = impp

iSCref = iosc+iSCh(Loads are off )

Y

iBref = iavg, iSCref =iosc,ipvref = impp

SoCB<BH

Y

iBref = iavg, iSCref=iosc+iSCh

ipvref = impp

iBref = iavg, ipvref = imppiSCref = iosc

SoCSC<SH

N

iBref = 0, ipvref = iavg

iSCref =iosc+iSCh

N

Y

Deficit Power ModeExcess Power Mode

Start

iavg, impp, SoCB, SoCSC

iavg>0N Y

Battery Charging Mode

PV Off-MPPT Mode Battery Discharging Mode

Load Shedding Mode

SoCSC>SH

iBref = iavg, ipvref = impp

iSCref = iosc (Loads are off )

iBref = iavg, ipvref = impp

iSCref =iosc+iSCh

N

iBref = 0, ipvref = iavgiSCref =iosc

SoCB>BL

Y

N

SoCSC<SH

Y

Fig. 2. Power management algorithm of DC microgrid considered.

A. Modeling of Current Control Loops

The current control loops of battery and supercapacitorconverters are shown in Fig. 3(a) and the correspondingtransfer functions are explained in this section. The duty ratio(dB) to battery current (iB) transfer function GciB(s) [23] is,

GidB(s) =iB(s)

dB(s)= GidB0

1 + sωziB

1 + sQBω0B

+ s2

ω20B

(1)

GidB0 =2Vdc

RLD′2B

, ωziB =2

RLCdc(2)

QB = D′

BRL

√Cdc

LB, ω0B =

D′

B√LBCdc

(3)

Similarly, the duty ratio (dSC) to the inductor current (iSC)transfer function of supercapacitor converter is given by,

GidS(s) =iSC(s)

ˆdSC(s)= GidS0

1 + sωziS

1 + sQSω0S

+ s2

ω20S

(4)

vdc

vdcrefGf (s)Gcv(s)

iB +

+vdc+ - + - GciB(s)

M

1

VGidB(s)

dBGviB(s)

iBref

Battery current control loop

iSCref iSC+ - GciS(s)M

1

VGidS(s)

dSC

SCH

GviS(s)

Supercapacitor current control loop

+ -

(a)

vdc

vdcrefGf (s)Gcv(s)

iB +

+

vdc+ -

B

1

HGviB(s)

iBref

Battery current control loop

iSCref1-Gf (s)

iSCGviS(s)

Supercapacitor current control loop

(b)

SC

1

H

VH

VH

BH

Fig. 3. (a) Small signal model of the DC microgrid (b) Simplified smallsignal model of the DC microgrid.



3

GidS0 =2Vdc

RLD′2SC

, ωziS =2

RLCdc(5)

QS = D′

SCRL

√Cdc

LSC, ω0S =

D′

SC√LSCCdc

. (6)

The battery current control loop controller is given by,

GciB(s) = GciB0

1 + ωzciB

s

1 + sωpciB

, (7)

where, ωzciB and ωpciB are respectively chosen to be a decadeahead and a decade after the desired battery current controlloop bandwidth (ωcB). The design of supercapacitor currentcontroller GciSC(s) is similar to that of GciB(s).

B. Modeling of Voltage Control Loop

The small signal model of DC microgrid is simplified asshown in Fig. 3(b) by ensuring the battery and supercapacitorcurrent control loop bandwidths are at least ten times of that ofvoltage control loop. The low-pass filter transfer function isGf (s) = (1 + sτc)

−1, where τc is the time constant whichis designed to obtain cut-off frequency of 5 Hz [3]. Thesupercapacitor inductor current (iSC) to DC link voltage (vdc)transfer function GviS(s) [23] is given by,

GviS(s) =vdc(s)

iSC(s)= GviS0

1− sωzvS

1 + sωpvS

(8)

GviS0 =HVD

′

SCRL

2HSC, ωzvS =

D′2

SCRL

LSC, ωpvS =

2

RLCdc, (9)

where Cdc=CdB+CdSC+Cpv . The battery current (iB) to DClink voltage (vdc) transfer function GviB(s) [23] is,

GviB(s) =vdc(s)

iB(s)= GviB0

1− sωzvB

1 + sωpvB

(10)

GviB0 =HVD

′

BRL

2HB, ωzvB =

D′2

BRL

LB, ωpvB =

2

RLCdc(11)

The uncompensated loop gain of the DC link voltage controlloop with battery and supercapacitor converters is given by,

TuV (s) = HV [Gf (s)GviB(s)

HB+

(1−Gf (s))GviS(s)

HSC] (12)

The transfer function of DC link voltage controller Gcv(s) isGcv(s) = Gcv0(1 + ωzcv

s ), where, ωzcv is placed a decadeahead of the desired bandwidth of DC link voltage controlloop (ωcv) and Gcv0 is selected such that the unity gain crossover of compensated voltage control loop occurs at ωcv . Thecompensated loop gain is TcV (s) = Gcv(s)TuV (s).

IV. CONVENTIONAL DESIGN METHOD

In conventional design method [3]–[10], the controllersGciB(s), GciSC(s) in battery, supercapacitor current controlloops and Gcv(s) in DC link voltage control loop are designedby considering the rated supercapacitor voltage. For betterunderstanding, the supercapacitor voltage used in the modelingand design of controllers is represented by VSCD and the op-erating voltage of the supercapacitor is represented by VSCO.For the system parameters given in Table I, the controllers

0

50

100

g(

)

100

101

102

103

104

105

-270

-180

-90

Pha

se (

deg)

TcB

Frequency (Hz)

TcB

Mag

nitu

de (

dB)

TcSC1TcSC2

TcSC1

TcSC2

Fig. 4. Frequency response of compensated battery current control loop(TcB) and compensated supercapacitor current control loop at VSCO=112 V(TcSC1) and VSCO=32 V (TcSC2).

GciB(s), GciSC(s) in battery, supercapacitor current controlloops are designed using conventional method to achieveinfinite gain margin and 78.60 phase margin at a bandwidth4 kHz and 6 kHz respectively as shown in Fig. 4. Thecontroller parameters are GciB0 = 0.5984, GciSC0 = 0.8976,ωzciB = 2519.3 rad / s, ωpciB = 251930 rad / s, ωzciSC =3769.9 rad / s, ωpciB = 376990 rad / s.

The right half plane zero (RHZ) of the supercapacitorconverter ωzvS is located at 633.7 Hz. Therefore, the voltagecontrol loop bandwidth is chosen to be 63.37 Hz, so that theeffect of RHZ can be minimized. The controller Gcv(s) inDC link voltage control loop is designed using conventionalmethod to achieve a bandwidth of 63.7 Hz as shown inFig. 5 and the corresponding parameters are Gcv0 = 2.1272,ωzcv = 39.82 rad/s. It is observed that the controller Gcv(s) de-signed using conventional method provides gain margin of 20dB, 9.15 dB, 0.633 dB and a phase margin of 800, 40.90, 5.450

at supercapacitor operating voltages of 112V, 32V and 12Vrespectively as shown in Fig. 5. Therefore, in the conventionaldesign method, the system gain margin and phase margindecrease as the supercapacitor operating voltage decreases.The reduced gain margin and phase margin results in ringingin DC link voltage, battery and supercapacitor currents. Thelocus of closed loop poles of DC link voltage control loopwith conventional design under variation of supercapacitoroperating voltage is shown in Fig. 6. It is observed that both thepoles of the system are on negative real axis for VSCO = 112 Vto 32 V and for VSCO = 31 V to 12 V, the poles are complexconjugates which implies that there will be ringing in DClink voltage for VSCO = 31 V to 12 V. At VSCO = 11 V, one

0

50

Mag

nitu

de (

dB)

10-1

100

101

102

103

104

180

220

260

Pha

se (

deg)

Tcv1

Frequency (Hz)

Tcv1Tcv2

Tcv3

Tcv2

Tcv3

Mag

nitu

de (

dB)

Fig. 5. Frequency response of compensated voltage control loop at VSCO

of 112 V (Tcv1), 32 V (Tcv2) and 12 V (Tcv3).



4

-600 -400 -200 0 200 400 600 800

-100

-50

0

50

100

Real Axis (s-1)

VSCO=112 VIm

agin

ary

Axi

s (s

-1)

VSCO= 31 V

VSCO= 12 V

VSCO= 12 V

VSCO=11 V

VSCO=10 V

VSCO= 96 V

VSCO=11 V

VSCO= 31 VVSCO=10 V

Fig. 6. Locus of closed loop poles of DC link voltage control loop usingconventional design with variation in supercapacitor operating voltage.

TABLE ISYSTEM PARAMETERS

Parameter ValueBattery Ah capacity & rated voltage 26 Ah & 108 VScap capacitance & rated voltage 8.28 F & 112 VPV source: Vmpp & Impp at 1000 W/m2 120 V & 6.8 ABattery, Scap, PV inductors: LB , LSC , LPV 5 mH, 5 mH, 5 mHDC link voltage, Load power: Vdc & Pload 210 V & 630 WSwitching frequency: Fsw 20 kHzFeedback gains: HB , HSC & HV 1, 1 & 1

of the poles enter the right half plane which implies that thesystem becomes unstable for VSCO less than 11 V. Therefore,the controller designed using conventional design method maymake the DC microgrid unstable during low supercapacitoroperating voltage.

V. PROPOSED DESIGN METHOD

In the proposed design method, an optimal supercapacitorvoltage is considered instead of the rated voltage in the designof DC link voltage controller such that the same controllerensures sufficient gain margin, phase margin and bandwidthat all supercapacitor operating voltages. The current controllerdesign remains same as that of the conventional design. Theeffect of variation of supercapacitor voltage on the stability ofmicrogrid is discussed below.

A. Effect of variation of supercapacitor voltage

The major drawback of the conventional design method isthat, the controller designed by considering the rated super-capacitor voltage VSCD is not able to provide sufficient gainmargin and phase margin when the supercapacitor operatingvoltage VSCO decreases. Therefore, it is required to designthe controllers by considering lower supercapacitor voltageinstead of the rated voltage. In order to understand the ef-fect of variation of supercapacitor voltage, the supercapacitorvoltage VSCD considered in the design and the supercapacitoroperating voltage VSCO are varied from 112 V to 12 V andthe corresponding gain margin, phase margin and bandwidthare plotted. It is observed that the gain margin and phasemargin increase as VSCD decreases as shown in Fig. 7(a)and (b). However, as VSCD decreases, the bandwidth of theDC link voltage control loop decreases as shown in Fig.7(c). Therefore, there is a trade off between the decrease inbandwidth and increase in gain margin, phase margin. Thevariation of gain margin, phase margin and bandwidth of

voltage control loop is formulated as a function of superca-pacitor design voltage VSCD and the optimal value of VSCD

is calculated by maximizing the gain margin, phase marginand bandwidth functions using MATLAB tool ‘fmincon’ (findminimum of constrained nonlinear multi-variable function), anonlinear programming solver.

B. Formation of Objective Function

The optimal value of supercapacitor voltage is calculated bymaximizing the gain margin, phase margin and bandwidth ofDC link voltage control loop at worst operating condition i.e.,VSCO = 12 V. At VSCO = 12 V, the gain margin (GM), phasemargin (PM) and bandwidth (BW) of DC link voltage controlloop are expressed as a function of supercapacitor voltageVSCD using the curve fitting tool with sum of squares dueto error (SSE) less than 1.5 and R-square between 0.9990 to1 as given below.

GM(VSCD) = −3.399e−7 × V

4SCD + 5.048e

−5 × V3SCD

+3.47e−3 × V

2SCD − 0.9292 × VSCD + 43.67,

PM(VSCD) = 4.638e−6 × V

4SCD − 1.524e

−3 × V3SCD

+0.1849 × V2SCD − 10.24 × VSCD + 244.3,

BW (VSCD) = 6.838e−7 × V

4SCD − 1.683e

−4 × V3SCD

+1.451e−2 × V

2SCD − 0.1901 × VSCD + 1.25

(13)

The objective function is framed as minimization of theweighted negative sum of the gain margin GM(VSCD),phase margin PM(VSCD) and bandwidth BW (VSCD) plusa penalty factor corresponding to the inequality constraints asgiven below.

min fobj = −[wGM GM(VSCD) + wPM PM(VSCD)

+wBW BW (VSCD)] + 1000 ∗ P,(14)

subjected to,16 ≤ VSCD ≤ 112; 10 ≤ GM(VSCD) ≤ 29.8

70 ≤ PM(VSCD) ≤ 89.8; 10 ≤ BW (VSCD) ≤ 20.5

0 ≤ wGM ≤ 1; 0 ≤ wPM ≤ 1; 0 ≤ wBW ≤ 1,

where VSCD, wGM , wPM and wBW are the variables tobe optimized using an adaptive optimization framework [24]to minimize the objective function while satisfying the con-straints imposed. The penalty factor is zero in the beginning.If any of the constraints violate by P amount, then 1000×P isadded to the objective function as a penalty (14). The optimiza-tion function is solved using nonlinear programming solver‘fmincon’ [25] in MATLAB and the solver has converged toVSCD = 46.32 V, wGM = 1, wPM = 1, wBW = 0.9998. There-fore, the supercapacitor voltage VSCD ≈ 48 V is consideredin the proposed design.

C. Design of DC link voltage controller in proposed method

In the proposed design method, the DC link voltage con-troller Gcv(s) is designed with the optimal supercapacitorvoltage i.e., VSCD = 48 V. The small signal model of DCmicrogrid shown in Fig. 3 is still valid, but the parame-ters of GviS(s) [23] change as GviS0 = 3982, ωzvS =3982.2 rad / s, ωpvS = 9.99 rad / s. It can be observed thatthe right half plane zero ωzvS has moved towards origini.e., ωzvS decreased from 633.7 Hz to 116.4 Hz. Therefore,



5

(a) Gain margin (dB) (b) Phase margin (degree) (c) Bandwidth (Hz)

VSCD (V) VSCD (V) VSCD (V)

Fig. 7. DC link voltage control loop frequency response with variation of VSCD and VSCO (a) Gain margin (b) Phase margin (c) Bandwidth.

-20

0

20

40

Mag

nitu

de (

dB)

10-1

100

101

102

103

180

225

270

315

Pha

se (

deg)

Tcv1

Frequency (Hz)

Tcv1

Tcv2

Tcv3

Tcv2

Tcv3

Mag

nitu

de (

dB)

Tcv4

Tcv4

Fig. 8. Frequency response of compensated voltage control loop at VSCO

of 112 V (Tcv1), 48 V (Tcv2), 32 V (Tcv3) and 12 V (Tcv4).

TABLE IICOMPARISON OF PROPOSED DESIGN WITH CONVENTIONAL DESIGN

VSCO (V ) Gain Margin (dB) Phase Margin (deg) Bandwidth (Hz)Conv. Prop. Conv. Prop. Conv. Prop.

112 20 29.8 80.2 89.8 63.7 20.532 9.15 18.9 40.9 55.8 27.3 10.812 0.633 10.4 5.45 35.5 33 11.7

the bandwidth of DC link voltage control loop is chosenas 11.7 Hz at the supercapacitor operating voltage VSCO

of 48V . However, while operating at VSCO equal to 112 V,the bandwidth is equal to 20.5 Hz as shown in Fig. 8. Theparameters of the DC link voltage controller (Gcv) designedusing the proposed method are Gcv0 = 0.6938, ωzcv = 7.28rad/s.

The comparison of gain margin, phase margin and band-width for the conventional design and proposed design is givenin Table II. It is observed that the proposed design provideshigher gain and phase margins at all supercapacitor operatingvoltages VSCO. From the locus of closed loop poles of DC linkvoltage control loop with proposed design shown in Fig. 9, itis observed that both the poles of the system are on negativereal axis of the s-plane for VSCO = 112 V to 2 V. Therefore, thesystem is stable and there are no ringings in DC link voltagefor VSCO = 112 V to 2 V.

VI. SIMULATION STUDIES

The DC microgrid shown in Fig. 1(a) is modeled usingMATLAB/Simulink tool and its performance is compared

-300 -250 -200 -150 -100 -50 0-1

-0.5

0

0.5

1

Real Axis (s-1)

Imag

inar

y A

xis

(s-1

)

VSCO= 112 V

VSCO= 112 V to 2 VVSCO= 96 V

VSCO= 2 V

{

VSCO= 80 V VSCO= 3 V

Fig. 9. Locus of closed loop poles of DC link voltage control loop usingproposed design with variation in supercapacitor operating voltage.

under conventional design and proposed design. The systemparameters are given in Table I. In order to observe the changesin operating modes, the inputs to the power managementalgorithm i.e., PV MPP reference current impp, battery andsupercapacitor SoCs are varied such that the system entersinto all the four operating modes. The same variation of inputsis considered for simulation studies of both conventional andproposed designs. The battery, supercapacitor SoC upper limitsi.e., BH , SH and lower limits i.e., BL, SL are set as 0.95, 0.95and 0.40, 0.20 respectively.

A. Performance of DC microgrid with conventional design

The dynamic response of DC microgrid with conventionaldesign is evaluated at supercapacitor operating voltage VSCO

of 112 V, 32 V and 12 V with the same controller Gcv(s)designed with rated supercapacitor voltage. The performanceof DC microgrid at VSCO = 112 V is shown in Figs. 10(a)-(e).The system is turned on at t = 0 s with SoCB and SoCSC setto 0.6 and 0.4 respectively and the PV current reference is setto 1 A at 110 V as shown in Fig. 10(b) and (e) respectively.The load power is set to 315 W i.e., 1.5 A drawn from DClink as shown in Fig. 10(b). The load power 315 W is morethan the PV power 110 W, therefore, the system is in deficitpower mode. As the battery SoC is within limits, it suppliesthe deficit power in battery discharging mode.

The focus of the simulation studies is kept mainly on thedynamic variations in DC link voltage at the starting of thesystem and during the changes in load, PV and battery states.At t = 0 s, it is observed that the DC link voltage vdc has a



6

0.20.40.60.8

1

0 1 2 3 4 5 6 7 8 9 10108

110

112

-8-4048

0246

210

230

250

0 0.2 0.4

210230250

0.5 0.6208

210dc

SC B

B

pv

SC

mpp load

pv

B

SC

Fig. 10. Performance of DC microgrid at VSCO=112 V with conventionaldesign (a) DC link voltage (b) PV MPP current reference, PV and load currents(c) Battery and supercapacitor SoC inputs (d) Battery and supercapacitorcurrents (e) Battery, supercapacitor and PV voltages.

peak overshoot of 35 V and it settles in 0.12 s as shown inthe zoomed view of vdc in Fig. 10(a). At t = 0.5 s, a step loaddisturbance of 50% of rated load i.e., 315 W is introduced asshown in Fig. 10(b). It caused a dip of 1.2 V in the DC linkvoltage which settled in 0.06 s as shown in the zoomed viewof vdc in Fig. 10(a).

From t = 0 to 2 s, the system is in battery discharging modeand the supercapacitor supplies the transient component ofpower in DC link and charges with 2 A whenever its SoC isless than the upper limit as shown in Fig. 10(d). From t = 2 to4 s, the system is in load shedding mode as the battery SoCis set 0.35, which is less than the lower limit BL i.e., 0.4.The load is disconnected and the load current becomes zeroas shown in Fig. 10(b). The excess power is used to charge thebattery and supercapacitor units as shown in Fig. 10(d). Fromt = 4 to 6 s, the system is in excess power mode where thebattery regulates the DC link voltage by absorbing the excesspower in battery charging mode as shown in Fig. 10.

From t = 6 to 8 s, the PV power is set more than the loadpower and the battery SoC is set higher than the upper limitBH which forces the PV system to operate in Off-MPPT modeto regulate the DC link voltage.

From Fig. 10(b), it can be observed that the PV currentis always less than the PV MPP reference current impp. Att = 8 s, the battery SoC is set 0.6 which is less than the upperlimit. The system enters in battery charging mode as shown inFig. 10(d). Similarly, at t = 9 s, the system enters into batterydischarging mode. These results show that the system is stableduring operating mode changes. The variations in PV MPPcurrent reference, load changes, battery and supercapacitorSoC variations and battery, supercapacitor and PV voltagesshown in Fig. 10 are maintained same for the rest of thesimulation studies.

With the same controller Gcv(s) designed by consideringrated supercapacitor voltage, the DC microgrid is operated

0 1 2 3 4 5 6 7 8 9 10

32

33-8-4048

190210230250

0 0.2 0.4170210270

0.5 0.55 0.6208210

BDM

vdc (V)

LSM BCM POM BCM BDM

iSC (A)iB (A)

vSC (V)

Fig. 11. Performance of DC microgrid at VSCO=32 V with controllersdesigned using conventional method (a) DC link voltage (b) Battery andsupercapacitor currents (c) Supercapacitor voltage.

-505

1015

140

170

210

240

270

0 0.5 1150210270

5 5.1 5.2206

210

0 1 2 3 4 5 6 7 8 9 10

12

13

BDM

vdc (V)

LSM BCM POM BCM BDM

iSC (A)iB (A)

vSC (V)

Fig. 12. Performance of DC microgrid at VSCO=12 V with controllersdesigned using conventional method (a) DC link voltage (b) Battery andsupercapacitor currents (c) Supercapacitor voltage.

at the supercapacitor voltage VSCO of 32 V and 12 V. Thecorresponding simulation results are shown in Figs. 11 (a)-(c)and Figs. 12 (a)-(c) respectively. When VSCO is set to 32 V,the major observation is that the peak overshoot at t = 0 s hasincreased to 60 V with a settling time of 0.25 s and the stepload change has caused a dip of 2.5 V at t = 0.5 s as shownin the zoomed view of vdc in Fig. 11(a). When VSCO is setto 12 V, it is observed that the peak overshoot at t = 0 s hasincreased to 62 V with a settling time of 1.1 s and the stepload change has caused a dip of 3.5 V at t = 5 s and there aresignificant oscillations in vdc as shown in the zoomed view ofvdc in Fig. 12(a). Therefore, it is evident that the gain marginand phase margin with conventional design are decreasing asthe supercapacitor operating voltage decreases, which in turnis causing the higher peak overshoot and ringing in DC linkvoltage, battery and supercapacitor currents.

B. Performance of DC microgrid with proposed design

The controller Gcv(s) in the DC link voltage controlloop is designed with the optimized supercapacitor voltagei.e VSCD = 48 V and its dynamic response at supercapacitoroperating voltage VSCO equal to 112 V, 32 V and 12 V isshown in Figs. 13(a)-(c), Figs. 14(a)-(c) and Figs. 15(a)-(c)respectively. It is observed that there are no oscillations in DClink voltage and it has a starting peak overshoot of 4 V, 24 Vand 28 V with settling time ts of 0.3 s at VSCO equal to 112 V,



7

207

210

2130 0.2 0.4

210212

0.5 0.75208

210

0 1 2 3 4 5 6 7 8 9 10

-8-4048

0246

BDM

vdc (V)

LSM BCM POM BCM BDM

iSC (A)

ipv (A) impp (A)iload (A)

iB (A)

Fig. 13. Performance of DC microgrid at VSCO=112 V with proposed design(a) DC link voltage (b) PV MPP current reference, PV and load currents (c)Battery and supercapacitor currents.

210

230

250

0 0.2 0.4210230

0.5 0.7 0.9207

210

0 1 2 3 4 5 6 7 8 9 10

32

33-8-4048

vdc (V)

iSC (A)iB (A)

vSC (V)

BDM LSM BCM POM BCM BDM

Fig. 14. Performance of DC microgrid at VSCO=32 V with proposed design(a) DC link voltage (b) Battery and supercapacitor currents (c) Supercapacitorvoltage.

32 V and 12 V respectively as shown in Fig. 16. It is observedthat the step load disturbance has caused a voltage dip of 1.5 V,3 V, 4.2 V with settling time of 0.5 s at VSCO equal to 112 V,32 V and 12 V respectively as shown in Fig. 16(b).

The comparison of peak overshoot Mp, settling time tsat the starting of the system, voltage regulation ∆V for astep load change of 50% of rated load and settling time t∆V

during step load change observed in DC link voltage withconventional design and proposed design is given in TableIII. It is observed that the proposed design has significantlyreduced the peak overshoot Mp at all operating voltages ofsupercapacitor and the oscillations in the DC link voltage areeliminated as shown in Fig. 16(a). The variation in DC linkvoltage during increase in PV power and battery state changeare shown in Figs. 16(c) and (d) and the magnitude of voltagedip (∆V) during disturbances has increased by a small margindue to the reduced bandwidth in proposed design.

VII. EXPERIMENTAL STUDIES

A laboratory prototype of DC microgrid shown in Fig.1(a) is developed as shown in Fig. 17 to verify the dy-namic response of the DC microgrid with conventional designand proposed design. The control unit is implemented usingdSPACE-MicrolabBox 1201 and the system parameters aregiven in Table I. The experimental results of DC microgridwith conventional design and operating at VSCO of 12 V areshown in Fig. 18(a)-(b). The initial dynamics of DC link

190

210

230

250

0 0.2 0.4210230

5 5.1 5.2206210

-8-4048

0 1 2 3 4 5 6 7 8 9 10

12

13

vdc (V)

iSC (A)iB (A)

vSC (V)

BDM LSM BCM POM BCM BDM

Fig. 15. Performance of DC microgrid at VSCO=12 V with proposed design(a) DC link voltage (b) Battery and supercapacitor currents (c) Supercapacitorvoltage.

0 0.2 0.4210

230

250

0 0.25 0.5

170210250

3.5 3.7 3.9

209.9210

210.1

3.5 3.7 3.9

209.9210

210.1

3.5 3.7 3.9

209.9210

210.1

6 6.1 6.2209.8

210210.2210.4

6 6.1 6.2

210210.2210.4

6 6.1 6.2

210210.2210.4

SCO SCO SCO

5 5.2 5.4206208210212

0.5 0.7 0.9206

208

210

0.5 0.7 0.9208

209

210

0 0.4 0.8 1.2140

210

270

Fig. 16. Dynamic response of vdc with conventional design (blue color) andproposed design (red color) at (a) Starting of the system (b) Step load change(c) Step change in PV current (d) Step change in battery current.

voltage, battery current and supercapacitor current are shownin Fig. 19(a). It is observed that the DC link voltage has a peakovershoot of 78 V at t1 instant and oscillates for a duration of1.95 s as shown in Fig. 19(a). A step load of 315 W i.e., 50% ofthe rated load power is applied at t2 instant and it is observedthat the DC link voltage oscillates with a peak overshoot of6 V for a duration of 0.6 s as shown in Fig. 19(b).

The experimental results of DC microgrid with the con-troller Gcv(s) designed using the proposed method and op-erating at a supercapacitor voltage VSCO equal to 12 V areshown in Fig. 20(a)-(b). It is observed that the the DC linkvoltage has a peak overshoot of 29 V at t1 instant as shown inFig. 21(a) which is only 37% of that of the conventional designand the oscillations in vdc are reduced significantly as shownin Fig. 21(a). The voltage dip at t2 instant has increased to 9 V

Supercapacitorpack

IGBT legTransducers

Battery pack

Gate driverDC link

Host system

dSPACE 1202

Inductor

Fig. 17. Experimental setup of DC microgrid.



8

TABLE IIICOMPARISON OF CONVENTIONAL AND PROPOSED DESIGNS USING

SIMULATION STUDIES

Parameter VSCO = 112 V VSCO = 32 V VSCO = 12 VConv. Prop. Conv. Prop. Conv. Prop.

Mp(V) 35 4 60 24 62 28ts(s) 0.12 0.3 0.25 0.3 1.1 0.3

∆V (V) 1.2 1.5 2.5 3 3.5 4.2t∆V (s) 0.06 0.5 0.08 0.5 0.16 0.5

(4 A/div)vdc(50 V/div)210 V iB

iSC

(1 A/div)

20 s/div

1

iload

vSC 20 V/div

vB (1 V/div)

108 V

(1 A/div)20 s/div

32 2 31

(a) (b)

Time (s) Time (s)

Fig. 18. Experimental results using conventional method of design andVSC0 = 12 V: (a) Battery current iB , DC link voltage vdc and supercapacitorcurrent iSC (b) Load current iload, battery voltage vB and supercapacitorvoltage vSC .

(a)

vdc(27 V/div)

iSC (2 A/div)

vdc (10 V/div)210 V

21

iSC (2 A/div)0.3 s/div 0.3 s/div

(b)

(10 A/div)iB

210 V

(10 A/div)iB

Time (s) Time (s)

288 V

Fig. 19. Experimental results using conventional method of design: (a)Zoomed view of Fig. 18(a) at t1 instant (b) Zoomed view of Fig. 18(a) at t2instant.

and settling time has increased to 0.4 V. This is due to the factthat the proposed design provides less bandwidth comparedto that of conventional design. The major improvement is thatthe peak overshoot has reduced significantly and the ringingin DC link voltage is eliminated. This is due to the fact thatthe gain margin and phase margin of the DC microgrid withthe proposed design are more than that of the conventionaldesign as given in Table II.

Similarly, the experimental results for both the conventionaldesign and the proposed design with supercapacitor operatingvoltages of 32 V and 112 V are shown in Fig. 22 and Fig. 23respectively and the performance comparison is given in TableIV. It is observed that the conventional design has an initialpeak overshoot of 64 and 37 V at VSCO = 32 and 112 V re-spectively. Whereas, the proposed design has a peak overshootof 14 V and 4 V at VSCO = 32 V and 112 V respectively, whichare much less than that of the conventional design.

TABLE IVCOMPARISON OF CONVENTIONAL AND PROPOSED DESIGNS USING

EXPERIMENTAL STUDIES

Parameter VSCO = 112V VSCO = 32V VSCO = 12VConv. Prop. Conv. Prop. Conv. Prop.

Mp(V ) 37 4 64 14 78 29ts(s) 0.15 0.4 0.21 0.45 1.95 0.4

∆V (V ) 1 3 3 7 6 9

(4 A/div)

vdc (20 V/div)

iB

iSC

(1 A/div)

20 s/div

1

iload

vSC (20 V/div)

vB (50 V/div)108 V

(2 A/div)

20 s/div

2 21

(a) (b)

Time (s) Time (s)

210 V

Fig. 20. Experimental results using proposed method of design andVSCO = 12 V: (a) DC link voltage vdc, Battery current iB and Supercapacitorcurrent iB (b) Load current iload, Battery voltage vB and Supercapacitorvoltage vSC .

(a)vdc(35 V/div)

iSC (4 A/div)

vdc (10 V/div)

21

iSC (2 A/div)

0.2 s/div 0.2 s/div

(b)

(4 A/div)iB(4 A/div)iB

Time (s) Time (s)

210 V

210 V

239 V

Fig. 21. Experimental results using proposed method of design: (a) Zoomedview of Fig. 20(a) at t1 instant (b) Zoomed view of Fig. 20(a) at t2 instant.

vdc (10 V/div)

t1

0.1 s/div

210 V

(2 A/div)iB

Time (s)(a)

iSC (4 A/div)

274 V

t1

0.2 s/div

iSC (10 A/div)

vdc(7 V/div)

210 V

224 V

(4 A/div)iB

Time (s)(b)

Fig. 22. Experimental results of DC microgrid: (a) Conventional design withVSCO = 32 V (b) Proposed design with VSCO = 32 V.

vdc (20 V/div)

iSC (4 A/div)0.3 s/div

(b)

(4 A/div)iB

Time (s)

210 V

237 V

0.2 s/divTime (s)t1 (a)

214 V

0.1 s/div

210 Vvdc (10 V/div)

(4 A/div)iB

iSC (10 A/div)

t1 (b)

Fig. 23. Experimental results of DC microgrid: (a) Conventional design withVSCO = 112 V (b) Proposed design with VSCO = 112 V.

VIII. CONCLUSION

The effect of supercapacitor voltage variation on the sta-bility of DC microgrid is analyzed with its accurate smallsignal model. An optimal supercapacitor voltage based DClink voltage controller design method is proposed to ensure thesufficient gain margin and phase margin at all supercapacitorvoltages. The simulation and experimental results confirmedthat the proposed design provides higher gain and phasemargins than that of the conventional design. Therefore, theproposed controller design achieves superior dynamic responseover a wide range of supercapacitor operating voltages.



9

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[2] Y. Jia, R. Shibata, N. Yamamura, and M. Ishida, “Characteristics ofsmoothed-power output topology of stand-alone renewable power systemusing edlc,” in 2006 37th IEEE Power Electron. Specialists Conf., June2006, pp. 1–7.

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Srikanth Kotra (S’15) was born in Lingala, Waran-gal, India in 1991. He received his Bachelor degreefrom Jawaharlal Nehru Technological University,Hyderabad, India, in 2012. Presently he is pursuingPh.D. at Indian Institute of Technology Madras,Chennai, India. His research interests include powerelectronic converter applications in microgrid andrenewable energy systems and electric vehicles.

Mr. Srikanth is the recipient of the Best PaperAward at the 2015 IEEE India Conference (IN-DICON) held at New Delhi, India and the Best

Presentation Award at 2015 IEEE Industrial Electronics Conference (IECON)held at Yokohama, Japan.

Mahesh K. Mishra (S’00-M’02-SM’10) MaheshK. Mishra (S00-M02-SM10) received the B.Tech.degree from the College of Technology, Pantnagar,India, in 1991, the M.E. degree from the IndianInstitute of Technology, Roorkee, India, in 1993,and the Ph.D. degree from the Indian Institute ofTechnology, Kanpur, India, in 2002, all in electricalengineering. He has about 29 years of teachingand research experience. For about ten years, hewas with the Department of Electrical Engineering,Visvesvaraya National Institute of Technology, Nag-

pur, India. He is currently a Professor with the Department of ElectricalEngineering, Indian Institute of Technology Madras Chennai, India. Hisresearch interests include the areas of power distribution systems, powerelectronics, microgrids, and renewable energy systems.

Prof. Mahesh is a Life Member of the Indian Society of TechnicalEducation. He received the IETE Prof. Bimal Bose Award in 2015 forhis outstanding contributions to Power Electronics Applications in PowerSystems. In Nov. 2017, he has been elected as Fellow of Indian NationalAcademy of Engineering. He is senior member of IEEE and serves as anEditor for the IEEE Transactions on Sustainable Energy.

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Design and Stability Analysis of DC Microgrid with Hybrid ... · proposed to ensure the stability of DC microgrid in all operating modes. The stability of the DC microgrid with controllers