SYNOPSIS OF

DESIGN AND DEVELOPMENT OF ADVANCED

NUMERICAL DISTANCE RELAYING TECHNIQUES

A THESIS

to be submitted by

C. VENKATESH

for the award of the degree

of

DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL ENGINEERINGINDIAN INSTITUTE OF TECHNOLOGY MADRAS

JULY 2014

1 Introduction

Protective relays serve as a backbone to the power system. A century old protection tech-

nique has recently transformed itself into fourth generation technology, a massive development

from i) electromechanical to static, ii) static to digital and from iii) digital to numerical and

wide area protection. In 1960 Rockefeller [1] suggested the use of digital computers to protect

power system equipments and this opened up a new area in digital protection. This pioneering

work attracted many researchers which finally led to the developments in algorithms and filters

which are targeted towards digital implementation. In fourth generation technology protective

relays, all the logics, techniques and filters are implemented numerically. It also provides scope

for development of sophisticated algorithms to assist the distance algorithm for intelligent trip

decision. This led to the wide spread use of intelligent electronic device (IED) throughout the

power system network, right from generation, transmission and sub-transmission to distribu-

tion.

Transmission lines are typically protected by distance protection and it has been serving this

task for at-least a century. Numerical distance relay (NDR) protecting transmission lines

receives two 3 phase inputs i.e voltage from capacitor voltage transformer (CVT) and cur-

rent from current transformer (CT). NDR processes these inputs and estimates the apparent

impedance. If the estimated impedance is within the set zone of protection, tripping signal is

forwarded to the corresponding pole/breaker as set in the protection logics. It may appear to be

simple, however it is very difficult to achieve high speed and accurate estimation of apparent

impedance of the protected line. This is due to factors like, fault resistance, remote end in-feed,

high source to line reach impedance ratio (SIR) and CVT transients which may cause NDR

to mal-operate i.e., over-reach or under-reach [2]. This mal-operation may result in system

stability issues and damage to equipments which may lead to safety issues.

1.1 Motivation

This research work focuses on developments in numerical distance protection where four dif-

ferent problems i.e., delay in total fault clearing time (TFCT) due to time delay in communica-

tion medium or failure of communication medium, relay mal-operation due to CVT transients,

estimation of electronic ferro resonance suppression circuit (FSC) resistance and protection of

series compensated parallel transmission (SCPTL) lines are discussed.

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Distance relay is typically assisted by tele-protection schemes to reduce the TFCT. However,

this involves cost due to communication infrastructure. The currently available technique

which is still serving the utility is the loss of load protection [3] which is used to accelerate

tripping when communication medium is not available or failed. The major limitation is that,

it covers all fault types except three-phase fault, as the idea is to detect loss of load current

in the healthy phases. This has motivated the need to develop and test accelerated trip logic

in real time which can detect balanced faults and can be used along with the existing distance

algorithms.

Capacitor voltage transformer is typically used to measure voltages at extra high voltage level

because of economic reasons. The fault information delivered by CVT may result relay mal-

operation if transients are close to fundamental frequency. Distance relay mal-operation due

to potential device transients was first reported in AIEE committee report [4]. Even though

transient phenomenon in CVT was existing before, it was not brought to notice due to the slow

response time of electromechanical relays. On the other hand, NDR offers half to one full

cycle range high speed tripping which emphasized the issue due to CVT transients. This led to

the birth of digital CVT models and new techniques/logic to assist the distance algorithm for

intelligent trip decision [5, 6, 7, 8]. Most of the techniques proposed were focused to either

adaptively reduce zone 1 reach or to provide fixed time delay. Other proposed algorithms

are obtained by using simplified CVT model. These factors motivated the research for a cost

effective, system independent, simple, and adaptive blocking logic.

Recently, CVT with electronic FSC was proposed [9], where passive FSC was replaced with

electronic FSC. The damping resistance value in electronic FSC was estimated by trial and

error method. Moreover, the obtained damping resistance values were not validated for ferro-

resonance test and transient response test [10] by digital simulation. This motivated the need

to estimate damping resistance and test it as per the standard.

In the case of transmission line with series compensation, NDR is prone to mal-operate due

to factors like voltage inversion, current inversion and sub-synchronous resonance [11]. Even-

though memory polarization is currently available to handle inversion issue, sub-synchronous

resonance is still a bottle-neck. The existing zone settings for protecting series compensated

single line may degrade the NDR performance in the presence of parallel line with series com-

pensation. In order to estimate the zone reach setting, utility has to estimate the steady state

and transient errors encountered. This factor motivated to analyze the relay behaviors which

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are used to protect SCPTL.

1.2 Objectives of the Work

The main objectives of the research work are :

1. To design assisting logics for numerical distance relay, which can be implemented with-out any modification in hardware and existing algorithms. The logics are,

(a) Accelerated trip logic - To accelerate tripping time for balanced faults when com-munication medium fails or when communication time is high

(b) Adaptive blocking logic - To prevent mal-operation of distance relay due to CVTtransients

Implementation of above logics along with existing distance relay algorithm in field pro-grammable gate array (FPGA) to test the performance in real time.

2. Estimation of damping resistance for electronic FSC and to test the performance in realtime

3. Estimation of steady state error encountered by distance relay for single phase to groundfault (SPGF) in SCPTL.

1.3 Scope of the Work

The scope of the work is limited to the protection of transmission lines by distance relays,

which are given as follows

1. The assisting logics i.e., accelerating logic and adaptive blocking logic are individuallogic blocks which can be implemented along with existing distance protection withoutany modification in existing distance algorithm.

2. Testing the performance of estimated damping resistance for ferro-resonance and tran-sient response test are limited to digital simulations. Whereas, the performance of NDRfor estimated resistance is tested in real time using FPGA.

3. The other part of the work which analyzes the distance relay steady state error is limitedto the protection of SCPTL terminated at same buses at both ends. The analysis is limitedto steady state error for SPGF under the assumption that capacitor is not bypassed by airgap or metal oxide varistor, which is the case for low fault current levels.

2 Description of Research Work

The performance of assisting logics and the performance of CVT with electronic FSC has to be

tested in real time before field implementation, as direct implementation without testing may

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lead to catastrophic equipment damages. This demands for a power system modeling where

every individual element in the network is modeled to mimic its behavior depending upon the

requirements. In this research work, Alternative Transient Program (ATP) is used to model the

entire power system. This includes CVT model [5], CT model [12], arc modeling [13], bus bar

model and frequency dependent line modeling [14] for transmission line. In order to test the

performance, the protection algorithm in existing IEDs has to be updated, but this cannot be

done as details regarding hardware and software are not available and are proprietary. This is

overcome by first designing and testing the existing distance algorithm in FPGA.

2.1 Numerical Distance Relay Design

The existing distance relay algorithm along with the most important features are first developed

in Xilinx spartan 3A DSP 3SD1800A-FG676. The extracted fault information (vr,y,b, ir,y,b)

is then played to the relay which involves both real and non real time operations as shown

in Figure 1. As the aim is to test the performance of assisting logics and electronic FSC in

Power SystemModeling in ATP

CVTCT

LINE

BusBar

Arc

Antialiasing filtering,sampling, dc offset

removal in MATLAB

scaling, conversionto signed 16 bitand conversionto HEX format

Numerical distancerelay code inHDL verilog

vr,y,b, ir,y,b

.COE file

bit file

generation

code validation using ISim

code validation using Chipscope Pro

OscilloscopeReal Time

Fig. 1 Design of numerical distance relay for real time testing

real time, analog signal processing i.e. anti-aliasing filter, sampling and digital signal pre-

processing (filtering to remove dc offset) are done using MATLAB. The signals after pre-

5 / 16

processing are then scaled down, converted to signed 16 bit and finally converted to HEX

format. The fault information is then stored in FPGA memory and later used for processing by

relay. This relay incorporates the most important modules as shown in Table I. The complete

Table I Distance relay modules

Module Name FunctionDiscrete Fourier transform to estimate phasorsSequence transformation to estimate sequence parametersPolarizing quantity to estimate polarizing phasorsGround elements to estimate positive sequence impedancePhase elements to estimate positive sequence impedanceSecurity counter to prevent mal-operation

design of NDR is done using hardware description language (HDL) Verilog coding and Xilinx

ISE-12.1 WebPACK is used to synthesize and implement the design in FPGA.

3 Accelerated Trip Logic

This subsection presents the AT logic which is to be included in sending end relay and receiv-

ing end relay. Figure 2 shows the logic which will assert the AT signal. This AT signal will

Ph. Element

RYZ2

Y BZ2

BRZ2

G. Element

RZ2

YZ2

BZ2

TripT

ACCELERATED TRIP

V2 < V2thV0 < V0thI2 < I2thI0 < I0th

Zest < Zactual

SIR < 5series compensation disabled=1

AT

≥1Timer

Timer

&

Trip

Signal sent

to Rr

Zone 1

Zone 2

Zone 3

Signal received

from Rr

existinglogic

1

Fig. 2 Accelerated trip logic along with existing PUTT scheme

RZ2, YZ2, BZ2 Zone 2 ground elements RYZ2, Y BZ2, BRZ2 Zone 2 phase elementsV2, I2 negative sequence phasor V2th, I2th negative sequence thresholdV0, I0 zero sequence phasor V0th, I0th zero sequence thresholdZest estimated positive sequence Zactual actual positive sequence

impedance impedance

be acting as an input to the existing permissive under-reach transfer trip scheme (PUTT) com-

munication scheme as shown in Figure 2. In order to test the performance of AT logic in real

6 / 16

time, test system shown in Figure 3 is considered. The extracted fault information for 170km,

Ph. Element

RYZ2

Y BZ2

BRZ2

G. Element

RZ2

YZ2

BZ2

TripT

ACCELERATED TRIP

V2 < V2th

V0 < V0th

I2 < I2th

I0 < I0th

Zest < Zactual

SIR < 5

AT

Figure 1: Proposed accelerated trip logic

S

CTCVT CTCVT

Rs Rr

R

G1

δs

ZS ZL G2ZS

δr

Communication delay

Zone 1

Zone 2

F

−20 0 20 40

0

20

40

60

80

Resistance (Ω)

Rea

ctan

ce(Ω

)

ZL

Z1Z2Z3Zest.

2

Fig. 3 Single line diagram of test system

180km, 190km and 200km for a particular value of SIR (0.25) and loading condition (δs = 30)

is played to sending end relay (Rs), receiving end relay (Rr) and the signals are captured using

4 input channel oscilloscope. Operating time delays with and without AT logic obtained using

hardware are shown in Table II (excluding circuit breaker operating time). Since the signal

Table II Relay operating time (from hardware)

Fault location (km) Operating time(ms)Rr Rs Rs

without AT logic with AT logic170 19 64 28180 19 64 30190 19 64 30200 19 64 30

transmission time can be as high as 45ms [15] without including the signal propagation time,

communication delay is assumed to be 45ms. It can be observed that there is a considerable

reduction in total fault clearing time when AT logic is incorporated along with the existing

communication scheme.

4 CVT Transient Detection Logic

In order to handle the issue of distance relay mal-operation due to CVT transients, the re-

quirement is to extract the CVT transients i.e., the filter should provide good attenuation at

fundamental frequency. Transfer function of the proposed filter in z domain (z) for which the

required output is CVT transients is shown in equation (1) which is obtained for a sampling

rate of 600 Hz.

H(z) = 0.5 + 0.5z−6 (1)

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Magnitude response of this filter shown in Fig. 4 confirms that this filter meets this requirement.

It is also necessary that the transient information is available as soon as possible to block the

100 101 102 103−150

−125

−100

−75

−50

−25

0

fundamental frequency

Frequency (Hz)

Magnitude(d

B)

Fig. 4 Magnitude response digital filter to extract CVT transients

trip signal due to over-reach. The proposed logic which performs this task is shown in Fig. 5.

where RZ1, YZ1, BZ1 are ground elements, RYZ1, Y BZ1, BRZ1 are phase elements and SC is

Ph. Element

RYZ1

Y BZ1

BRZ1

G. Element

RZ1

YZ1

BZ1

Trip SCT

Vr(t) Filter Vlth ≤ Vrf (t) ≤ Vuth

Vrf

Vy(t) Filter Vlth ≤ Vyf (t) ≤ Vuth

Vyf

Vb(t) Filter Vlth ≤ Vbf (t) ≤ Vuth

Vbf

Signal Not FitSNF

Smart TripST

Security Counter (SC)

Proposed

Latching Relay

Fig. 5 Adaptive blocking logic to prevent relay mal-operation

security counter. In order to perform this task, filter shown in equation (1) is used to extract the

unwanted information (Vrf , Vyf , Vbf ) from the voltage samples (Vr(t), Vy(t), Vb(t)) which are

obtained after prepossessing using anti-aliasing filter. The extracted information is compared

with both lower (Vlth) and upper (Vuth) bounds, since the output of PF (Vrf , Vyf , Vbf ) will be

almost zero during normal operating condition or when CVT transients dies out completely.

The performance of the proposed logic is tested for different fault types and loading conditions

for remote end faults. In addition to this, the real time performance of the proposed logic for

close-in faults is also tested.

8 / 16

5 Estimation of resistance for CVT with Electronic FSC

The transient response of instrument transformers affects the performance of high speed relays,

particularly speed and over-reach in case of distance protection. Transient response of CVT

depends on the type of FSC, provided in CVT secondary to damp the ferro resonant oscillations

as shown in Fig. 6. Fig. 7 shows the model of electronic FSC used in Fig. 6. In order to

C2

C1

SW1

CT

RC LC RT1 LT1

LTCRTC

RT2 LT2

RBFSC SW2

S1

S2

VR

VY

VB

Fig. 6 Detailed model of CVT

C1, C2 stack capacitance RC , LC tuning resistance and inductanceSW1, SW2 switches RB relay burdenRT1, LT1, CT , RTC , LTC , RT2, LT2 parameters of intermediate transformer

estimate this resistance (R), transfer function of the CVT shown in Figure 6 is obtained [5], but

without simplification as in [5]. The transfer function of CVT model is shown in equation (2)

R

Fig. 7 Model of electronic FSC

G(s) =N3s

3 +N2s2

D5s5 +D4s4 +D3s3 +D2s2 +D1s+D0

(2)

where N3, N2, D5, D4, D3, D2, D1 are the coefficients expressed by CVT parameters. The re-

quirement is to have low time constant, so that the protective relays are exposed to the actual

desired information immediately after fault inception. This is achieved by estimating damping

resistance (Rest) which will give low time constant by using equation (3).

TCmin = min

max(T1R, T2R, T3R, T4R, T5R)∣∣∣∣∣R=1,2,..,10000

(3)

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where T1R, T2R, T3R, T4R, T5R are the time constants of the transfer function G(s) for a partic-

ular value of damping resistance R. Figure 8 is obtained from equation (3), where maximum

100 101 102 103 10410−8

10−7

10−6

10−5

10−4

10−3

10−2

10−1

100

101

102

Damping resistance of electronic FSC (Ω)

Tim

econstan

t(secon

d)

T1 T2 T3

T4 T5

Rest = 15Ω

Fig. 8 Estimated damping resistance for CVT with electronic FSC

time constant of the transfer function is obtained for each value of resistance. The CVT with

estimated resistance for electronic FSC is tested for ferro-resonance and transient response test

[10] and the results are found within the limits. The performance of CVT is also tested in

real time. In addition to this, the performance of CVT with estimated resistance is also com-

pared with existing techniques for different source to line reach impedance ratio, fault types

and loading conditions.

6 Protection of Series Compensated Transmission Lines

Distance relay zone reach setting demands the knowledge of transient and steady state error to

ensure secure operation. The knowledge of this steady state error is important, as this gives

initial information regarding reach setting for ground and phase elements, above which the

transient errors are considered to decide the final reach setting in distance relay. From utility

perspective, it helps protection engineers to analyze the steady state relay behavior by pro-

viding the basic sequence impedance information, which is estimated for a particular tower

configuration. In order to analyze the steady state error and behavior of distance relays A, B,

C in the presence of series capacitor, test system shown in Fig. 9 is considered. Expressions to

estimate impedance for both with and without zero sequence mutual compensation are derived

considering different factors i.e., fault resistance, remote end in-feed, capacitor located at one

10 / 16

Bus M Bus S

ZSG1

δs

ZM G2

δr

RELAY A

VR,A, VY,A, VB,A

IR,A, IY,A, IB,A

CBA

ZL1 (LINE 1)

CBB C

MOV

RELAY B

VR,B , VY,B , VB,B

IR,B , IY,B , IB,B

Communication link

CBC

ZL2(LINE 2)

CBD

RELAY C

VR,C , VY,C , VB,C

IR,C , IY,C , IB,C

C

MOV

RELAY D

VR,D, VY,D, VB,D

IR,D, IY,D, IB,D

Communication link

F1m = 0 m = 1

IM IS

where,

G Generator δs Loading angle sending endZM ,ZS Source impedance ZL Line impedanceCB Circuit breaker m Fault location in puF Single phase to ground fault (SPGF) MOV Metal oxide varistorC Capacitor δr Loading angle receiving endIM In-feed from sending end for SPGF IS In-feed from receiving end for SPGF

Fig. 9 Conventional distance relay protecting SCPTL

G Generator δs Loading angle sending endZM ,ZS Source impedance ZL Line impedanceCB Circuit breaker m Fault location in puF1 Single phase to ground fault (SPGF) MOV Metal oxide varistorIS In-feed from receiving end for SPGF δr Loading angle receiving endIM In-feed from sending end for SPGF C CapacitorVR Voltage phasor estimated by relay IR Current phasor estimated by relay

end and for capacitor located at both ends. In order to assist the analytical expressions, the

actual relay behavior for two different tower configurations for each of the above mentioned

cases are discussed. The capacitors are assumed to be located at the end of the line, which is

mostly the case in real world scenario. This is due to the fact, that mid-point capacitors will

incur additional installation cost (if substation does not exist) when compared to capacitors

located at the end of the line. Out of the ten different fault types (3 SPGF, 3 phase to phase

fault, 3 phase to phase and ground fault and 3 phase fault), fault involving ground is chosen, as

the impact of coupling on distance relay is significant in zero sequence. SPGF is considered,

because probability of its occurrence is more when compared to phase to phase and ground

fault.

7 Summary and Conclusions

The work can be summarized as follows :

1. Distance relay assisting logics

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(a) Accelerated trip logic reduces the TFCT for balanced faults. This will not affectthe performance of existing schemes as there is no information exchange betweenAT logic and the present schemes. This logic is simple and is practically feasiblefor implementation without any hardware modification. Real time testing is carriedout for different fault locations to monitor its performance.

(b) Adaptive blocking logic blocks the distance relay mal-operation when transientsis detected and unblock the distance relay mal-operation when transients decay.Testing is carried out at high SIR for different fault types, loading condition. Inaddition to this real time performance of the logic is also verified for close-in faults.

2. Estimation of resistance for CVT with electronic FSC is done using transfer function ofdetailed CVT model. Real time testing is carried out to verify the performance of CVTwith existing method. In addition to this the performance of CVT with electronic FSC isanalyzed for different fault types, loading condition and SIR with existing FSC.

3. Analytical expressions are derived to estimate steady state error for different conditionsfor the protection of SCPTL.

The important conclusions of the work are:

1. Distance relay assisting logics(a) The advantage of the AT logic is suitable for system, where communication medium

is other than the fiber optic cable or if the medium fails. If stability is the majorconcern for the utility to switch to costly communication medium, then AT logicwill be a cost effective solution

(b) The adaptive blocking logic monitors the CVT transients directly in time domainunlike any other approach where the transients are indirectly monitored in fre-quency domain. This saves time to detect transients as transforming informationfrom time domain to frequency domain involves delay. Moreover, since the tran-sients are directly monitored, it does not need any SIR threshold which are auto-matically derived in background using relay settings

2. CVT with electronic FSCThe CVT with estimated resistance is tested for transient response test and ferroresonance test as per the standard and the errors are found within the limits. CVTwith electronic FSC shows better transient response when compared with existingtechniques. This results in distance relay exposed to actual primary fault informa-tion relatively fast and with less error. Analysis shows that the performance of CVTwith electronic FSC is better for high SIR, however the improvement is minimal

3. Steady state error in SCPTL protectionThe prior availability of sequence impedance information for relay setting helpsthe utility to estimate steady state error and study the relay behavior by direct sub-stitution. These expressions helps to provide primary information to the utility indeciding zone 1 reach setting, before considering safety factor for zone reach settingto accommodate transient errors.

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References

[1] G. Rockefeller, “Fault protection with a digital computer,” IEEE Trans. Power App. Syst.,vol. PAS- 88, no. 4, pp. 438–464, Apr. 1969.

[2] G. Ziegler, Numerical Distance Protection: Principles and Applications, 3rd ed. Erlan-gen: Wiley, 2008.

[3] ALSTOM. (2011) Micom P44x Technical Manual,. [Online]. Available:http://www.alstom.com/Global/Grid/Resources/Documents/Automation/Technical%20manuals/MiCOM%20Alstom%20P44x%20ver50K%20Manual%20GB.pdf

[4] “The effects of coupling-capacitor potential-device transients on protective-relay opera-tion,” Trans. of the American Inst. of Electr. Engineers, vol. 70, no. 2, pp. 2089 –2096,Jul. 1951.

[5] J. Izykowski, B. Kasztenny, E. Rosolowski, M. Saha, and B. Hillstrom, “Dynamic com-pensation of capacitive voltage transformers,” IEEE Trans. Power. Del., vol. 13, no. 1, pp.116–122, Jan. 1998.

[6] E. Pajuelo, G. Ramakrishna, and M. Sachdev, “Phasor estimation technique to reduce theimpact of coupling capacitor voltage transformer transients,” IET Generation, Transmis-sion & Distribution, vol. 2, no. 4, pp. 588–599, Feb. 2008.

[7] Y.-C. Kang, T.-Y. Zheng, S.-W. Choi, Y.-H. Kim, Y.-G. Kim, S.-L. Jang, and S.-H. Kang,“Design and evaluation of a compensating algorithm for the secondary voltage of a cou-pling capacitor voltage transformer in the time domain,” IET Generation, Transmission& Distribution, vol. 3, no. 9, pp. 793–800, May 2009.

[8] M. Davarpanah, M. Sanaye-Pasand, and F. Badrkhani Ajaei, “Compensation of cvt in-creased error and its impacts on distance relays,” IEEE Trans. Power. Del., vol. 27, no. 3,pp. 1670–1677, Jul. 2012.

[9] J. Sakamuri and D. Yesuraj, “Modeling and simulation of capacitor voltage transformertransients using PSCAD/EMTDC,” in PowerTech, Trondheim, 2011.

[10] Instrument transformers- Capacitor Voltage Transformers IEC 60044-5, IEC Standard60 044-5, 2004.

[11] C. E. Ugalde-Loo, J. B. Ekanayake, and N. Jenkins, “Subsynchronous resonance in aseries-compensated Great Britain transmission network,” IET Generation, Transmission& Distribution, vol. 7, no. 3, pp. 209–217, Mar. 2013.

[12] R. Folkers, “Determine current transformer suitability using EMTP models,” SchweitzerEngineering Laboratories, Inc., Tech. Rep., 1999. [Online]. Available: www.selinc.com

[13] V. Terzija, G. Preston, M. Popov, and N. Terzija, “New static "airarc" EMTP model oflong arc in free air,” IEEE Trans. Power Del., vol. 26, no. 3, pp. 1344 –1353, Jul. 2011.

[14] José R Marti, “Accuarte modelling of frequency-dependent transmission lines in elec-tromagnetic transient simulations,” IEEE Trans. Power App. Syst., vol. 101, no. 1, pp.147–157, Jan. 1982.

[15] Teleprotection equipment of power systems Performance and testing-Command systems,IEC Standard 60 834-1, 1999.

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8 Proposed Contents of the Thesis

The outline of the thesis is as follows:

Chapter 1 Introduction1.1 Power System Protection

1.2 Motivation

1.3 Objectives and Scope of the Work

1.4 Organization of the Thesis

Chapter 2 Overview of Transmission Line Protection2.1 Historical Background

2.2 Survey of Related Literature

Chapter 3 Power System Modeling in Alternate Transient Program3.1 Generator

3.2 Current Transformer

3.3 Capacitive Voltage Transformer

3.4 Arc

3.5 Bus Bar

3.6 Transmission Line

3.7 Circuit Breaker

3.8 Power System Model Validation

3.9 System Modeling for Series Compensated Parallel Transmission Lines

Chapter 4 Distance Relay Signal Pre-Processing4.1 Distance Protection Overview

4.2 Analog Signal Processing Unit

4.3 Digital Signal Processing

Chapter 5 Distance Relay Main Module-Hardware Implementation5.1 FPGA Basics

5.2 Design Flow

5.3 Distance Relay Development

Chapter 6 Accelerated Trip Logic for Balanced Fault with Tele-Protection6.1 Test System

6.2 Accelerated Trip Logic

6.3 Hardware Requirement Details

6.4 Performance of Accelerated Trip Logic

Chapter 7 CVT Transient Detection Logic7.1 Indirect Filters

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7.2 Direct Filters

7.3 Proposed Logic

7.4 Test System

7.5 Hardware Requirement Details

7.6 Performance of Transient Detection Logic

Chapter 8 Electronic Ferro-resonance Suppression Circuit8.1 Transfer Function of CVT model

8.2 Digital Testing of CVT model

8.3 Impact of CVT with Electronic FSC on Zone 1 reach

8.4 Real Time Testing and Validation

8.5 Performance Analysis of Electronic FSC

Chapter 9 Steady State Error Estimation in SCPTL9.1 Power System Model for SCPTL

9.2 Error Estimation with Capacitor at One End

9.3 Error Estimation with Fault Resistance

9.4 Error Estimation with Capacitor at Both Line Ends

Chapter 10 Conclusions

Appendix A Capacitor Voltage Transformer Data

Appendix B Transmission Line Data for Damping Resistance Estimation

Appendix C Current Transformer Saturation Data

Appendix D Bus Bar Capacitance

Appendix E Electronic FSC

Appendix F Passive FSC

Appendix G Budner’s Approach to Estimate Line Parameters as function of frequency

Appendix H Marti’s Approach to Estimate Line Parameters as function of frequency

9 Publications

9.1 Journal

Accepted

1. Venkatesh. C and K. S. Swarup, “Steady State Error Estimation in Distance Relay forSingle Phase to Ground Fault in Series-Compensated Parallel Transmission Lines,” IET,Generation, Transmission and Distribution, vol. 8, no. 7, pp. 1318-1337, Jul. 2014

15 / 16

2. Venkatesh. C and K. S. Swarup, “Performance Assessment of Distance Protection fedby Capacitor Voltage Transformer with Electronic Ferro-resonance Suppression Circuit,”Electric Power System Research, vol. 112, pp. 12–19, Jul. 2014

3. Venkatesh. C and K. S. Swarup, “Challenges and Developments in Numerical DistanceProtection,” The Journal of Central Power Research Institute, vol. 7, no. 1, pp. 23–32,Mar. 2011

Under 2nd Revision

1. Venkatesh. C and K. S. Swarup, “Estimation of Electronic Suppression Circuit Resis-tance for Protective Relaying Applications,” Electric Power Components & Systems(2014)

Communicated

1. Venkatesh. C and K. S. Swarup, “Adaptive Blocking Logic to Prevent Distance RelayMal-operation,” IEEE PES letters (2014)

9.2 Conference

International

1. Venkatesh. C and K. S. Swarup, “Faulty Line Identification by Distance Relay In Series-Compensated Parallel Transmission Lines,” in IEEE Power and Energy Society GeneralMeeting 2014, Washington DC, Jul. 2014

2. Venkatesh. C, K. S. Swarup and Prasath. S. V, “Smart Trip Logic for Smart Grids toBlock Distance Relay Mal-operation - Implementation and Validation,” in IEEE Innova-tive Smart Grid Technologies - Asia (ISGT Asia), Bangalore, Nov. 2013

3. K. Yashwant, Venkatesh. C and K. S. Swarup, “An Open Source Framework for IEC61850 based Protection and Automation Schemes,” in IEEE Innovative Smart Grid Tech-nologies - Asia (ISGT Asia), Bangalore, Nov. 2013

4. Venkatesh. C and K. S. Swarup, “Insights into testing and validation of dc offset removalfilters in numerical distance protection,” in Annual IEEE India Conference (INDICON),Kochi, Dec. 2012

5. Venkatesh. C and K. S. Swarup, “Investigating performance of numerical distance relaywith higher sampling rate,” in 44th IEEE North American Power Symposium, Illinois,Sept. 2012

National

1. Venkatesh. C and K. S. Swarup, “Investigating Performance of Symmetrical ComponentDistance Relay,” in 17th National Power System Conference, U.P, Dec. 2012

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