Deep Sub Micron Issue

8/8/2019 Deep Sub Micron Issue

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16. Deep Submicron Issues

J. A. Abraham

Department of Electrical and Computer Engineering

The University of Texas at AustinEE 382M, VLSI I

Fall 2010

October 25, 2010

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 1 / 23



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Ideal Transistor I-V

Shockley first-order transistor models

I ds =

0 V gs < V t cutoff

β

V gs − V t − V ds2

V ds V ds < V dsat linearβ 2

(V gs − V t)2 V ds > V dsat saturation




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Ideal nMOS I-V Plot

180 nm TSMC process

Ideal Modelsβ = 155(W/L) µA/V 2

V t = 0.4 V V DD = 1.8 V




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Simulated nMOS I-V Plot

180 nm TSMC process

BSIM3 3V3 SPICE models

What differs?Less ON currentNo square lawCurrent increases insaturation




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Velocity Saturation

We assumed carrier velocity ∝ E-field

ν = µE lat = µV ds/L

Carriers scatter off atoms

Velocity reaches ν satElectrons: 6− 10× 106

cm/sHoles: 4− 8× 106 cm/s

Better model

ν =µE lat

1 + E latE sat

=⇒ ν sat = µE sat




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Velocity Saturation I-V Effect

Ideal transistor ON current increases with V

2

DD

I ds = µC oxW

L

(V gs − V t)2

2=

β

2(V gs − V t)

2

Velocity-saturated ON current increases with V DD

I ds = C oxW (V gs − V t)ν max

Real transistors are partially velocity saturated

Approximate with α-power law model

I ds ∝ V αDD

1 < α < 2 determined empirically




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α-Power Model

I ds =

0 V gs < V t cutoff

I dsatV dsV dsat

V ds < V dsat linear

I dsat V ds > V dsat saturation

I dsat = P cβ

2(V gs − V t)

α

V dsat = P ν (V gs − V t)α/2

α, β , P c and P ν areparameters determinedempirically from a curve-fit of I-V characteristics




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Channel Length Modulation

Reverse-biased p-n junctions form a depletion regionRegion between n and p with no carriers

Width of depletion Ld region grows with reverse biasLeff = L− Ld

Shorter Leff = more currentI ds increases with V dsEven in saturation


C



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Channel Length Modulation I-V

I ds =β

2(V gs − V t)

2(1 + λV ds)

λ = channel length modulation coefficientNot feature sizeEmpirically fit to I-V characteristics


B d Eff



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Body Effect

V t: gate voltage necessary to invert channelIncreases if source voltage increases because source is

connected to the channelIncrease in V t with V s is called the body effect

Body Effect Model

V t = V t0 = γ φs + V sb − φsφs = surface potential at threshold

φs = 2ν T ln(N Ani )

Depends on doping level N AAs well as intrinsic carrier concentration ni

γ = body effect coefficient

γ =tox

ox 2qSiN A =

√2qSiN A

C oxECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 9 / 23

OFF T i B h i



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OFF Transistor Behavior

What about current in cutoff?

Simulated results don’t match measurements

What differs?Current doesnt go to 0 in cutoff


L k S



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Leakage Sources

Subthreshold conduction

Transistors can’t abruptly turn ON or OFF

Junction leakage

Reverse-biased PN junction diode current

Gate leakage

Tunneling through ultrathin gate dielectric

Subthreshold leakage is the biggest source of leakage inmodern transistors

Subthreshold Leakage

Subthreshold leakage is exponential with V gs

I ds = I ds0eV gs−V tnνT

1− e

−V dsνT

, I ds0 = βν 2T e

1.8

n is process dependent, typically 1.4 – 1.5


Oth L k S



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Other Leakage Sources

Drain-Induced Barrier Lowering (DIBL)

Drain Voltage also affects V t (V t = V t−

ηV ds)

High drain voltage causes subthreshold leakage to increase

Junction Leakage

Reverse-biased p-n junctions have some leakage

I D = I S

eV

DνT − 1

I s depends on doping levels

As well as area and perimeter of diffusion regionsTypically < 1 fA/µm2


G t L k g



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Gate Leakage

Carriers may tunnel thorough very thin gate oxides

Negligible for olderprocesses

Becoming criticallyimportant for nanoscaletransistors

However, use of metalgates and rare-earth

dielectrics (Hf) mayreduce this significantly

Predicted tunneling current (from Song, 2001)


Temperature Sensitivity



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Temperature Sensitivity

Increasing temperatureReduces mobilityReduces V

tI ON decreases with temperatureI OFF increases with temperature


So What?



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So What?

So what if transistors are not ideal?

They still behave like switches, and isn’t that enough fordigital logic?

But these effects matter for . . .

Supply voltage choiceLogical effortQuiescent power consumptionPass transistorsTemperature of operation


Parameter Variations



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Parameter Variations

Transistors have uncertainty in parameters

Process: Leff , V t, tox of nMOS and pMOS

Vary around typical (T) values

Fast (F)Leff : shortV t: lowtox: thin

Slow (S): opposite

Not all parameters are independent for nMOS and pMOS


Environmental Variation



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Environmental Variation

V DD and T also vary in time and space

Fast:

V DD : high

T : lowCorner Voltage Temperature

F 1.98 0

T 1.8 70

S 1.62 125


Process Corners



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Process Corners

Process corners describe worst case variations

If a design works in all corners, it will probably work for any

variationDescribe corner with four letters (T, F, S)

nMOS speedpMOS speedVoltage

Temperature

Important Corners

Some critical simulation corners include

Purpose nMOS pMOS V DD TempCycle time S S S S

Power F F F F

Subthreshold leakage F F F S

Pseudo-nMOS S F ? ?


Causes of Variations?



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Causes of Variations?


Features Smaller than Wavelengths



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Features Smaller than Wavelengths

What is drawn is not what is printed on silicon

Source: Raul Camposano, Synopsys


Random Dopant Fluctuations



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Random Dopant Fluctuations


Dynamic Temperature Variations



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Dynamic Temperature Variations

Thermal Map – 1.5 GHz Itanium Chip


Dynamic Voltage and Power Variations



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y g


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