Deep sub-micron chip development

Nov 7-11, 2005 Vertex 2005 @Nikko, H.Ikeda ISAS, JAXA

1

Deep sub-micron chip development

Hirokazu IkedaInstitute of space and astronautical scienc

eJapan aerospace exploration agency


2

HII-A MV

MV, ISAS

HII-A, JAXA


3

Contents for Talk

1. Introduction2. Multi-chip project available in

Japan3. Open-IP4. 4096-channel pixel array5. TEG for FD-SOI CMOS6. Summary


4

Benefit of sub-micron CMOS are:

Deep sub-micron CMOS: could be defined as CMOS whosefeature size is smaller than 0.5 um and which no more sustainsa power supply voltage of 5.0 V.

1) Increase in number of transistors on a chip2) Improvement of functionality of LSI’s3) Increase in switching speed of MOSFET’s and circuits4) and, hence, improvement of operation speed of LSI’s5) Decrease in cost of LSI’s per performance6) Steep increase in radiation hardness (total doze) (enclosed structure assists to improve radiation hardnes

s.)

1. Introduction


5

TMC1004,0.8 um CMOS, NTT

TMC-X0.18 um CMOS30 ps/bit

Trend for TMC


6

Academicinstitutes

2. Multi-chip project available in Japan

VDEC(operated

by University of Tokyo)

1.2 um (ON SEMI.)0.35 um (ROHM)

0.18 um (Hitachi)

MOSIS 0.25 um (TSMC)

0.18 um (TSMC)0.5 um SiGe (IBM)

+ direct submission to MOSIS+ private multi-chip project

0.15 um SOI (OKI)0.09 um (ASPLA)

VLSIDesign &EducationCenter


7

VDEC provides1) LSI chip fabrication…… multi-chip project2) Test and measurement support……logic tester, EB prober, FIB facility, and etc.3) CAD software tool support……Cadence, Mentor, Synopsys, Silvaco, and etc.4) Lecture course for LSI design


8

3. Open-IP

Even with these availability of design tools, there exists a big hurdle for beginners to design an integrated circuit from scratch. In order to lower the hurdle, a circuit library (IP) is extracted from existing designs, and constructed to show known circuit topologies together with more or less realistic W/L values.

Available for research use.Expanded by users’ effort.

KEK, ISAS

FB elements

Amplifier elements


9

Employing OPEN-IPTohoku university is developing a pair monitor system for ILC. The pair monitor employs a 3-D detector as a sensor. 　 The readout chip is configured as a pixel chip. Each pixel circuit includes a preamplifier, shaping amplifier and 　 comparator. The shaping amplifier has a peaking time of 100 ns and a decay time of 200 ns to be compatible with the micro-bunch structure with noise level better than 1000 e’s.The output of the comparator is fed into a Gray-coded 8-bit counter, 　 whose counts are latched 16 times during the beam burst and, then, read out during intermittence of the beam burst. A prototype chip is designed in a 0.25-um rule to be submitted to TSMC.

Tohoku, ISAS


10

Employing OPEN-IPTokyo metropolitan university is developing an aerogel Cherenkov detector system for Super B-factory experiment. The two-dimensionally segmented hybrid avalanche photo detector 　 acquires a ring image emitted from the aerogel radiator when charged particles pass through. An analog chain is designed to achieve a noise level of 1500 e for a detector capacitance 80 　 pF of the avalanche diode. 　 The peaking time of the analog signal is adjustable in a 　 range of 0.5 us to 2 us. 　 The output of the analog chain is 　 fed in to a comparator,　 and, then, to a shift register chain to compensate for a trigger latency. The readout is only in binary. A prototype chip is designed in a 0.35-um rule to be submitted to ROHM.

π or KSilica aerogel（ 1 ～ 2cm ）

Pixelized photo detector

0.5<p<4.0 GeV/c

Injection gain: 1000Avalanche gain: 10Total: 10000

TMU, KEK etc.


11

Employing OPEN-IPNagoya university is developing a TOF system for a TOP (Time of propagation) detector. The TOP detector is a sort of a Cherenkov detector to measure time differences and geometrical positions of photons at the end of a quartz bar to reconstruct a Cherenkov image in a space-time coordinate. The geometrical coordinate is measured by a position sensitive photo-multiplier or a micro-channel plate, whose outputs are fed into a TAC chip. The TAC chip includes a leading-edge and/or a constant-fraction comparator channels to be fed into TAC circuits. The TAC circuit is configured as a dual system to be operated with 10-MHz bi-phase gates with an overlap of 25 ns. The time resolution envisaged is 20-30 ps. The TAC chip is designed in a 0.35-um rule to be submitted to ROHM.

10 ns 20 ns 30 ns

Nagoya, KEK etc.

Preliminary


12

Employing OPEN-IPOsaka university is developing 　 a CCD readout system for the X-ray astronomy. A CCD detector shows a superior nature in noise, but has a drawback in terms of A 　 readout speed. In order to improve the resolving time, they plan to employ a parallel readout CCD together with a multi-channel readout VLSI. A test chip is designed to reproduce an existing performance with a discrete circuit. The noise level envisaged is an order of less than 10 electrons. The test chip includes two channels of a complete integrator, hold circuit, and 12-bit 　 Gray- coded Wilkinson A-to-D converter. A double-correlated subtraction is carried out in off-line. The test chip is design in a 0.25 um rule to be submitted to TSMC.

CCD BufferV-I/Integration/HOLD

ADC

12-b*2output

Osaka, ISAS

Preliminary Preliminary


13

3. 4096-channel pixel arrayInstitute of space and astronautical science 　 is

developing a two-dimensional analog VLSI for 　 readoutof pixel sensors based on silicon (Si) or cadmium telluride (CdTe) for a future use of spectroscopic imaging observations in X-ray and 　 gamma-ray region.

The chip consists of four 8 mm-by -8 mm sub-chips .The entire chip can be operated either sequentially or independently for each sub-chip, depending on the readout speed requirement.. In the upper left corner 　 of the pixel layout there is an octagonal bonding pad with a diameter of 50 um.

ISAS


14

4096-channel pixel array: signal processing

The amplifier array consists of a charge sensitive preamplifier, shaping amplifier(FAST and SLOW), peak-hold circuit, and analog multiplexor circuit together with a test-pulse circuit, analog-monitor circuit and digital-control circuit.


15

In order to maintain low-noise characteristics

1) One is the insertion of capacitors between the gate and drain nodes of a current mirror to slow down the frequency band-width of the bias voltage generation circuit. 2) Another is the employment of an RC filter for the gate of the current source of the CSA circuit. The RC filter consists of an off-transistor for R, and a MOS capacitor for C. 3) The third measure is related to a digital-to-analog interference. We employed a deep N-well process to electrically isolate the analog circuit from the nearby digital circuits. Eventually the electronic noise is suppressed down to 100 electrons (rms) or less for a CdTe pixel X-ray detector.

1) Base lines of amplifiers are raised or lowered by 400 mV, which assumes thatthe preamplifier is only dedicated to a positive charge. 2) In a similar context, medium VT transistors are employed almost everywhere except for in logic gates, switches and constant current sources.

In order to cope with low power rail voltage


16

1) Latchup immunity2) Higher packing density3) Higher speed performance4) Lower power consumption5) Lower leakage current6) Reduced short-channel eff

ects7) Wide voltage /temperature

operation range9) Lower processing cost

1) Floationg body phenomena2) Parasitic effects3) Degraded heat dissipation 4) Availability and cost of the substrate5) Processing difficulties on the thin film substrates

5. SOI TEG Fabrication

KEK, ISAS etc.

PROS

CONS


17

Entering into late 1990's, the trend curve of a bulk CMOSprocess tends to go behind the Moore's law, and, hence, the manufactures are eager to find a way to recover development speed. SOI CMOS is then revisited toreveal its performance over an existing bulk CMOS; the SOI CMOS eventually shows up as a successor of the CMOS process inheriting well-matured fabrication technologies for a bulk CMOS. 　　

SOI of OKI

The fabrication process for our TEG design is a 0.15 um FD-SOI CMOS process from Oki electric industry Co., Ltd. In comparison with a PD (partially depleted) SOI, the FD (fully depleted) SOI employs a thinner silicon layer, and , then, the silicon layer underneath the gate electrode is completely depleted. The kink effect, which is revealed for the PD SOI, is moderated for the FD SOI. An improvement for the threshold slope parameter assists for us to employ a low VT transistor for an analog circuit design.

FD （ fully depleted ） -SOIThickness: less than 50 nm

Depleted region


18

Amplifier Feedback

CHAIN1

16 fC

I fC

Large currentSmall current


19

CHAIN2 CHAIN3


20

The TEG circuit includes a bufferamplifier for a monitoring purpose,AC-coupling circuit, differential amplifier(slow/fast/medium) and comparator.

CHAIN4


21

LAYOUT of the TEG design

2.4 mm

2.4 mmBias circuit

CHAIN4

CHAIN1

CHAIN3

CHAIN2


22

1) Deep sub-micron CMOS processes have been widely employed forhigh energy physics, astrophysics, and other use.2)Japanese activities for the deep sub-micron CMOS integrated circuits are discussed, one of which is a 4096-channel pixel array that is designed and fabricated for future use in the area of astrophysics.The noise level better than 100 e's is envisaged with incorporatingexperiences/ideas obtained so far. 3) In order to go beyond existing technologies for an FE circuit design, we initiate a design work with an FD SOI process from Oki electric industry Co., Ltd. 4) We have submitted a TEG design to identify if we can still employ design practices for a deep sub-micron CMOS, or need to incorporate technologies exploited/devised in other research fields.

6. Summary


23

高速時間計測回路の実現へ向けて

TAC Duplex

Constant-fraction discriminator

(ROHM 0.35-um CMOS)


24

Introduction

TOP (Time-of-Propagation) Counter　・ New type of ring-imaging Chrenkov counter　・ Possible next-generation particle-identification device at the KEKB-factory Belle experiment ・ Measure time difference and geometrical positions of photons at the end of a quarts bar to reconstruct a Cherenkov ring image in a space-time coordinate ・ Geometrical coordinate is measured by a micro-channel plate (MCP)


25

IC Design• TAC （ Time-to-Amplitude Converter ）・ Dual system to be operated with 10MHz bi-phase gates with an overlap

of 25ns• Time-walk correction　　・ Leading Edge(LE) comparator

　　・ Amplitude and Risetime Compensated （ ARC) comparator

• Designed in a 0.35 μm rule submitted to ROHM by a multi-chip project provided by VDEC (VLSI design and education center)

AMP AMPAMPAMPAMPAMP LVRIN OUT

AMP

AMP AMPAMPAMPAMPAMP LVR

TH

IN OUT


26

High-Speed Timing Circuit

• SYNC signal check by changing CLOCK frequency and duty ratio

・ Operation is possible at 50 MHz ・ At 40MHz : duty ratio 56-60% SYNC 信号

CLOCK 信号

Preliminary


27

Linearity and Time Resolution

Time resolution as a function of delay

・ 30-50 ps is achieved by the current chip

• Correlation between TAC output and delay ・ Measure TAC output by 2 channel to cancel out same jitter ・ Clean linearity is observed

Preliminary

Preliminary


28

完全積分回路＋ホールド回路＋ Willkinson 型 A/D (Gray code) 12 bit , 167 MHz

Binary

Gray

完全積分回路

マルチポート CCD 読出し回路の開発


29

M01 チップ COB にパッケージング

評価基板との組み合わせCCD amp2重相関サンプリング ADC 出力

12ビット

チップ内

M01 チップの仕様CCD の信号処理を目的として開発－チップサイズ 2.5 mm × 8 mm－ CCD からの入力信号を積分する積分回路－ 12 ビットの AD 変換回路（ウェルキンソン方式）－２ｃｈ分の処理回路を実装

M01 チップレイアウト図

M01 チップの回路ブロック（ 1ch 分）

評価基板との組み合わせ


30

動作確認

channel

cou

nts

取得イメージ

得られたスペクトル

入力電圧

ランプ信号用ゲート信号

積分回路用ゲート信号

ランプ信号

積分回路信号

WIDTH 信号

Preliminary


31


32


33

HIGH GAIN


34

LOW GAIN


35

0 1 2 3 4 5


36


37

CHAIN1

160 mV

3 us

Output buffer


38

CHAIN2

AC-coupling comparator

3 us

200 mV


39

CHAIN3

Differntal amplifier(slow)

Threshold circuit

閾値設定回路

1 us

230 mV


40

CHAIN4

Differntial amplifier(meduim) Differntil amplifier(fast)

62 mV

1 us


41

More about CHAIN4


42

差動増幅回路


43

コンパレータ回路


44

E/43

Documents

Deep sub-micron chip development