Data Processor Status Hardware

Data Processor StatusHardware

Giuseppe Osteria INFN Napoli

Paris, October 12, 2012 Euso Balloon 8th progress meeting Giuseppe Osteria INFN Sezione di Napoli

2

OUTLINE DP reminder

DP external interfaces DP internal interfaces

DP sub-assemblies status CPU & DST CLK board GPS receiver DP box

DP pre-integration test DP Software Status & dev. plan

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Data Processor subassembly itemsThe DP functionality is obtained by connecting

different specialized items, which form a complex system.

The main subassembly items are: Control Cluster Board (CCB) Main processing unit (CPU) Data Storage (DST) Housekeeping system (HK) Clock Board (CLKB) GPS receiver (GPSR) Data Processor Power Supplies (DP-LVPS1-2-3) PDM Power Supply (PDM-LVPS)

28V DPLVPSs

vSpaceWire

5V

Ethernet

vSATAData

Storage

Visible cam(adv. opt.)

SpaceWire

to PCI

v PCI

GPS

vHK

system

v5V

5V

28V

CLKs, Sync, Trig, Busy

RS232

PDMbox

vRS422

12V, 5V

RS 422

Anal

og (V

, T)

Fast

par

alle

l lin

k S

PI

PWP

V, T

mon

. SPI

12V

CCB

CPU

IR Camera

(adv. opt.)

CLKboard

SIREN syste

m

vSpaceWire

V, A Monitor

1PPS

TLS

Anal

og (

T)

Analog ( T)

RelaysHL-CMD CC

Data Processor block diagram

5

External interfaces DP-SIREN

CPU-Siren data telemetry interface Ethernet

HK-Siren command interface RS422 (level adapter to

RS232) Open drain (switch ON/OFF)?

DP-TLS HK-lenses/structure

Temperature sensors (analog) heaters?, motors?, other?

(TBD)

External interfaces DP- PDM

CCB-PDM-board data/cmd interface (OK!) Parallel data link (40 MHz, 8 bit) PDMCCB SPI (2 MHz) for commands CCBPDM Clock/Control signals• Broadcast signal (external trigger)

HK-PDM-board (OK) SPI (2 MHz) (Volt.,Temp.)

HK-HV system (OK!) DP- PWP

LVPS-PWP (TBC)

Internal interfaces CPU- CCB (OK!)

SpaceWire data/command interface CPU- CLK board (OK!)

SpaceWire data/command interface CLKboard-CCB (OK!)

Clocks, Time Sync, 2nd level trigger, Busy, Broadcast signal

CPU-HK (OK!) RS422 data/command interface Temp. sensors (TBC)

HK- CLKboard, CCB, GPS (OK!) SPI (2 MHz) (Voltages,Temp.) Alarm and Reset Lines

DP_LVPS- CPU, DST, CCB, CLKboard, GPS (OK!)

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Data processor subassembly – CPU -Description

Arbor iTX-i2705 2 x OCZ 512 GB SSD diskSpaceWire PCI Mk2

+ +

+Riser card

Data Processor subassembly –CPU-Frame-type plug-in units 3D model

9SpaceWire boardArbor board metal sheet

SATA disks

Data processor subassembly – CPU -Status

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CPU mounted in the Frame-type plug-in units

Arbor iTX-i2705

Power

SpaceWire PCI Mk2

RS422

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Data processor subassembly – CLKB -Description:

The clock signals are transmitted to the CCB by using differential LVDS point-to-point connections.

The FPGA will host the following interfaces to: GPS receiver through a RS232 port (NMEA protocol). 1PPS pulse of the GPS receiver in order to synchronize, at level of 1 GTU, the

apparatus with the UTC time. CPU (Command and data interface via Space Wire) HK (HK parameters: SPI serial protocol )

Form factor: 3U Euro card (160 mm x100 mm x 25 mm )

An FPGA Xilinx Virtex5 XC5VLX50T (Industrial grade) will be used to implement all the required functionalities of the board.

Master clock: 40 MHz Temperature Compensated

Crystal Oscillator frequency stability of +/-1 ppm in the

temperature range of -40°C to +85°C.

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Data processor subassembly – CLKB -Status

Prototype fully tested OK

Connectors mounted and tested

CLKB mounted in the Frame-type plug-in units

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Data processor subassembly – GPSR –Description: GPSR candidate is based on the SiRFstarIII™ 20-

channel GPS SMD compact module/receiver The ISM300F2-C5-V0004 module is

programmed with HIGH ALTITUDE BUILD, and works at cold temperatures for ballon applications.

Maximum altitude of 42000 meters (137795 ft) Avalaible interfaces:

SiRF Binary at 57600 baud on port A NMEA at 4800 baud on port B 1 PPS output

ITAR-free component

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Data processor subassembly – GPSR –status:Optimized version of the GPSR board equipped with ISM300F2-C5-V0004 chip(3U EuroCard board with power supply, interfaces, connectors , etc, optimized respect o the evaluation board)produced and fully tested OK

GPRS connectors mounted and testedGPRS mounted in the Frame-type plug-in units

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Data processor subassembly – GPSR –Test (failed) and development plane: The Inventek GPS receiver has been tested at CNES in June

and in October with two GPS constellation simulators . The last test demonstrate that the chip stops to transmit GPS

coordinates at altitude grater then 18 km. Inventek GPSR cannot be used for the balloon flight (ok forTA) A new GPS receiver (Motorola Oncore M12 card) has been

suggested by CNES people The new card will be integrated in a new board and tested as

soon as possible at CNES (December?) In case of successful test the Motorola chip the new board

will be considered the baseline GPS receiver of the mission. New GPS receiver board tests will be performed by using the

prototype of the CLK board. Testing shall be completed by the end of November2012

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DPLVPS2

DPLVPS3

DPLVPS1

PDMLVPS CCB GPSR CLKB

HK CPU

Data Processor: - DP box –3D model - Front view

Data Processor: - DP box – Status

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DP box ready to host modules

Data processor pre-integration testCPU – CLKB interface (SpaceWire)

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Test performed:• GPSR receiving GPS signal from

antenna• GPSR board connected with

CLKB• GPS NMEA strings transmitted

to CLKB from GPSR once per second

• GPS NMEA string transmitted on request from CLKB to CPU through SpW link Setup used to test the SpW interface

Test performed by using Star Dundee software.Transmission of reading commands from CPU to CLKB and consequent sending of data from CLKB to CPU successfully performed at 200 Mbit/sec .

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Data Processor pre-integration testTest in vacuum chamber (preliminary)

DP box with CPU, CLKB and GPSRin vacuum chamberPower supply currents monitoredEthernet connection (remote control)Mother board sensors monitored3 external thermal sensors

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Data Processor pre-integration testTest in vacuum chamber

Preliminary testLess than two hours at 3 mbar with the whole system powered.First time in vacuum for GPSR, CLKB and SpaceWire board MK2.Setup:Temperature sensors on GPSR, CLKB and SpW board.CPU temperature monitored by reading the Core temp.GPSR receiving GPS signal from antennaGPSR board connected with CLKBGPS NMEA strings transmitted to CLKB from GPSR once per secondGPS NMEA strings transmitted on request from CLKB to CPU through SpW link at 200 Mbit/sec .

0 50 100 150 200 250 3002030405060

Temperature on external sensors

Time [minutes]

Tem

pera

ture

[°C

]

0 50 100 150 200 250 3001

10

100

1000

10000

Pressure

Time (minutes)

TiPr

essu

re (m

bar)

• Power supply currents almost stable• Temperature max reached 58 °C (CPU

core)

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Data Processor pre-integration testCPU – HK interface (RS422)

Arduino MEGA 2560 board purchaised in Naples andequipped with a shield for differential signals (RS422 and SPI interfaces)

Setup used to test RS422 CPU communication port

Arbor board serial port configured as RS422 and communication with corresponding port of the Arduino Mega 2560 successfully tested at 19200 bauds

Data Processor pre-integration testCCB – CPU interface

C. De Santis, N. De Simone and A. Pesoli tested the CCB to CPU comunication in Tubingen with G. Distratis, C. Tenzer, J. Bayer.

Tests done in 24th-28th September 2012

CPU & Spacewire Rome system (same as flight ones) with no SSD disks.

CLK and PDM boards emulated.

12/10/20128th Progress Meeting, Oct. 2012, Paris

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Data Processor pre-integration testCCB – CPU interface CCB data format:·

in order to improve data-rate performance all GTU frames will be transmitted together; A single data packet of estimated size ~ 332 KB will be transmitted.

CRC chosen: CRC-32 IEEE 802.3 (Ethernet), with inverted packet input (bitwise), inverted output (bitwise)

Several configuration parameters have been extensively tested (FIFO size, transmission speed, transmission delay) to find the best data transfer rate.

In the standard nominal SpaceWire configuration (200 Mbit/s CCB TX interface) the data-rate obtained writing to a standard SATA disk: 17.11 MB/s (real time) 21.36 MB/s (CPU time)

A list of message types defining command exchange from CPU to CCB and PDM (via CCB) has been defined.

A command running counter will be included to check the command transmission integrity (CPU command counter must be the same as the CCB one).

A list of commands needed by the CCB has been defined. No packet retransmission will be implemented. Retransmission cost a lot of CCB-

FGPA resource No transmission errors found during the test.


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Data Processor pre-integration testCLKB – CPU interface

N. De Simone and A. Pesoli tested the CLKB to CPU comunication in Naples with V. Scotti and me.

Tests done in 8th-10th October 2012

Flight CPU, disks and Spacewire system used.

Real CLKB and emulated CCB were acquired together simulating a real acquisition procedure


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Up to 48 CCB (332 kB) + CLKB (0.8 KB) pkt/s were transferredBetter result respect the performance of Star Dundee software.

Data Processor pre-integration testCLKB – CPU interface CLKB data format:·

in order to improve data-rate performance all CLKB will be transmitted together; A single data packet of estimated size ~ 0.8 KB will be transmitted.

CRC chosen: CRC-32 IEEE 802.3 (Ethernet), with inverted packet input (bitwise), inverted output (bitwise)

Several configuration parameters have been extensively tested (FIFO size, transmission speed, transmission delay) to find the best data transfer rate.

In the standard nominal SpaceWire configuration (200 Mbit/s CLKB TX interface) the data-rate obtained writing to the two SSD disks in raid configuration : 46-48 data packets per second - 18 -19 MB/s (real time)

A list of commands needed by the CCB has been defined. No transmission errors found during the test. A system able to emulate CCB and CLKB sending packets at 200 Mbit/s at

selectable rates has been implemented by V. Scotti on a Virtex emulation board . The system is now available in Rome and will help in the developing and improving of the acquisition software.


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Software Status & dev. plan There are now two working system

(CPU+SpaceWire) in Naples & Tor Vergata. Naples, Tor Vergata & Bari, drafting project

architecture and design. Focus has been put on the validation and test of the

hardware interfaces and software drivers. Spacewire PCI interface has been tested and

validated in a Linux OS environment. Spacewire communication between CCB and CPU

and CLK and CPU has been tested and validated. RS422 communication between HK and CPU has

been tested and validated using an Arduino board. Data and command format for CCB has been frozen.

12/10/20128th Progress Meeting, Oct. 2012, Paris 26

DUI

HWI

DUI

HWI

JEBControl

RUI

HWI

RUI

HWI

RUI

HWI

RUI

HWI

RUI

HWI

TUI

HWI

Data Manager

Log Manager

Control ManagerRun Control

Configuration Manager

Event Builder

Message ManagerCMD

CMD

CMD

CMD

CMD

CMD

CMD

UI

CMD

CMD

CMD

CMD

CMD

CMD

CMD

Data

(Mem

ory

pool

)

CCB

HK System

CLKboard

Storage

Visible cam (adv. Opt.)

IR Camera(adv. Opt.)

Telemetry system

Console, remote

access, etc.

DATA

DATA Data stream

(GbE, GSE, etc.)

DATA

DATA

DATA

DATA

DATA

DATA

Mes

sage

Bus

ALARM

DP software blocks scheme


Hardware Interfaces & drivers

27

DUI

HWI

DUI

HWI

JEBControl

RUI

HWI

RUI

HWI

RUI

HWI

RUI

HWI

RUI

HWI

TUI

HWI

Data Manager

Log Manager



Event Builder

Message ManagerCMD

CMD

CMD

CMD

CMD

CMD

CMD

UI

CMD

CMD

CMD

CMD

CMD

CMD

CMD

Data

(Mem

ory

pool

)

CCB

HK System

CLKboard

Storage



Telemetry system

Console, remote

access, etc.

DATA

DATA Data stream

(GbE, GSE, etc.)

DATA

DATA

DATA

DATA

DATA

DATA

Mes

sage

Bus

ALARM



Hardware Interfaces & drivers tested

28

DUI

HWI

DUI

HWI

JEBControl

RUI

HWI

RUI

HWI

RUI

HWI

RUI

HWI

RUI

HWI

TUI

HWI

Data Manager

Log Manager



Event Builder

Message ManagerCMD

CMD

CMD

CMD

CMD

CMD

CMD

UI

CMD

CMD

CMD

CMD

CMD

CMD

CMD

Data

(Mem

ory

pool

)

CCB

HK System

CLKboard

Storage



Telemetry system

Console, remote

access, etc.

DATA

DATA Data stream

(GbE, GSE, etc.)

DATA

DATA

DATA

DATA

DATA

DATA

Mes

sage

Bus

ALARM



Spacewire Interfaces

29

RS422 Interface

DP Sw. Document Status


The Software Specification and requirement document table of contents.1. Scope of the document2. Documentation2.1 Applicable documents2.2 Glossary

General introductory parts.

3. Introduction General description of the DP and its role in the instrument.

4. The DP unit4.1 The CPU4.2 The CLK board4.3 The CCB board4.4 The HK board

Detailed description of the DP unit and components connected to the CPU, along with the interfaces between blocks. Functional modes are sketched as well.

5. Software description5.1 Single block description5.2 Readout Unit Interface (RUI)5.3 Data Unit Interface (DUI)

Detailed description of the software overall project along with the one for the single functional block or interface.

6. Software functional requirements The list of the software functional requirements. It could be

subdivided into chapter for each component.

7. Software specifications The list of the software specifications. It could be subdivided into chapter for each component.

8. User’s scenarios A list of user’s scenarios.

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Software Status & dev. plan After the test of the interfaces and a better

definition of the CCB working modes, a review of the general architecture will be done, to accommodate the result of the tests done in Tubingen and Naples. The will reflect also the data and command formats.

The low level protocols has been fixed and we can work on the higher level processes.

The definition of the full command and configuration parameter lists needed by HK, CCB, PDM and ASICS, is in progress.

12/10/20128th Progress Meeting, Oct. 2012, Paris 31

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DP integration plane The first step of the integration will regard the LVPS modules, the

HK and the CPU. During this phase, after the verification of all the mechanical and electrical compatibilities, the communication between CPU and HK system on the RS422 port will be faced and tuned. (HK configuration, switch-on/off sequence etc etc)

The second step will be the introduction in the system of the CLK board and GPS board in order to test the relative LVPS and to verify the SPI interfaces HK-CLKb and HK-GPSb. The interface CLKb-GPSb with the two boards powered by the LVPS will be tested too.

The third step will be the introduction in the system of the CCB. Also in this case we have to test mechanical and electrical compatibilities, the interface with CLKb in order to provide a clock to the board and all the ancillary functionality.

The fourth step will be the test of the the SpaceWire interface and the full simulation of the different operational mode of the system.

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Data Processor:Frame-type plug-in units 3D model –CLKb-

CLK board metal plates

35

Data Processor:DP box 3D model – Rear view

Cooling plate

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Data Processor:DP box 3D model – CLK board and CPU

Cooling plate

CPU

37

Data Processor:Budgets

Mass (kg) Size Power budget (W)

Sub_system Measured Estimated Measured (mm)

Estimated (mm)

# SLOTS (HP) Measured Measured

Peak Estimated

CCB 0,3 + 0,3 ? 160x100x25 10 6

CLKboard 0,3 + 0,3 160x100x25 10 3

GPS 0,3+ 0,3 160x100x25 10 0,2 0,3 1

HK 0,3+ 0,3 ? ? 28 6

PDM_LVPS 0,3+ 0,3 10 4

DP_LVPS1 0,3+ 0,3 ? 10 6.5

DP_LVPS2 0,3+ 0,3 ? 10 3

DP_LVPS3 0,3+ 0,3 ? 10 4

CPU 1 170x170x25 21 (6U) 11 15 12

DST 0,3 0 3 7 5

SUBRACK (19" 6U) 10 230x430x235 (21 6U)

(126 3U) 0 0 0

Total 15,8 21 6U102 3U 49.5

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CCB

DP planning for Telescope Array

HK

CPU

DP mechanics

DP cablesCCB

LVPS

CLKB

GPSR

Week numb.

Documents

Data Processor Status Hardware