ADSP-BF537 Blackfin® Processor Hardware Reference › wswitala › download › pdf › BF537_HRM_whole_book_o.pdfADSP-BF537 Blackfin® Processor Hardware Reference Revision 2.0,

ADSP-BF537 Blackfin® ProcessorHardware Reference

Revision 2.0, December 2005

Part Number82-000555-01

Analog Devices, Inc.One Technology WayNorwood, Mass. 02062-9106 a

Copyright Information© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc.

Printed in the USA.

DisclaimerAnalog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli-cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark NoticeThe Analog Devices logo, Blackfin, the Blackfin logo, CrossCore, EZ-KIT Lite, SHARC, TigerSHARC, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

ADSP-BF537 Blackfin Processor Hardware Reference iii

CONTENTS

PREFACE

Purpose of This Manual ............................................................... xliii

Intended Audience ....................................................................... xliii

Manual Contents .......................................................................... xliv

What’s New in This Manual ......................................................... xlvii

Technical or Customer Support .................................................... xlvii

Supported Processors .................................................................. xlviii

Product Information ..................................................................... xlix

MyAnalog.com ........................................................................ xlix

Processor Product Information ................................................. xlix

Related Documents ..................................................................... l

Online Technical Documentation ............................................... li

Accessing Documentation From VisualDSP++ ....................... lii

Accessing Documentation From Windows ............................. lii

Accessing Documentation From the Web .............................. liii

Printed Manuals ....................................................................... liii

VisualDSP++ Documentation Set ......................................... liii

Hardware Tools Manuals ...................................................... liv

Processor Manuals ................................................................ liv

Data Sheets .......................................................................... liv

Contents

iv ADSP-BF537 Blackfin Processor Hardware Reference

Conventions .................................................................................... lv

Register Diagram Conventions .................................................. lvi

INTRODUCTION

Peripherals .................................................................................... 1-1

Memory Architecture .................................................................... 1-4

Internal Memory ..................................................................... 1-6

External Memory .................................................................... 1-6

I/O Memory Space .................................................................. 1-7

DMA Support .............................................................................. 1-7

External Bus Interface Unit ........................................................... 1-9

PC133 SDRAM Controller ..................................................... 1-9

Asynchronous Controller ........................................................ 1-9

Ports .......................................................................................... 1-10

General-Purpose I/O (GPIO) ................................................ 1-10

Two-Wire Interface ..................................................................... 1-11

Controller Area Network ............................................................ 1-12

Ethernet MAC ............................................................................ 1-14

Parallel Peripheral Interface ......................................................... 1-14

SPORT Controllers .................................................................... 1-16

Serial Peripheral Interface (SPI) Port ........................................... 1-18

Timers ....................................................................................... 1-18

UART Ports ............................................................................... 1-19

Real-Time Clock ........................................................................ 1-20

Watchdog Timer ......................................................................... 1-21

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Contents

Clock Signals .............................................................................. 1-22

Dynamic Power Management ...................................................... 1-23

Full On Mode (Maximum Performance) ................................ 1-23

Active Mode (Moderate Power Savings) .................................. 1-23

Sleep Mode (High Power Savings) .......................................... 1-23

Deep Sleep Mode (Maximum Power Savings) ......................... 1-24

Hibernate State ..................................................................... 1-24

Voltage Regulation ...................................................................... 1-24

Boot Modes ................................................................................ 1-25

Instruction Set Description ......................................................... 1-27

Development Tools ..................................................................... 1-29

CHIP BUS HIERARCHY

Overview ...................................................................................... 2-1

Interface Overview ........................................................................ 2-3

Internal Clocks ........................................................................ 2-4

Core Bus Overview .................................................................. 2-4

Peripheral Access Bus (PAB) ..................................................... 2-6

PAB Arbitration .................................................................. 2-6

PAB Agents (Masters, Slaves) ............................................... 2-6

PAB Performance ................................................................ 2-7

DMA Access Bus (DAB), DMA Core Bus (DCB), DMA External Bus (DEB) .................................................... 2-8

DAB Arbitration ................................................................. 2-8

DAB Bus Agents (Masters) .................................................. 2-9

DAB, DCB, and DEB Performance ................................... 2-10

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vi ADSP-BF537 Blackfin Processor Hardware Reference

External Access Bus (EAB) .................................................... 2-10

Arbitration of the External Bus .............................................. 2-11

DEB/EAB Performance ......................................................... 2-11

MEMORY

Memory Architecture .................................................................... 3-1

L1 Instruction SRAM ................................................................... 3-5

L1 Data SRAM ............................................................................ 3-7

L1 Data Cache ............................................................................. 3-8

Boot ROM ................................................................................... 3-8

External Memory .......................................................................... 3-8

Processor-Specific MMRs .............................................................. 3-8

DMEM_CONTROL Register ................................................. 3-9

DTEST_COMMAND Register ............................................ 3-10

SYSTEM INTERRUPTS

Overview ...................................................................................... 4-1

Features .................................................................................. 4-1

Interfaces ...................................................................................... 4-2

Description of Operation .............................................................. 4-2

Events and Sequencing ............................................................ 4-2

System Peripheral Interrupts .................................................... 4-7

Programming Model ................................................................... 4-14

System Interrupt Initialization ............................................... 4-14

System Interrupt Processing Summary ................................... 4-14

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Contents

System Interrupt Controller Registers .......................................... 4-16

SIC_IARx Registers ............................................................... 4-18

SIC_IMASK Register ............................................................ 4-20

SIC_ISR Register .................................................................. 4-21

SIC_IWR Register ................................................................. 4-22

Programming Examples ............................................................... 4-23

Clearing Interrupt Requests ................................................... 4-23

DIRECT MEMORY ACCESS

Overview and Features .................................................................. 5-1

DMA Controller Overview ............................................................ 5-5

External Interfaces ................................................................... 5-6

Internal Interfaces ................................................................... 5-6

Peripheral DMA ...................................................................... 5-7

Memory DMA ........................................................................ 5-9

Handshaked Memory DMA Mode .................................... 5-11

Modes of Operation .................................................................... 5-12

Register-based DMA Operation ............................................. 5-12

Stop Mode ........................................................................ 5-13

Autobuffer Mode .............................................................. 5-14

Two-Dimensional DMA Operation ........................................ 5-14

Examples of Two-Dimensional DMA ................................ 5-15

Descriptor-based DMA Operation ......................................... 5-16

Descriptor List Mode ........................................................ 5-17

Descriptor Array Mode ..................................................... 5-18

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viii ADSP-BF537 Blackfin Processor Hardware Reference

Variable Descriptor Size .................................................... 5-18

Mixing Flow Modes .......................................................... 5-19

Functional Description ............................................................... 5-20

DMA Operation Flow ........................................................... 5-20

DMA Startup ................................................................... 5-20

DMA Refresh ................................................................... 5-25

Work Unit Transitions ...................................................... 5-27

DMA Transmit and MDMA Source .............................. 5-28

DMA Receive ............................................................... 5-30

Stopping DMA Transfers .................................................. 5-31

DMA Errors (Aborts) ............................................................ 5-32

DMA Control Commands .................................................... 5-34

Restrictions ...................................................................... 5-38

Transmit Restart or Finish ............................................. 5-38

Receive Restart or Finish ............................................... 5-39

Handshaked Memory DMA Operation .................................. 5-40

Pipelining DMA Requests ................................................. 5-41

HMDMA Interrupts ......................................................... 5-43

DMA Performance ................................................................ 5-44

DMA Throughput ............................................................ 5-45

Memory DMA Timing Details .......................................... 5-48

Static Channel Prioritization ............................................. 5-48

Temporary DMA Urgency ................................................ 5-50

Memory DMA Priority and Scheduling ............................. 5-51

Traffic Control ................................................................. 5-53

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Contents


Synchronization of Software and DMA .................................. 5-56

Single-buffer DMA Transfers ............................................. 5-58

Continuous Transfers Using Autobuffering ........................ 5-58

Descriptor Structures ........................................................ 5-60

Descriptor Queue Management ......................................... 5-61

Descriptor Queue Using Interrupts on Every Descriptor 5-62

Descriptor Queue Using Minimal Interrupts .................. 5-63

Software Triggered Descriptor Fetches ............................... 5-65

DMA Registers ........................................................................... 5-67

DMA Channel Registers ........................................................ 5-68

DMAx_PERIPHERAL_MAP/MDMA_yy_PERIPHERAL_MAP Registers ................... 5-71

DMAx_CONFIG/MDMA_yy_CONFIG Registers ........... 5-74

DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS Registers .............................. 5-78

DMAx_START_ADDR/MDMA_yy_START_ADDR Registers ............................ 5-82

DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR Registers ........................................................................ 5-83

DMAx_X_COUNT/MDMA_yy_X_COUNT Registers .... 5-85

DMAx_CURR_X_COUNT/MDMA_yy_CURR_X_COUNT Registers ..................... 5-86

DMAx_X_MODIFY/MDMA_yy_X_MODIFY Registers ................................ 5-88

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x ADSP-BF537 Blackfin Processor Hardware Reference

DMAx_Y_COUNT/MDMA_yy_Y_COUNT Registers ................................. 5-90

DMAx_CURR_Y_COUNT/MDMA_yy_CURR_Y_COUNT Registers ..................... 5-91

DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY Registers ........................................................................ 5-93

DMAx_NEXT_DESC_PTR/MDMA_yy_NEXT_DESC_PTR Registers ..................... 5-94

DMAx_CURR_DESC_PTR/MDMA_yy_CURR_DESC_PTR Registers .................... 5-96

HMDMA Registers ............................................................... 5-98

HMDMAx_CONTROL Registers .................................... 5-99

HMDMAx_BCINIT Registers ........................................ 5-101

HMDMAx_BCOUNT Registers .................................... 5-101

HMDMAx_ECOUNT Registers ..................................... 5-102

HMDMAx_ECINIT Registers ........................................ 5-103

HMDMAx_ECURGENT Registers ................................ 5-104

HMDMAx_ECOVERFLOW Registers ........................... 5-104

DMA Traffic Control Registers ............................................ 5-105

DMA_TC_PER Register ................................................ 5-105

DMA_TC_CNT Register ............................................... 5-106

Programming Examples ............................................................ 5-107

Register-Based 2D Memory DMA ....................................... 5-107

Initializing Descriptors in Memory ...................................... 5-111

Software-Triggered Descriptor Fetch Example ...................... 5-114

Handshaked Memory DMA Example .................................. 5-116

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Contents

EXTERNAL BUS INTERFACE UNIT

EBIU Overview ............................................................................ 6-1

Block Diagram ........................................................................ 6-4

Internal Memory Interfaces ...................................................... 6-5

Registers .................................................................................. 6-6

Shared Pins ............................................................................. 6-6

System Clock .......................................................................... 6-7

Error Detection ....................................................................... 6-7

Bus Request and Grant ............................................................ 6-8

Operation ............................................................................... 6-8

AMC Overview and Features ......................................................... 6-9

Features ................................................................................... 6-9

Asynchronous Memory Interface .............................................. 6-9

Asynchronous Memory Address Decode ............................ 6-10

AMC Pin Description ................................................................. 6-10

AMC Description of Operation ................................................... 6-11

Avoiding Bus Contention ...................................................... 6-11

External Access Extension .................................................. 6-12

AMC Functional Description ...................................................... 6-12

Programmable Timing Characteristics .................................... 6-12

Asynchronous Reads ......................................................... 6-13

Asynchronous Writes ......................................................... 6-14

Adding External Access Extension ..................................... 6-16

Byte Enables .......................................................................... 6-18

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xii ADSP-BF537 Blackfin Processor Hardware Reference

AMC Programming Model ......................................................... 6-18

AMC Registers ........................................................................... 6-21

EBIU_AMGCTL Register ..................................................... 6-21

EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers ............... 6-21

AMC Programming Examples ..................................................... 6-24

SDC Overview and Features ....................................................... 6-25

Features ................................................................................ 6-25

SDRAM Configurations Supported ....................................... 6-26

SDRAM External Bank Size .................................................. 6-27

SDC Address Mapping .......................................................... 6-27

Internal SDRAM Bank Select ................................................ 6-29

Parallel Connection of SDRAMs ........................................... 6-29

SDC Interface Overview ............................................................. 6-30

SDC Pin Description ............................................................ 6-30

SDRAM Performance ........................................................... 6-31

SDC Description of Operation ................................................... 6-32

Definition of SDRAM Architecture Terms ............................. 6-32

Refresh ............................................................................. 6-32

Row Activation ................................................................. 6-32

Column Read/Write ......................................................... 6-32

Row Precharge .................................................................. 6-33

Internal Bank ................................................................... 6-33

External Bank ................................................................... 6-33

Memory Size .................................................................... 6-33

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Contents

Burst Length ..................................................................... 6-33

Burst Type ........................................................................ 6-34

CAS Latency ..................................................................... 6-34

Data I/O Mask Function ................................................... 6-34

SDRAM Commands ......................................................... 6-34

Mode Register Set (MRS) command .................................. 6-34

Extended Mode Register Set (EMRS) command ................ 6-34

Bank Activate command .................................................... 6-35

Read/Write command ....................................................... 6-35

Precharge/Precharge All Command .................................... 6-35

Auto-refresh command ...................................................... 6-35

Enter Self-Refresh Mode ................................................... 6-35

Exit Self-Refresh Mode ...................................................... 6-36

SDC Timing Specs ................................................................ 6-36

tMRD .............................................................................. 6-36

tRAS ................................................................................ 6-36

CL .................................................................................... 6-37

tRCD ............................................................................... 6-37

tRRD ............................................................................... 6-37

tWR ................................................................................. 6-37

tRP ................................................................................... 6-38

tRC .................................................................................. 6-38

tRFC ................................................................................ 6-38

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xiv ADSP-BF537 Blackfin Processor Hardware Reference

tXSR ................................................................................ 6-38

tREF ................................................................................ 6-39

tREFI ............................................................................... 6-39

SDC Functional Description ....................................................... 6-39

SDC Operation .................................................................... 6-39

SDC Address Muxing ....................................................... 6-42

Multibank Operation ........................................................ 6-43

Core and DMA Arbitration .............................................. 6-44

Changing System Clock During Runtime .......................... 6-44

Changing Power Management During Runtime ................ 6-46

Deep Sleep Mode .......................................................... 6-46

Hibernate State ............................................................. 6-46

Shared SDRAM ................................................................ 6-46

SDC Commands ................................................................... 6-47

Mode Register Set Command ............................................ 6-49

Extended Mode Register Set Command (Mobile SDRAM) .......................................................... 6-50

Bank Activation Command ............................................... 6-51

Read/Write Command ...................................................... 6-51

Write Command With Data Mask .................................... 6-51

Single Precharge Command .............................................. 6-52

Precharge All Command ................................................... 6-52

Auto-Refresh Command ................................................... 6-52

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Contents

Self-Refresh Mode ............................................................. 6-53

Self-Refresh Entry Command ................................... 6-53

Self-Refresh Exit Command ..................................... 6-54

No Operation Command .................................................. 6-54

SDC SA10 Pin ...................................................................... 6-55

SDC Programming Model ........................................................... 6-55

SDC Configuration ............................................................... 6-56

Example SDRAM System Block Diagrams ............................. 6-58

SDC Register Definitions ............................................................ 6-60

EBIU_SDRRC Register ......................................................... 6-60

EBIU_SDBCTL Register ....................................................... 6-62

Using SDRAMs With Systems Smaller than 16M byte ....... 6-65

EBIU_SDGCTL Register ...................................................... 6-67

EBIU_SDSTAT Register ........................................................ 6-78

SDC Programming Examples ...................................................... 6-79

PARALLEL PERIPHERAL INTERFACE

Overview ...................................................................................... 7-1

Features ........................................................................................ 7-1



Functional Description ................................................................. 7-6

ITU-R 656 Modes ................................................................... 7-6

ITU-R 656 Background ...................................................... 7-6

ITU-R 656 Input Modes ................................................... 7-10

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xvi ADSP-BF537 Blackfin Processor Hardware Reference

Entire Field .................................................................. 7-10

Active Video Only ........................................................ 7-11

Vertical Blanking Interval (VBI) only ............................ 7-11

ITU-R 656 Output Mode ................................................. 7-12

Frame Synchronization in ITU-R 656 Modes .................... 7-12

General-Purpose PPI Modes .................................................. 7-13

Data Input (RX) Modes .................................................... 7-15

No Frame Syncs ............................................................ 7-16

1, 2, or 3 External Frame Syncs ..................................... 7-16

2 or 3 Internal Frame Syncs .......................................... 7-17

Data Output (TX) Modes ................................................. 7-18

No Frame Syncs ............................................................ 7-18

1 or 2 External Frame Syncs .......................................... 7-18

1, 2, or 3 Internal Frame Syncs ..................................... 7-19

Frame Synchronization in GP Modes ................................ 7-20

Modes With Internal Frame Syncs ................................. 7-20

Modes With External Frame Syncs ................................ 7-21


DMA Operation ................................................................... 7-23

PPI Registers .............................................................................. 7-26

PPI_CONTROL Register ..................................................... 7-26

PPI_STATUS Register .......................................................... 7-30

PPI_DELAY Register ............................................................ 7-34

PPI_COUNT Register .......................................................... 7-34

PPI_FRAME Register ........................................................... 7-35

ADSP-BF537 Blackfin Processor Hardware Reference xvii

Contents


Data Transfer Scenarios ......................................................... 7-39

ETHERNET MAC

Overview ...................................................................................... 8-1

Features ................................................................................... 8-1


External Interface .................................................................... 8-4

Clocking ............................................................................. 8-4

Pins .................................................................................... 8-5

Internal Interface ..................................................................... 8-6

Power Management ............................................................. 8-7


Protocol .................................................................................. 8-7

MII Management Interface .................................................. 8-7

Operation ............................................................................. 8-10

MII Management Interface Operation ............................... 8-10

Receive DMA Operation ................................................... 8-11

Frame Reception and Filtering ....................................... 8-13

RX Automatic Pad Stripping ......................................... 8-17

RX DMA Data Alignment ............................................. 8-18

RX DMA Buffer Structure ............................................. 8-18

RX Frame Status Buffer ................................................. 8-19

RX Frame Status Classification ...................................... 8-20

Contents

xviii ADSP-BF537 Blackfin Processor Hardware Reference

RX IP Frame Checksum Calculation ............................. 8-21

RX DMA Direction Errors ............................................ 8-22

Transmit DMA Operation ................................................ 8-24

Flexible Descriptor Structure ......................................... 8-27

TX DMA Data Alignment ............................................ 8-27

Late Collisions .............................................................. 8-28

TX Frame Status Classification ..................................... 8-29

TX DMA Direction Errors ............................................ 8-30

Power Management .......................................................... 8-31

Ethernet Operation in the Sleep State ............................ 8-33

Magic Packet Detection ................................................ 8-34

Remote Wake-up Filters ................................................ 8-35

Ethernet Event Interrupts ................................................. 8-38

RX/TX Frame Status Interrupt Operation ..................... 8-42

RX Frame Status Register Operation at Startup and Shutdown ............................................... 8-43

TX Frame Status Register Operation at Startup and Shutdown ............................................... 8-43

MAC Management Counters ............................................ 8-43


Configure MAC Pins ............................................................ 8-46

Multiplexing Scheme ........................................................ 8-47

CLKBUF ......................................................................... 8-47

Configure Interrupts ............................................................. 8-47

ADSP-BF537 Blackfin Processor Hardware Reference xix

Contents

Configure MAC Registers ...................................................... 8-48

MAC Address ................................................................... 8-48

MII Station Management .................................................. 8-48

Configure PHY ..................................................................... 8-50

Receive and Transmit Data .................................................... 8-50

Receiving Data .................................................................. 8-51

Transmitting Data ............................................................. 8-51

Ethernet MAC Register Definitions ............................................. 8-51

Control-Status Register Group ............................................... 8-63

EMAC_OPMODE Register .............................................. 8-64

EMAC_ADDRLO Register ............................................... 8-70

EMAC_ADDRHI Register ................................................ 8-71

EMAC_HASHLO and EMAC_HASHHI Registers ........... 8-72

EMAC_STAADD Register ................................................ 8-76

EMAC_STADAT Register ................................................. 8-78

EMAC_FLC Register ........................................................ 8-78

EMAC_VLAN1 and EMAC_VLAN2 Registers ................. 8-80

EMAC_WKUP_CTL Register .......................................... 8-81

EMAC_WKUP_FFMSK0, EMAC_WKUP_FFMSK1, EMAC_WKUP_FFMSK2, and EMAC_WKUP_FFMSK3 Registers ........................................................................ 8-84

EMAC_WKUP_FFCMD Register .................................... 8-89

EMAC_WKUP_FFOFF Register ...................................... 8-91

EMAC_WKUP_FFCRC0 and EMAC_WKUP_FFCRC1 Registers ................................ 8-92

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xx ADSP-BF537 Blackfin Processor Hardware Reference

System Interface Register Group ............................................ 8-93

EMAC_SYSCTL Register ................................................. 8-93

EMAC_SYSTAT Register ................................................. 8-95

Ethernet MAC Frame Status Registers ................................... 8-97

EMAC_RX_STAT Register ............................................... 8-97

EMAC_RX_STKY Register ............................................ 8-103

EMAC_RX_IRQE Register ............................................. 8-107

EMAC_TX_STAT Register ............................................. 8-108

EMAC_TX_STKY Register ............................................ 8-112

EMAC_TX_IRQE Register ............................................ 8-114

EMAC_MMC_RIRQS Register ...................................... 8-115

EMAC_MMC_RIRQE Register ..................................... 8-117

EMAC_MMC_TIRQS Register ...................................... 8-119

EMAC_MMC_TIRQE Register ..................................... 8-121

MAC Management Counter Registers .................................. 8-123

EMAC_MMC_CTL Register .......................................... 8-124


Ethernet Structures ............................................................. 8-126

MAC Address Setup ............................................................ 8-129

PHY Control Routines ........................................................ 8-130

CAN MODULE

Overview ...................................................................................... 9-1

Interface Overview ....................................................................... 9-2

CAN Mailbox Area ................................................................. 9-4

ADSP-BF537 Blackfin Processor Hardware Reference xxi

Contents

CAN Mailbox Control ............................................................. 9-6

CAN Protocol Basics ............................................................... 9-7

CAN Operation ............................................................................ 9-9

Bit Timing .............................................................................. 9-9

Transmit Operation ............................................................... 9-12

Retransmission .................................................................. 9-13

Single Shot Transmission ................................................... 9-15

Auto-Transmission ............................................................ 9-15

Receive Operation ................................................................. 9-15

Data Acceptance Filter ...................................................... 9-18

Remote Frame Handling ................................................... 9-19

Watchdog Mode ............................................................... 9-19

Time Stamps ......................................................................... 9-20

Temporarily Disabling Mailboxes ........................................... 9-21

Functional Operation .................................................................. 9-22

CAN Interrupts ..................................................................... 9-23

Mailbox Interrupts ............................................................ 9-23

Global Interrupt ............................................................... 9-24

Event Counter ....................................................................... 9-26

CAN Warnings and Errors ..................................................... 9-28

Programmable Warning Limits .......................................... 9-28

CAN Error Handling ........................................................ 9-28

Error Frames ................................................................. 9-29

Error Levels .................................................................. 9-31

Contents

xxii ADSP-BF537 Blackfin Processor Hardware Reference

Debug and Test Modes .......................................................... 9-33

Low Power Features ............................................................... 9-37

CAN Built-In Suspend Mode ............................................ 9-37

CAN Built-In Sleep Mode ................................................ 9-38

CAN Wakeup From Hibernate State ................................. 9-38

Register Definitions .................................................................... 9-39

Global Registers .................................................................... 9-42

CAN_CONTROL Register .............................................. 9-43

CAN_STATUS Register ................................................... 9-44

CAN_DEBUG Register .................................................... 9-45

CAN_CLOCK Register .................................................... 9-45

CAN_TIMING Register ................................................... 9-46

CAN_INTR Register ........................................................ 9-46

CAN_GIM Register ......................................................... 9-47

CAN_GIS Register ........................................................... 9-47

CAN_GIF Register ........................................................... 9-48

Mailbox/Mask Registers ........................................................ 9-48

CAN_AMxx Registers ....................................................... 9-49

CAN_MBxx_ID1 Registers .............................................. 9-53

CAN_MBxx_ID0 Registers .............................................. 9-55

CAN_MBxx_TIMESTAMP Registers ............................... 9-57

CAN_MBxx_LENGTH Registers ..................................... 9-59

CAN_MBxx_DATAx Registers ......................................... 9-61

ADSP-BF537 Blackfin Processor Hardware Reference xxiii

Contents

Mailbox Control Registers ..................................................... 9-68

CAN_MCx Registers ........................................................ 9-69

CAN_MDx Registers ........................................................ 9-70

CAN_RMPx Register ........................................................ 9-71

CAN_RMLx Register ........................................................ 9-72

CAN_OPSSx Register ....................................................... 9-73

CAN_TRSx Registers ........................................................ 9-74

CAN_TRRx Registers ....................................................... 9-75

CAN_AAx Register ........................................................... 9-76

CAN_TAx Register ........................................................... 9-77

CAN_MBTD Register ...................................................... 9-78

CAN_RFHx Registers ....................................................... 9-78

CAN_MBIMx Registers .................................................... 9-79

CAN_MBTIFx Registers ................................................... 9-80

CAN_MBRIFx Registers ................................................... 9-81

Universal Counter Registers ................................................... 9-82

CAN_UCCNF Register .................................................... 9-83

CAN_UCCNT Register .................................................... 9-84

CAN_UCRC Register ....................................................... 9-84

Error Registers ....................................................................... 9-85

CAN_CEC Register .......................................................... 9-85

CAN_ESR Register ........................................................... 9-85

CAN_EWR Register ......................................................... 9-86

Contents

xxiv ADSP-BF537 Blackfin Processor Hardware Reference

Programming Examples .............................................................. 9-87

CAN Setup Code .................................................................. 9-87

Initializing and Enabling CAN Mailboxes .............................. 9-89

Initiating CAN Transfers and Processing Interrupts ................ 9-90

SPI COMPATIBLE PORT CONTROLLERS

Overview .................................................................................... 10-1

Features ...................................................................................... 10-1

Interface Overview ..................................................................... 10-3

External Interface .................................................................. 10-4

Serial Peripheral Interface Clock Signal (SCK) ................... 10-4

Master Out Slave In (MOSI) ............................................ 10-5

Master In Slave Out (MISO) ............................................ 10-5

Serial Peripheral Interface Slave Select Input Signal ............ 10-6

Serial Peripheral Interface Slave Select Enable Output Signals ................................................... 10-7

Slave Select Inputs .......................................................... 10-10

Use of FLS Bits in SPI_FLG for Multiple Slave SPI Systems ......................................................... 10-10

Internal Interfaces ............................................................... 10-12

DMA Functionality ........................................................ 10-12

SPI Transmit Data Buffer .................................................... 10-13

SPI Receive Data Buffer ...................................................... 10-14

Description of Operation .......................................................... 10-14

SPI Transfer Protocols ......................................................... 10-14

ADSP-BF537 Blackfin Processor Hardware Reference xxv

Contents

SPI General Operation ........................................................ 10-17

SPI Control ......................................................................... 10-18

Clock Signals ...................................................................... 10-19

SPI Baud Rate ..................................................................... 10-20

Error Signals and Flags ........................................................ 10-20

Mode Fault Error (MODF) ............................................. 10-21

Transmission Error (TXE) ............................................... 10-22

Reception Error (RBSY) .................................................. 10-22

Transmit Collision Error (TXCOL) ................................. 10-22

Interrupt Output ................................................................. 10-23

Functional Description ............................................................. 10-23

Master Mode Operation ...................................................... 10-24

Transfer Initiation From Master (Transfer Modes) ................ 10-25

Slave Mode Operation ......................................................... 10-26

Slave Ready for a Transfer .................................................... 10-27

Programming Model ................................................................. 10-28

Beginning and Ending an SPI Transfer ................................. 10-28

Master Mode DMA Operation ............................................. 10-30

Slave Mode DMA Operation ............................................... 10-32

SPI Registers ............................................................................. 10-40

Programming Examples ............................................................. 10-45

Core Generated Transfer ...................................................... 10-45

Initialization Sequence .................................................... 10-45

Starting a Transfer ........................................................... 10-46

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xxvi ADSP-BF537 Blackfin Processor Hardware Reference

Post Transfer and Next Transfer ...................................... 10-47

Stopping ........................................................................ 10-48

DMA Transfer .................................................................... 10-48

DMA Initialization Sequence .......................................... 10-49

SPI Initialization Sequence ............................................. 10-50

Starting a Transfer .......................................................... 10-51

Stopping a Transfer ......................................................... 10-51

TWO WIRE INTERFACE CONTROLLER

Overview .................................................................................... 11-1



Serial Clock signal (SCL) .................................................. 11-3

Serial data signal (SDA) .................................................... 11-4

TWI Pins ......................................................................... 11-4

Internal Interfaces ................................................................. 11-5

Description of Operation ............................................................ 11-6

TWI Transfer Protocols ......................................................... 11-6

Clock Generation and Synchronization ............................. 11-6

Bus Arbitration ................................................................. 11-7

Start and Stop Conditions ................................................. 11-8

General Call Support ........................................................ 11-9

Fast Mode ...................................................................... 11-10

TWI General Operation ........................................................... 11-10

TWI Control ...................................................................... 11-10

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Contents

Clock Signal ........................................................................ 11-11

Error Signals and Flags ........................................................ 11-12

TWI Master Status .......................................................... 11-12

TWI Slave Status ............................................................ 11-15

TWI FIFO Status ........................................................... 11-16

TWI Interrupt Status ...................................................... 11-17


General Setup ...................................................................... 11-20

Slave Mode .......................................................................... 11-20

Master Mode Clock Setup ................................................... 11-22

Master Mode Transmit ........................................................ 11-22

Master Mode Receive ........................................................... 11-23

Repeated Start Condition .................................................... 11-24

Transmit/Receive Repeated Start Sequence ....................... 11-24

Receive/Transmit Repeated Start Sequence ....................... 11-26


Register Descriptions ................................................................ 11-30

TWI_CONTROL Register .................................................. 11-30

TWI_CLKDIV Register ...................................................... 11-30

TWI_SLAVE_CTL Register ................................................ 11-31

TWI_SLAVE_ADDR Register ............................................. 11-33

TWI_SLAVE_STAT Register ............................................... 11-33

TWI_MASTER_CTL Register ............................................ 11-34

TWI_MASTER_ADDR Register ......................................... 11-37

TWI_MASTER_STAT Register ........................................... 11-38

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xxviii ADSP-BF537 Blackfin Processor Hardware Reference

TWI_FIFO_CTL Register .................................................. 11-38

TWI_FIFO_STAT Register ................................................. 11-40

TWI_INT_MASK Register ................................................. 11-40

TWI_INT_STAT Register .................................................. 11-43

TWI_XMT_DATA8 Register .............................................. 11-43

TWI_XMT_DATA16 Register ............................................ 11-44

TWI_RCV_DATA8 Register ............................................... 11-45

TWI_RCV_DATA16 Register ............................................. 11-46


Master Mode Setup ............................................................. 11-47

Slave Mode Setup ................................................................ 11-52

Electrical Specifications ............................................................ 11-59

SPORT CONTROLLERS

Overview .................................................................................... 12-1

Features ................................................................................ 12-2


SPORT Pin/Line Terminations .............................................. 12-9

Description of Operation .......................................................... 12-10

SPORT Operation .............................................................. 12-10

SPORT Disable .................................................................. 12-10

Setting SPORT Modes ........................................................ 12-11

Stereo Serial Operation ....................................................... 12-12

Multichannel Operation ...................................................... 12-15

Multichannel Enable ....................................................... 12-18

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Contents

Frame Syncs in Multichannel Mode ................................. 12-19

The Multichannel Frame ................................................. 12-20

Multichannel Frame Delay .............................................. 12-21

Window Size ................................................................... 12-21

Window Offset ............................................................... 12-22

Other Multichannel Fields in SPORTx_MCMC2 ............ 12-22

Channel Selection Register .............................................. 12-23

Multichannel DMA Data Packing ................................... 12-24

Support for H.100 Standard Protocol ................................... 12-25

2X Clock Recovery Control ............................................. 12-26


Clock and Frame Sync Frequencies ...................................... 12-26

Maximum Clock Rate Restrictions .................................. 12-28

Word Length ....................................................................... 12-28

Bit Order ............................................................................ 12-28

Data Type ........................................................................... 12-28

Companding ....................................................................... 12-29

Clock Signal Options .......................................................... 12-30

Frame Sync Options ............................................................ 12-30

Framed Versus Unframed ................................................ 12-31

Internal Versus External Frame Syncs ............................... 12-32

Active Low Versus Active High Frame Syncs .................... 12-33

Sampling Edge for Data and Frame Syncs ........................ 12-33

Early Versus Late Frame Syncs (Normal Versus Alternate Timing) ........................................................ 12-35

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xxx ADSP-BF537 Blackfin Processor Hardware Reference

Data Independent Transmit Frame Sync .......................... 12-37

Moving Data Between SPORTs and Memory ....................... 12-38

SPORT RX, TX, and Error Interrupts ................................. 12-38

PAB Errors .......................................................................... 12-39

Timing Examples ................................................................ 12-39

SPORT Registers ...................................................................... 12-45

Register Writes and Effective Latency .................................. 12-47

SPORTx_TCR1 and SPORTx_TCR2 Registers ................... 12-47

SPORTx_RCR1 and SPORTx_RCR2 Registers ................... 12-52

Data Word Formats ............................................................. 12-57

SPORTx_TX Register ......................................................... 12-58

SPORTx_RX Register ......................................................... 12-60

SPORTx_STAT Register ..................................................... 12-63

SPORTx_TCLKDIV and SPORTx_RCLKDIV Registers ..... 12-64

SPORTx_TFSDIV and SPORTx_RFSDIV Register ............ 12-65

SPORTx_MCMCn Registers .............................................. 12-66

SPORTx_CHNL Register ................................................... 12-67

SPORTx_MRCSn Registers ................................................ 12-68

SPORTx_MTCSn Registers ................................................ 12-70


SPORT Initialization Sequence ........................................... 12-73

DMA Initialization Sequence .............................................. 12-75

Interrupt Servicing .............................................................. 12-77

Starting a Transfer ............................................................... 12-78

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Contents

UART PORT CONTROLLERS

Overview .................................................................................... 13-1

Features ...................................................................................... 13-1

Interface Overview ...................................................................... 13-2


Internal Interface ................................................................... 13-3


UART Transfer Protocol ........................................................ 13-4

UART Transmit Operation .................................................... 13-5

UART Receive Operation ...................................................... 13-6

IrDA Transmit Operation ...................................................... 13-8

IrDA Receive Operation ........................................................ 13-9

Interrupt Processing ............................................................ 13-10

Bit Rate Generation ............................................................. 13-12

Autobaud Detection ............................................................ 13-13


Non-DMA Mode ................................................................ 13-15

DMA Mode ........................................................................ 13-17

Mixing Modes ..................................................................... 13-18

UART Registers ........................................................................ 13-19

UARTx_LCR Registers ........................................................ 13-21

UARTx_MCR Registers ...................................................... 13-23

UARTx_LSR Registers ........................................................ 13-24

UARTx_THR Registers ....................................................... 13-26

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xxxii ADSP-BF537 Blackfin Processor Hardware Reference

UARTx_RBR Registers ....................................................... 13-26

UARTx_IER Registers ........................................................ 13-27

UARTx_IIR Registers ......................................................... 13-29

UARTx_DLL and UARTx_DLH Registers .......................... 13-30

UARTx_SCR Registers ........................................................ 13-31

UARTx_GCTL Registers .................................................... 13-31


GENERAL-PURPOSE PORTS

Overview .................................................................................... 14-1

Features ...................................................................................... 14-2



Port F Structure ................................................................ 14-4

Port G Structure ............................................................... 14-5

Port H Structure ............................................................... 14-6

Port J Structure ................................................................ 14-7


Performance/Throughput ...................................................... 14-9


Operation ............................................................................. 14-9

General-Purpose I/O Modules ............................................. 14-10

GPIO Interrupt Processing .................................................. 14-14


Memory-Mapped GPIO Registers ............................................. 14-22

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Contents


GENERAL-PURPOSE TIMERS

Overview and Features ................................................................ 15-1

Features ................................................................................. 15-1





Interrupt Processing .............................................................. 15-8

Illegal States ........................................................................ 15-10

Modes of Operation .................................................................. 15-13

Pulse Width Modulation (PWM_OUT) Mode ..................... 15-13

Output Pad Disable ........................................................ 15-15

Single Pulse Generation ................................................... 15-15

Pulse Width Modulation Waveform Generation ............... 15-16

PULSE_HI Toggle Mode ................................................ 15-18

Externally Clocked PWM_OUT ..................................... 15-22

Using PWM_OUT Mode With the PPI .......................... 15-23

Stopping the Timer in PWM_OUT Mode ....................... 15-23

Pulse Width Count and Capture (WDTH_CAP) Mode ....... 15-26

Autobaud Mode .............................................................. 15-34

External Event (EXT_CLK) Mode ....................................... 15-34


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xxxiv ADSP-BF537 Blackfin Processor Hardware Reference

Timer Registers ........................................................................ 15-37

TIMER_ENABLE Register ................................................. 15-38

TIMER_DISABLE Register ................................................ 15-39

TIMER_STATUS Register .................................................. 15-40

TIMERx_CONFIG Registers .............................................. 15-43

TIMERx_COUNTER Registers .......................................... 15-45

TIMERx_PERIOD and TIMERx_WIDTH Registers .......... 15-46

Summary ............................................................................ 15-50


CORE TIMER


Timer Overview ......................................................................... 16-1

External Interfaces ................................................................ 16-2



Interrupt Processing .............................................................. 16-3

Core Timer Registers .................................................................. 16-4

TCNTL Register ................................................................... 16-4

TCOUNT Register ............................................................... 16-5

TPERIOD Register ............................................................... 16-6

TSCALE Register .................................................................. 16-7

Programming Examples .............................................................. 16-7

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Contents

WATCHDOG TIMER






Register Definitions .................................................................... 17-5

WDOG_CNT Register ......................................................... 17-5

WDOG_STAT Register ......................................................... 17-6

WDOG_CTL Register .......................................................... 17-7


REAL-TIME CLOCK

Overview .................................................................................... 18-1



RTC Clock Requirements ...................................................... 18-4

Prescaler Enable ..................................................................... 18-4

RTC Programming Model ........................................................... 18-6

Register Writes ...................................................................... 18-7

Write Latency ........................................................................ 18-8

Register Reads ....................................................................... 18-9

Deep Sleep ............................................................................ 18-9

Event Flags .......................................................................... 18-10

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xxxvi ADSP-BF537 Blackfin Processor Hardware Reference

Setting Time of Day ............................................................ 18-12

Using the Stopwatch ........................................................... 18-13

Interrupts ........................................................................... 18-14

State Transitions Summary .................................................. 18-16

Register Definitions .................................................................. 18-19

RTC_STAT Register ........................................................... 18-20

RTC_ICTL Register ........................................................... 18-20

RTC_ISTAT Register .......................................................... 18-21

RTC_SWCNT Register ...................................................... 18-21

RTC_ALARM Register ....................................................... 18-22

RTC_PREN Register .......................................................... 18-22


Enable RTC Prescaler .......................................................... 18-23

RTC Stopwatch For Exiting Deep Sleep Mode ..................... 18-24

RTC Alarm to Come Out of Hibernate State ....................... 18-26

SYSTEM RESET AND BOOTING

Reset and Powerup ..................................................................... 19-2

Hardware Reset ..................................................................... 19-2

System Reset Configuration Register (SYSCR) ....................... 19-4

Software Resets and Watchdog Timer .................................... 19-5

Software Reset Register (SWRST) ......................................... 19-6

Core-Only Software Reset ..................................................... 19-7

Core and System Reset .......................................................... 19-8

Reset Vector .......................................................................... 19-8

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Contents

Servicing Reset Interrupts ...................................................... 19-9

Booting Process ......................................................................... 19-11

Header Information ............................................................. 19-13

Host Wait Feedback Strobe (HWAIT) ............................. 19-19

Final Initialization ........................................................... 19-21

Initialization Code ............................................................... 19-22

Multi-Application (Multi-DXE) Management ...................... 19-26

User-callable Boot ROM Functions ................................. 19-27

Booting a Different Application ................................... 19-27

Determining Boot Stream Start Addresses .................... 19-29

Specific Blackfin Boot Modes .................................................... 19-34

Bypass (No-Boot) Mode (BMODE = 000) ........................... 19-34

8-Bit Flash/PROM Boot (BMODE = 001) ........................... 19-36

16-Bit Flash/PROM Boot (BMODE = 001) ......................... 19-40

SPI Master Mode Boot from SPI Memory (BMODE = 011) .............................................................. 19-42

SPI Memory Detection Routine ...................................... 19-44

SPI Slave Mode Boot From SPI Host (BMODE = 100) ........ 19-48

TWI Master Boot Mode (BMODE = 101) ........................... 19-53

TWI Slave Boot Mode (BMODE = 110) .............................. 19-55

UART Slave Mode Boot via Master Host (BMODE = 111) .............................................................. 19-56

Blackfin Loader File Viewer ....................................................... 19-59

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xxxviii ADSP-BF537 Blackfin Processor Hardware Reference

DYNAMIC POWER MANAGEMENT

Phase Locked Loop and Clock Control ....................................... 20-1

PLL Overview ....................................................................... 20-2

PLL Clock Multiplier Ratios ................................................. 20-3

Core Clock/System Clock Ratio Control ........................... 20-5

Dynamic Power Management Controller ..................................... 20-7

Operating Modes .................................................................. 20-8

Dynamic Power Management Controller States ...................... 20-8

Full On Mode .................................................................. 20-9

Active Mode ..................................................................... 20-9

Sleep Mode ...................................................................... 20-9

Deep Sleep Mode ........................................................... 20-10

Hibernate State ............................................................... 20-11

Operating Mode Transitions ................................................ 20-11

Programming Operating Mode Transitions ...................... 20-14

PLL Programming Sequence ....................................... 20-15

PLL Programming Sequence Continues ....................... 20-17

Dynamic Supply Voltage Control ........................................ 20-18

Power Supply Management ................................................. 20-18

Controlling the Voltage Regulator ................................... 20-19

Changing Voltage ........................................................... 20-21

Powering Down the Core (Hibernate State) ..................... 20-22

PLL Registers ........................................................................... 20-24

PLL_DIV Register .............................................................. 20-25

PLL_CTL Register .............................................................. 20-26

ADSP-BF537 Blackfin Processor Hardware Reference xxxix

Contents

PLL_STAT Register ............................................................. 20-26

PLL_LOCKCNT Register ................................................... 20-27

VR_CTL Register ................................................................ 20-27


Active Mode to Full On Mode ............................................. 20-29

Full On Mode to Active Mode ............................................. 20-30

In the Full On Mode, Change CLKIN to VCO Multiplier From 31x to 2x ................................................ 20-31

Setting Wakeups and Entering Hibernate State ..................... 20-32

Changing Internal Voltage Levels ......................................... 20-33

SYSTEM DESIGN

Pin Descriptions ......................................................................... 21-1

Managing Clocks ........................................................................ 21-1

Managing Core and System Clocks ........................................ 21-2

Configuring and Servicing Interrupts ........................................... 21-2

Semaphores ................................................................................. 21-2

Example Code for Query Semaphore ..................................... 21-3

Data Delays, Latencies and Throughput ...................................... 21-4

Bus Priorities .............................................................................. 21-4

External Memory Design Issues ................................................... 21-5

Example Asynchronous Memory Interfaces ............................ 21-5

Avoiding Bus Contention ...................................................... 21-7

High Frequency Design Considerations ....................................... 21-8

Signal Integrity ...................................................................... 21-8

Decoupling Capacitors and Ground Planes .......................... 21-10

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xl ADSP-BF537 Blackfin Processor Hardware Reference

5 Volt Tolerance .................................................................. 21-11

Resetting the Processor ........................................................ 21-12

Recommendations for Unused Pins ..................................... 21-12

Programmable Outputs ....................................................... 21-12

Test Point Access ................................................................. 21-12

Oscilloscope Probes ............................................................. 21-13

Recommended Reading ....................................................... 21-13

SYSTEM MMR ASSIGNMENTS

Dynamic Power Management Registers ......................................... A-2

System Reset and Interrupt Control Registers ................................ A-2

Watchdog Timer Registers ............................................................ A-3

Real-Time Clock Registers ............................................................ A-4

UART0 Controller Registers ......................................................... A-4

SPI Controller Registers ................................................................ A-5

Timer Registers ............................................................................ A-6

Ports Registers .............................................................................. A-8

SPORT0 Controller Registers ..................................................... A-12

SPORT1 Controller Registers ..................................................... A-14

External Bus Interface Unit Registers .......................................... A-16

DMA/Memory DMA Control Registers ...................................... A-17

PPI Registers .............................................................................. A-19

UART1 Controller Registers ....................................................... A-20

CAN Registers ............................................................................ A-21

Ethernet MAC Registers ............................................................. A-29

ADSP-BF537 Blackfin Processor Hardware Reference xli

Contents

Handshake MDMA Control Registers ........................................ A-34

Core Timer Registers .................................................................. A-36

Processor-Specific Memory Registers .......................................... A-36

TEST FEATURES

JTAG Standard ............................................................................ B-1

Boundary-Scan Architecture ......................................................... B-2

Instruction Register ................................................................ B-4

Public Instructions ................................................................. B-5

EXTEST – Binary Code 00000 .......................................... B-5

SAMPLE/PRELOAD – Binary Code 10000 ....................... B-6

BYPASS – Binary Code 11111 ........................................... B-6

Boundary-Scan Register .......................................................... B-6

GLOSSARY

INDEX

Contents

xlii ADSP-BF537 Blackfin Processor Hardware Reference

ADSP-BF537 Blackfin Processor Hardware Reference xliii

PREFACE

Thank you for purchasing and developing systems using an enhanced Blackfin® processor from Analog Devices.

Purpose of This ManualThe ADSP-BF537 Blackfin Processor Hardware Reference provides architec-tural information about the ADSP-BF534, ADSP-BF536, and ADSP-BF537 processors. The architectural descriptions cover functional blocks, buses, and ports, including all features and processes that they sup-port. For programming information, see the ADSP-BF53x/BF56x Blackfin Processor Programming Reference. For timing, electrical, and package speci-fications, see the ADSP-BF534 Embedded Processor Data Sheet or the ADSP-BF536/ADSP-BF537 Embedded Processor Data Sheet.

Intended AudienceThe primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts (such as the appropriate instruction set reference manuals and data sheets) that describe your target architecture.

Manual Contents

xliv ADSP-BF537 Blackfin Processor Hardware Reference

Manual ContentsThis manual consists of:

• Chapter 1, “Introduction”Provides a high level overview of the processor, including peripher-als, power management, and development tools.

• Chapter 2, “Chip Bus Hierarchy”Describes on-chip buses, including how data moves through the system.

• Chapter 3, “Memory”Describes processor-specific memory topics, including L1memories and processor-specific memory MMRs.

• Chapter 4, “System Interrupts”Describes the system peripheral interrupts, including setup and clearing of interrupt requests.

• Chapter 5, “Direct Memory Access”Describes the peripheral DMA and Memory DMA controllers. Includes performance, software management of DMA, and DMA errors.

• Chapter 6, “External Bus Interface Unit”Describes the External Bus Interface Unit of the processor. The chapter also discusses the asynchronous memory interface, the SDRAM controller (SDC), related registers, and SDC configura-tion and commands.

• Chapter 7, “Parallel Peripheral Interface”Describes the Parallel Peripheral Interface (PPI) of the processor. The PPI is a half-duplex, bidirectional port accommodating up to 16 bits of data and is used for digital video and data converter applications.

ADSP-BF537 Blackfin Processor Hardware Reference xlv

Preface

• Chapter 8, “Ethernet MAC”Describes the Ethernet Media Access Controller (MAC) peripheral that is available on ADSP-BF536 and ADSP-BF537 processors. The Ethernet MAC provides a 10/100Mbit/s Ethernet interface, compliant to IEEE Std. 802.3-2002, between an MII (Media Inde-pendent Interface) and the Blackfin peripheral subsystem.

• Chapter 9, “CAN Module”Describes the CAN module, a low bit rate serial interface intended for use in applications where bit rates are typically up to 1Mbit/s.

• Chapter 10, “SPI Compatible Port Controllers”Describes the Serial Peripheral Interface (SPI) port that provides an I/O interface to a variety of SPI compatible peripheral devices.

• Chapter 11, “Two Wire Interface Controller”Describes the Two Wire Interface (TWI) controller, which allows a device to interface to an Inter IC bus as specified by the Philips I2C Bus Specification version 2.1 dated January 2000.

• Chapter 12, “SPORT Controllers”Describes the two independent, synchronous Serial Port Control-lers (SPORT0 and SPORT1) that provide an I/O interface to a variety of serial peripheral devices.

• Chapter 13, “UART Port Controllers”Describes the two Universal Asynchronous Receiver/Transmitter ports (UART0 and UART1) that convert data between serial and parallel formats. The UARTs support the half-duplex IrDA® SIR protocol as a mode-enabled feature.

• Chapter 14, “General-Purpose Ports”Describes the general-purpose I/O ports, including the structure of each port, multiplexing, configuring the pins, and generating interrupts.

Manual Contents

xlvi ADSP-BF537 Blackfin Processor Hardware Reference

• Chapter 15, “General-Purpose Timers”Describes the eight general-purpose timers.

• Chapter 16, “Core Timer”Describes the core timer.

• Chapter 17, “Watchdog Timer”Describes the watchdog timer.

• Chapter 18, “Real-Time Clock”Describes a set of digital watch features of the processor, including time of day, alarm, and stopwatch countdown.

• Chapter 19, “System Reset and Booting”Describes the booting methods, booting process and specific boot modes for the processor.

• Chapter 20, “Dynamic Power Management”Describes the clocking, including the PLL, and the dynamic power management controller.

• Chapter 21, “System Design”Describes how to use the processor as part of an overall system. It includes information about bus timing and latency numbers, sema-phores, and a discussion of the treatment of unused