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ProjectMuMoR IST-34561 1

IST-2001-34561

MUMOR

D3.1

DigitalBasebandArchitectureScenariosforaMulti-ModeRadioDocumentNumber:IST-2001-34561/IMST/WP3/R/RE/001/01

ContractualDateofDeliverytotheCEC: October2002

ActualDateofDeliverytotheCEC: 31.10.2002

Author(s): UniS

Participant(s): UniS,NOKIA,LETI

Workpackage: WP3

Est.personmonths:

Security: Public

Nature: Report

Version: v09

Totalnumberofpages: 63

Abstract:

Themaintargetofthistaskisthedevelopmentofamulti -modesystemarchitectureforthedi gital

basebandpartofaUMTS/TDD/FDDandHSDPA/FDDsystem.Futurestandardenhancementswill

betakenintoaccount.Thereforeadetailedblockdiagramofthetargetsystemhastobedeveloped,

showingtheneededsystemfunctions,theirparametersandrequ irements.Theultimategoalofthe

digitalbasebandarchitectureisamulti -mode,i.e.soft -configurablearchitecture,andthesystem

architecturedesignwillreflectthis.

Keywordlist:UMTS,HSDPA,FDD,TDD,Multi-mode,Architecture


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Abbreviations/Terminology

ACK AcknowledgeADC AnaloguetoDigitalConverter

BMC BroadcastMulticastControl(optional,notimplementedhere)

BW BandWidth

CCSS CoCentricSystemStudio(alsosimplycalledSystemStudio)

CDMA CodeDivisionMultipleAccess

CPICH CommonPilotChannel

CQI ChannelQualityIndicator

CRC CyclicRedundancyCheck

DAC DigitaltoAnalogueConverter

DL Down-Link

DPCCH DedicatedPhysicalControlChannel

DPCH DedicatedPhysicalChannel

DPDCH DedicatedPhysicalDataChannel

FDD FrequencyDivisionDuplex

H-ARQ HybridAutomaticRepeatRequest

HSDPA HighSpeedDownlinkPacketAccess

HS-DPCCH HighSpeedDedicatedPhysicalControlChannel

HS-PDSCH HighSpeedPhysicalDownlinkSharedChannel

HS-SCCH High-SpeedSharedControlChannel

IF IntermediateFrequency

ISI Inter-Symbol-Interference

L1 Physicallayerasdefinedby3GPP,alsocalledPHY

L2 ProtocollayerconsistingofMAC,RLC,PDCPandBMCasdefinedby

3GPP

LLR LogLikelihoodRatio

MAC MediumAccessControl

MAI MultipleAccessInterference

Mbps MegaBitPerSecond

Mcps MegaChipsPerSecond

MMSE MinimumMeanSquareError

MOSI Multiple-Output-Single-Input.ThetermDLMOSIdiversityrefersto

STTD(twotransmitantennasatNodeB)andcellmacro-diversity.NACK NotAcknowledge


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OVSF OrthogonalVariableSpreadingFactor

P-CCPCH PrimaryCommonControlPhysicalChannel

PDCP PacketDataConvergenceProtocol

PHY Physicallayerasdefinedby3GPP,alsocalledL1

P-SCH PrimarySynchronizationChannel

QAM QuadratureAmplitudeModulation

QPSK QuadraturePhaseShiftKeying

RF RadioFrequency

RLC RadioLinkControl

RRC RadioResourceController

RRCos RootRaisedCosineFilter

Rx ReceiverorReceived,dependsonthecontext

SIR SymboltoInterferenceRatio

S-SCH SecondarySynchronizationChannel

TDD TimeDivisionDuplex

Tx TransmitterorTransmitted,dependsonthecontext

UARFCN UTRAAbsoluteRadioFrequencyChannelNumber

UE UserEquipment

UL Uplink

UTRAN UMTSTerrestrialRadioAccessNetwork

WCDMA WidebandCDMA


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Tableofcontents

1 INTRODUCTION ......................................................................................................................... 9

2 SYSTEMREQUIREMENTS..................................................................................................... 10

2.1 Transmitter/ReceiverChainsandPhysicalChannelstobeimplemented............................. 102.2 High-levelSystemRequirements.......................................................................................... 11

2.2.1 General .......................................................................................................................... 112.2.2 UMTSFDDSpecific..................................................................................................... 122.2.3 UMTSTDDSpecific .................................................................................................... 122.2.4 HSDPASpecific............................................................................................................ 12

2.3 HigherLayerInterface .......................................................................................................... 122.3.1 PrimitivesbetweenphysicallayerandMAClayer ....................................................... 122.3.2 PrimitivesbetweenphysicallayerandRRClayer ........................................................ 12

2.4 PhysicalLayerProcedures .................................................................................................... 132.5 UEPhysicalLayerMeasurementAbilities ........................................................................... 142.6 UECapabilityParameters ..................................................................................................... 14

2.6.1 UMTSFDD/TDDCapabilityParameters ..................................................................... 152.6.2 HS-DSCHCapabilityParameters.................................................................................. 17

3 OVERVIEWOFTHECONSTITUTINGSINGLEMODEARCHITECTURES............... 19

3.1 BasebandArchitectureforUMTS/FDD ............................................................................... 193.1.1 BasebandSignalProcessing.......................................................................................... 193.1.2 FDDBasebandSampleProcessing ............................................................................... 213.1.3 FDDBasebandChipProcessing ................................................................................... 233.1.4 TransmitterTransportChannelProcessing ................................................................... 29

3.1.5 TransmitterPhysicalChannelProcessing ..................................................................... 303.1.6 ReceiverPhysicalChannelProcessing.......................................................................... 303.1.7 ReceiverTransportChannelProcessing ....................................................................... 31

3.2 BasebandArchitectureforUMTS/TDD ............................................................................... 313.2.1 Transmitter .................................................................................................................... 313.2.2 Receiver......................................................................................................................... 34

3.3 BasebandArchitectureforHSDPA/FDD ............................................................................. 353.3.1 HSDPAspecificUplinkChannelcodingandmodulation ............................................ 363.3.2 HSDPAspecificDownlinkChannelcodingandmodulation ....................................... 373.3.3 PhysicalChannelDecoding........................................................................................... 39

4 MULTI-MODESYSTEMARCHITECTURE......................................................................... 44

4.1 FunctionalityMatrixforUplinkTransmitter ........................................................................ 444.1.1 SampleProcessing......................................................................................................... 444.1.2 ChipProcessing............................................................................................................. 444.1.3 TransportChannelProcessing....................................................................................... 454.1.4 PhysicalChannelProcessing......................................................................................... 46

4.2 FunctionalityMatrixforDownlinkReceiver........................................................................ 464.2.1 SampleProcessing......................................................................................................... 474.2.2 ChipProcessing............................................................................................................. 484.2.3 PhysicalChannelProcessing......................................................................................... 494.2.4 TransportChannelProcessing....................................................................................... 50

4.3 SystemPartitioning ............................................................................................................... 51

4.3.1 DigitalbasebandHW/SWpartitioning ......................................................................... 514.3.2 ComponentInteraction .................................................................................................. 524.3.3 Partitioningprocess ....................................................................................................... 53


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5 INTERFACETOFRONT-END................................................................................................ 54

6 VERIFICATIONCHANNELMODELANDPROPAGATIONCONDITIONS................. 58

6.1 UMTS-SpecValues:(B.2)PropagationConditions ............................................................. 586.1.1 PropagationConditions ................................................................................................. 586.1.2 ChannelModel:SpuriousEmissions ............................................................................ 59

6.2 RayleighChannelModelwithsimplifiedFront-End ............................................................ 60

7 CONCLUSION............................................................................................................................ 62

8 REFERENCES............................................................................................................................ 63


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Listoffigures

Figure2.1:Physicalchannelsimplementationoverview...................................................................... 11

Figure3-1:BasebandReceiverSignalProcessingandControl,SignalFlow ...................................... 20Figure3-2:BasebandTransmitterSignalProcessingandControl,SignalFlow.................................. 21

Figure3-3:TransmitterSampleProcessing,SignalFlow..................................................................... 21

Figure3-4:ReceiverSampleProcessing,SignalFlow ......................................................................... 22

Figure3-5:TypicalTxpulseshaping(controlleddelayforTDDonly)................................................ 22

Figure3-6:TypicalRxpulseshaping(controlleddelayforbothFDDandTDD)................................ 22

Figure3-7:TransmitterChipProcessing,SignalFlow......................................................................... 24

Figure3-8:ReceiverChipProcessing,SignalFlow ............................................................................. 25

Figure3-9:Spreadingforuplink........................................................................................................... 25Figure3-10:SpreadingforuplinkDPCCH,DPDCHsandHS-DPCCH .............................................. 26

Figure3-11:MultipathSearching ......................................................................................................... 27

Figure3-12:MultipathPowerEstimator,BlockDiagram .................................................................... 27

Figure3-13:RAKEReceiver ................................................................................................................ 28

Figure3-14:ExampleofRAKEMRCandChipLevelPreandPostDecisionBasedEqualisation . 28

Figure3-15:TransmitterTransportChannelProcessing,BlockDiagram............................................ 29

Figure3-16:TransmitterPhysicalChannelProcessing,BlockDiagram.............................................. 30

Figure3-17ReceiverPhysicalChannelProcessing,BlockDiagram ................................................... 30

Figure3-18ReceiverTransportChannelProcessing,BlockDiagram ................................................. 31

Figure3-19:BlockDiagramoftheTransmitter.................................................................................... 32

Figure3-20:BlockDiagramofTrCHModule. .................................................................................... 33

Figure3-21:BlockDivisionofSpreading/ScramblingUnit................................................................. 33

Figure3-22:StructureofBurstType1. ................................................................................................ 34

Figure3-23:StructureofBurstType2. ................................................................................................ 34

Figure3-24:ModuleidentificationofRx ............................................................................................ 35

Figure3-25:TimingstructureatUEforHS-DPCCHcontrolsignalling.............................................. 37

Figure3-26:SynchronizationandDemodulation ................................................................................. 38

Figure3-27:ChannelDecodingchainsHSDPA/HS-DSCH................................................................. 40

Figure3-28:HS-SCCHDecoding......................................................................................................... 42

Figure3-29:TimingrelationbetweentheHS-SCCHandtheassociatedHS-PDSCH......................... 43

Figure4-1:BlockMatrixUplinkTransmitterSampleProcessing .................................................... 44

Figure4-2:BlockMatrixUplinkTransmitterChipProcessing......................................................... 45

Figure4-3:BlockMatrixUplinkTransmitterTransportChannelProcessing .................................. 46

Figure4-4:BlockMatrixUplinkTransmitterPhysicalChannelProcessing..................................... 46

Figure4-5:BlockMatrixDownlinkReceiver ...................................................................................... 47


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Figure4-6:BlockMatrixDownlinkReceiverSampleProcessing .................................................... 47

Figure4-7:BlockMatrixDownlinkReceiverCellSearch................................................................ 48

Figure4-8:BlockMatrixDownlinkReceiverChipProcessing ........................................................ 49

Figure4-9:BlockMatrixDownlinkReceiverPhysicalChannelProcessing .................................... 50

Figure4-10:BlockMatrixDownlinkReceiverTransportChannelProcessing ................................ 50

Figure4-11:FE/BBpartitioningdegreesoffreedom ........................................................................... 51

Figure4-12:TypicalSoCdesign........................................................................................................... 52

Figure4-13:HW/SWPartitioningMap ................................................................................................ 53

Figure5-1:Front-EndInterfaceFunctionalityExample.................................................................... 54

Figure5-2:ControlInterfaceProtocol .................................................................................................. 57

Figure6-1:Themovingpropagationconditions................................................................................... 58

Figure6-2:PropagationConditionsforMultipathFadingEnvironments ........................................... 59

Figure6-4:ChannelModelwithabstractFront-EndModel................................................................. 61


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Listoftables

Table2.1:Transmitterandreceiverchainstobeimplemented ............................................................ 10

Table2.2:Implementedphysicalchannels ........................................................................................... 10Table2.3:PrimitivesbetweenL1andMAC......................................................................................... 12

Table2.4:PrimitivesbetweenL1andRRC.......................................................................................... 13

Table2.5:Supportofphysicallayerprocedures................................................................................... 14

Table2.6:SupportofUEmeasurementabilities .................................................................................. 14

Table2.7:Valuerangesforthephysicallayerradioaccesscapabilityparameters .............................. 17

Table2.8:FDDHS-DSCHphysicallayercategories ........................................................................... 18

Table2.9:TheselectedFDDHS-DSCHphysicallayercategory ........................................................ 18

Table3.1:BlockswithinBasebandReceiverSignalProcessingandControlforUMTS/FDD ........... 19Table3.2:BlockswithinBasebandTransmitterSignalProcessingandControlforUMTS/FDD ...... 20

Table5.1:Front-endInterfacefunctionality ......................................................................................... 54

Table5.2:Exemplaryfront-endconfigurationparameters ................................................................... 55

Table5.3:TheselectedFDDHS-DSCHphysicallayercategory ........................................................ 56

Table6.1:PropagationConditionsforMultipathFadingEnvironments............................................. 58

Table6.2:ParameteroftheMovingPropagationConditions............................................................... 59

Table6.3:RequirementsForSpuriousEmissions(FDD) .................................................................... 60

Table6.4:AdditionalRequirementsForSpuriousEmissions(FDD) .................................................. 60

Table6.5:ChannelModelParameters .................................................................................................. 61


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1 Introduction

Inthisdocumentanoverallmulti -modearchitectureofthemob ileterminalcoveringthreemodes,

namelyUMTS/FDD,UMTS/TDD,andHSDPA/FDDwillbeproposed. Firstofall, systemrequirementsofthemulti -modere-configurableterminalwillbepresented. Inorderto explor eand

developare -configurablearchitecture,so metypicalfeaturesspecifiedinthestandardsneedtobe

supported.Inthiswaytherequiredeffortcanbeputinthescopeoftheproject.

Beforegoingintomulti-modearchitecture,eachsingle-modearchitecturewillbeexaminedseparately,

sothatacl earunderstandingoftheuniquefeaturesofeachmodeandthesimilaritiesamongallthe

threemodescanbeacquired.Then ,amatrixlikeblockdiagramwillbeproposed.Eachrowofthis

matrixreferstoaspecificmode,i.e.standard,andeachcolumncons istsofallthesimilarfunctions

belongingtodifferentmodes.Thegroupingofidenticalfunctionsintocolumnswillbedoneat

functionallevel.Furthercolumnpartitioningbyfurtherinspectionsinareassuchasrequired

processingspeed,memory,anddatasizewillbeconsidered.

Interfacingbetweenfront-endandbasebandpartsinmulti -modesystemisofmoreimportancethanin

thesinglemodesystem.Re -configurabilityandmulti -modefeaturesarethetargetforbothparts,and

theirinterfaceshouldref lectthat.Hereageneralinterfacethatiswellcapableofcopingwiththe

evolutionofthefront -endandbasebandpartswillbedescribed.Alsochannelmodelsforthe

verificationofthedifferentfunctionalitiesofthemulti-modesystemwillbespecified.


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U

channelcoding

timeMUXed

withDPDCH

PayloadData

Source/

Drain*

U

C

C

C

C

C

C

Spread

Modulate

Chip-wise

sum

ChannelModel

Front-EndModel

Demodulate

De-Spread

channeldecoding

UTRAN UEPayloadDataSource/

Drain*

U

U

C

C

C

C

C

C

*U=Userplane,C=Controlplane

DPDCH

DPCCH

HS-PDSCH

HS-SCCH

CPICH

P-SCH

S-SCH

HS-DPCCH

4timesparalleltimeMUXed

withDPDCH

4timesparallel

Figure2.1:Physicalchannelsimplementationoverview

2.2 High-levelSystemRequirements

2.2.1 General

Thefunctionalimplementationiscompliantwith3GPPRelease5

DownlinkTxandRxmodemaresupposedtousedirectconversion

Supportformultiplededicateddatachannelsenablingconcurrentapplications

UseachannelequalizerorotheradvancedreceivertechniquesattheDLRxtoreducethechipinterferencecomparedtoRAKE

Rxsynchronisationfeatures:

o Frameandslotsynchronisation

o Frequencysynchronisation

o Timingsynchronisation

Staticlinkconfigurationatsimulationstart,noautomaticlinkadaptationthroughhigherlayerassignment

Completewirelessdownlinksimulated(alldownlinkchannelsthroughchannelmodelandreceivermodel);uplinkwillbesimplified

Notsupported:

o Anyhandoverrelatedproceduresandotherrequirements

o Anypowercontrolrelatedprocedureandotherrequirements

o Connectionset-up(radiolinkestablishmentandrelease)

o FlexiblepositionsofTrCHsinCCTrCh

o Beamforming

o MIMO

o Txdiversity


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2.2.2 UMTSFDDSpecific

None,thegeneralrequirementsfromthechapteraboveapplyhere

2.2.3 UMTSTDDSpecific

Notsupported:TimingAdvanceprocedureforUL

2.2.4 HSDPASpecific

Thepacketdatatransmissionrateofupto10MbpsinHSDPAmodeshouldbeexaminedandsupportediffeasible

Twomodulationschemes:16-QAMandQPSK

H-ARQsupport

2.3 HigherLayerInterface

ThephysicallayerinteractsdirectlywiththeMAClayerandtheRRClayer.Statusandcontrol

primitivesareexchangedtoset -upandconfigureradiobearers,toreportmeasurements,toexchange

datafortransmissionordatathathasbeenreceived,andforfurtherpurposes.

Thischapterdescribestheservices,neededtointeractwiththeRRCandMAClayer.All

correspondinginformationelementshavetobepreviouslyknownbyL1andprovidedbyhigherlayers

oraremeasurementresults(see3GPPTS25.331).

Thelistoftheprimitiveslistedhererepresentstheinformation,whichhastobeexchangedbetween

thephysicallayerandtheprotocollayers.Thefinalimplementationinthesystemhastobede finedin

detail.

2.3.1 PrimitivesbetweenphysicallayerandMAClayer

ThefollowingprimitivesareusedtoenablesignallingbetweenMACandphysicallayer.

Requirement

(Reference:3GPPTS25.302)

MuMoRSystemSupport

10.1.1PHY-Access-REQ Notsupported

10.1.2PHY-Access-CNF Notsupported

10.1.3PHY-Data-REQ Supported

10.1.4PHY-Data-IND Supported

10.1.5PHY-CPCH_Status-REQ Notsupported10.1.6PHY-CPCH_Status-CNF Notsupported

10.1.7PHY-Status-IND Supported

Table2.3:PrimitivesbetweenL1andMAC

2.3.2 PrimitivesbetweenphysicallayerandRRClayer

ThefollowingprimitivesareusedtoenablesignalingbetweenRRCandphysicallayer.

Requirement


MuMoRSystemSupport

10.2.1.1CPHY-Sync-IND Supported

10.2.1.2CPHY-Out-of-Sync-IND Supported


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Requirement


MuMoRSystemSupport

10.2.1.3CPHY-Measurement-REQ Supported

10.2.1.4CPHY-Measurement-IND Supported

10.2.1.5CPHY-Error-IND Notsupported

10.2.1.6CPHY-CPCH-EOT-IND Notsupported

10.2.2.1CPHY-TrCH-Config-REQ Supported

10.2.2.2CPHY-TrCH-Config-CNF Supported

10.2.2.3CPHY-TrCH-Release-REQ Notsupported

10.2.2.4CPHY-TrCH-Release-CNF Notsupported

10.2.2.5CPHY-RL-Setup-REQ Supported

10.2.2.6CPHY-RL-Setup-CNF Supported

10.2.2.7CPHY-RL-Release-REQ Notsupported

10.2.2.8CPHY-RL-Release-CNF Notsupported

10.2.2.10CPHY-RL-Modify-CNF Notsupported

10.2.2.11CPHY-Commit-REQ Notsupported

10.2.2.12CPHY-CPCH-Estop-IND Notsupported

10.2.2.13CPHY-CPCH-Estop-RESP Notsupported

10.2.2.14CPHY-CPCH-Estop-REQ Notsupported

10.2.2.15CPHY-CPCH-Estop-CNF Notsupported10.2.2.16CPHY -Out-of-Sync-Config-REQ Supported

10.2.2.17CPHY -Out-of-Sync-Config-CNF Supported

Table2.4:PrimitivesbetweenL1andRRC

2.4 PhysicalLayerProcedures

InthephysicallayerofaCDMAsystemtherearemanyproceduresessentialforthesystemoperation.

TheseprocedureshavebeennaturallyshapedbytheCDMA -specificpropertiesofthephysicallayer.

Proceduresaredefinedin3GPPTS25.214fortheFDDandin3GPPTS25.224fortheTDDoption.

Table2.5givesanoverviewofdefinedproceduresandhowtheywillbesupportedintheMuMoRprojectfortheFDDandTDDoptions.

Procedure FDD TDD MuMoRSystemSupport

SynchronisationProcedure X X Partialsupport:Noradiolinkrelease

andestablishment,onlymonitoring .

Mainlycoveringthecellsearch

Powercontrol X X Notsupported

Randomaccess X X Notsupported

TransmitDiversity X X Notsupported

IPDLlocation X X Notsupported

TimingAdvance - X Notsupported


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NodeBSynchronization - X Notsupported

Discontinuoustransmission - X Notsupported

DSCHProcedure - X Notsupported

HS-DSCHrelatedprocedure X X Partialsupport:Nocompressed

mode.OnlyFDDmode

Table2.5:Supportofphysicallayerprocedures

AstheMuMoRprojectisconcentratingonthemulti -modeaspectsofUMTS/FDD,TDDand

HSDPA/FDDanditsimpactonthesignalprocessingarchitecture, thetargetimplementationwill

consideronlythesynchronizationprocedure(mainlythecellsearch)fromtheUMTSsystemandthe

HS-DSCHprocedurefortheHSDPA/FDDoption.Insteadofsignalprocessingmostoftheother

procedurearebasedoncontrolprocessing(StateMachines).

2.5 UEPhysicalLayerMeasurementAbilities

ThischapterdescribesallnecessaryminimumrequirementstofulfiltheUE sL1tasktoserve

measurementrequestsofhigherlayersintheUEandUTRAN.Thefollowingmeasurement

specificationsapplytotheUEinFDDmode,beingneitheraGSMnorGPScapableterminal.

ThelevelofsupportofphysicallayermeasurementsperformedbytheUEandreportedtohigher

layersaredefined.Onlymeasurementsaresupported,whicharerequiredbythesupp ortedprocedures

andcanbeperformedbecausetherequiredphysicalchannelsaresupported.Somemeasurementsare

relevantforbothFDDandTDDmode.ThemeasurementsaredefinedinTS25.215fortheFDDand

inTS25.225fortheTDDmode.

Table2.6givesanoverviewofdefinedmeasurementsandhowtheywillbesupportedintheMuMoR

project.

Measurement FDD TDD MuMoRSystemSupport

CPICHRSCP X X Notsupported

CPICHEc/No X X Notsupported

SIR - X Notsupported

TransportchannelBLER X X Supported

UTRAcarrierRSSI X X NotSupported

UEtransmittedpower X X NotSupported

SFN-CFNobservedtimedifference X X NotSupported

SFN-SFNobservedtimedifference X X NotSupported

UERx-Txtimedifference X - NotSupported

P-CCPCHRSCP X X NotSupported

TimeslotISCP - X Notsupported

Table2.6:SupportofUEmeasurementabilities

Theunsupportedmeasurementsaremostlyrelatedtofrequencyandcellhandoverorpowe rcontrol

andthereforenotimplemented.

2.6 UECapabilityParametersUEsarenotfullyspecifiedintermsoftheirradioaccesscapability.ToallowUEsofdifferent

complexitiesandcapabilitiesbeing3GPPcompliantanamountofparametershasbeendefined


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togetherwitharangeandgranularityofvalidvaluesforeachofthem.UTRANneedstorespectthe

UEcapabilitieswhenconfiguringtheradiobearers.

Thecapabilityparametershavetobeconsideredseparatefromthephysicallayerparameters,which

all havetobesupportedby any fullycompliantimplementation.ThefollowingtableliststheUE

radioaccesscapabilityparameters,whicharerelevantforthephysicallayerbase -bandinFDDuplink

andFDDdownlink.Foramoredetaileddefinitionoftheparamet erspleaserefertothe3GPPTS

25.306document.

2.6.1 UMTSFDD/TDDCapabilityParameters

ThefiguresgivenherehavebeentakenfromtheTS25.306.Thesamedocumentalsogivesreference

toUEradioaccesscapabilitycombinationsforallofthevaluestobeuse dfortestspecificationsand

forconformancetestingagainstreferenceradioaccessbearer(RAB)aswellasmoredetailed

explanationoftheUEradioaccesscapabilityparameterdescriptionusedinTable2.7.

Thetargetsystemvaluesgivenin Table2.7areforthereferencesimulationmodel.Theperformance

capabilitiesfortheHW/SWdemonstratormightbelowerduetoimplementationrestrictions.

Relevance UEradioaccesscap ability

parameter

Valuerange MuMoRSystemValue

Maximumsumofnumberof

bitsofalltransportblocks

beingreceivedatanarbitrary

timeinstant

640,1280,2560,3840,

5120,6400,7680,8960,

10240,20480,40960 ,

81920,163840

163840


bitsofallconvolutionally

codedtransportblocksbeing

receivedatanarbitrarytimeinstant

640,1280,2560,3840,

5120,6400,7680,8960,

10240,20480,40960,

81920,163840

163840

Maximumsumofnumbe rof

bitsofallturbocoded

transportblocksbeing

receivedatanarbitrarytime

instant

640,1280,2560,3840,

5120,6400,7680,8960,

10240,20480,40960,

81920,163840

163840

Maximumnumberof

simultaneoustransport

channels

4,8,16,32 4

Maximum numberofsimultaneousCCTrCH

1,2,3,4,5,6,7,8 1

Maximumtotalnumberof

transportblocksreceived

withinTTIsthatendwithin

thesame10msinterval

4,8,16,32,48,64,96,

128,256,512

512

MaximumnumberofTFC 16,32,48,64,96,128,

256,512,1024

1024

MaximumnumberofTF 32,64,128,256,512,

1024

1024

Transportchannel

parametersin

downlink

Supportforturbodecoding Yes/No Yes


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parameter



bitsofalltransportblocksbeingtransmittedatan

arbitrarytimeinstant

640,1280,2560,3840,

5120,6400,7680,8960,10240,20480,40960,

81920,163840

163840


bitsofallconvolutionally

codedtransportblocksbeing

transmittedatanarbitrary

timeinstant

640,1280,2560,3840,

5120,6400,7680,896 0,

10240,20480,40960,

81920,163840

163840


bitsofallturbocoded

transportblocksbeing

transmittedatanarbitrarytimeinstant

640,1280,2560,3840,

5120,6400,7680,8960,

10240,20480,40960,

81920,163840

163840

Maximumnumberof

simultaneoustransport

channels

2,4,8,16,32 2

Maximumnumberof

simultaneousCCTrCHof

DCHtype(TDDonly;for

FDDthereisalwaysone

CCTrCHatatime)

1,2,3,4,5,6,7,8 1

Maximumtotalnumberoftransportblockstransmitted

withinTTIsthatstartatthe

sametime

2,4,8,16,32,48,64,96,128,256,512

512

MaximumnumberofTFC 4,8,16,32,48,64,96,

128,256,512,1024

1024

MaximumnumberofTF 32,64,128,256,512,

1024

1024

Transportchannel

parametersinuplink

Supportforturboencoding Yes/No Yes

MaximumnumberofDPCH/PDSCHcodestobe

simultaneouslyreceived

1,2,3,4,5,6,7,8 8

Maximumnumberof

physicalchannelbits

receivedinany10 ms

interval(DPCH,PDSCH,S -

CCPCH)

600,1200,2400,3600,

4800,7200,9600,

14400,19200,28800,

38400,48000,57600,

67200,76800

76800

SupportforSF512 Yes/No Yes

SupportofPDSCH Yes/No No

FDDPhysicalchannelparameters

indownlink

SimultaneousreceptionofSCCPCHandDPCH

Yes/No No


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parameter


Simultaneousreceptionof

SCCPCH,DPCHandPDSCH

Yes/No No

Maximumnumberof

simultaneousS -CCPCH

radiolinks

1 1

Supportofdedicatedpilots

forchannelestimation

Yes/No Yes

Maximumnumberof

DPDCHbitstransmittedper

10ms

600,1200,2400,4800,

9600,19200,28800,

38400,48000,57600

57600FDDPhysical

channelparameters

inuplink

SupportofPCPCH Yes/No No

Maximumnumberof

timeslotsperframe

1..14 14

Maximumnumberof

physicalchannelsperframe

1,2,3..224 224(16codes

*14timeslots)

MinimumSF 16,1 16(SF1not

supported)

SupportofPDSCH Yes/No No

TDD3.84Mcps

physicalchannel

parametersin

downlink

Maximumnumberof

physicalchannelspertimeslot

1..16 16

MaximumNumberof

timeslotsperframe

1..14 14

Maximumnumberof

physicalchann elsper

timeslot

1,2 1

MinimumSF 16,8,4,2,1 16(othersnot

supported)

TDD3.84Mcps

physicalchannel

parametersin

uplink

SupportofPUSCH Yes/No NoTable2.7:Valuerangesforthephysicallayerradioaccesscapabilityparameters

2.6.2 HS-DSCHCapabilityParameters

FortheUEsupportingHSDPAmodeseveralcapabilityparametershavebeendefined.Otherthanfor

UMTSthevalidvaluesoftheseparameterscannotbechosenfreely.ApredefinedHS-DSCHcategory

definedbyafixedcombinationofcapabilityparame tershastobechosen.TheHS -DSCHUE

capabilitiesareclassifiedaccordingtothefollowingcategories:

HS-DSCH

category

Maximumnumber

ofHS -DSCH

codesreceived

Minimuminter -TTI

interval

Maximumnumberofbits

ofanHS -DSCHtransport

blockreceivedwith inanHS-DSCHTTI

TotalNumberof

softchannelbits

Category1 5 3 7300 19200

Category2 5 3 7300 28800


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Category3 5 2 7300 28800

Category4 5 2 7300 38400

Category5 5 1 7300 57600

Category6 5 1 7300 67200

Category7 10 1 14600 115200Category8 10 1 14600 134400

Category9 15 1 20432 172800

Category10 15 1 28776 172800

Table2.8:FDDHS-DSCHphysicallayercategories

Theselectedcategoryforthetargetsystemiscategory10,asdescribedinTable2.9.

HS-DSCH

category

Maximumnumber

ofHS -DSCH

codesreceived

Minimuminter -TTI

interval

Maximumnumberofbits

ofanHS -DSCHtransport

blockreceivedwithinan

HS-DSCHTTI

TotalNumberof

softchannelbits

Category10 15 1 28776 172800

Table2.9:TheselectedFDDHS-DSCHphysicallayercategory


19/63


3 OverviewoftheConstitutingSinglemodeArchitectures

3.1 BasebandArchitectureforUMTS/FDDAgeneraldescriptionoftheli nklevelforUL/DLofUMTS/FDDwillbepresentedhere,and

functionalityoftheconstituentblockswillbedescribed.Thissection willgiveaclearunderstanding

ofthereceiveralgorithmsinUMTS/FDDmode.

3.1.1 BasebandSignalProcessing

Anarchitecturalover viewofthe basebandsignalprocessing ofUMTS/FDDwillbegiven inthis

section.

Theoperationalblockswithinbothreceiverandtransmitteraregroupedbasedonthesignaltypethat

theyprocess(sample,chip,physicalchannelandtransportchannel)and ontheirfunctionalrole

(processingcontrolorjustprocessing). Table 3.1and Table3.2 showthereceiverandtransmitteroperationalblockgrouping.

SampleProcessing ChipProcessing PhysicalChannel

Processing

TransportChannel

Processing

RxSignal

Processing

Control

1. RxGain

Controller.

2. D.LTime

Controller.

3. CellSearcher.

4. Multipath

Searcherand

Channel

Estimator.

5. DLTraining

Sequences,Pilots

andCodesSignatures

Generator.

6. FrequencyOffset

Estimator.

7. CRCCheck

Rx

Baseband

Signal

Processing

1. A.D.C.

2. RxPulse

Shaper.

3. Feedback

Frequency

Synchroniser.

4. RAKEReceiver

5. Forward

Frequency

Synchronizer.

6. DLSoftBit

Mapper

7. PhysicalChannel

De-Mapper.

8. 2nd

De-

Interleaver.

9. PhysicalChannel

De-Segmentation.

10.TransportChannel

De-Multiplexer.

11.RadioFrameDe-

Segmentation.

12.1st

De-Interleaver.

13.DTXRemoval.

14.RateDe-Matching.

15.ChannelDecoder.

16.TransportBlock

De-Concatenation

andCodeBlock

Desegmentation.

Table3.1:BlockswithinBasebandReceiverSignalProcessingandControlforUMTS/FDD

SampleProcessing ChipProcessing PhysicalChannel

Processing

TransportChannel

Processing

TxSignal

1. TxGain

2. ULPilotsand


20/63


Processing

Control

Controller. CodesSignatures

Generator.

Tx

BasebandSignal

Processing

1. PulseShaper.

2. TxTruncator

3. DAC

4. Spreaderand

Modulator.

5. Transport

Multiplexer.6. PhysicalChannel

Segmentation.

7. 2nd

Interleaver.

8. PhysicalMapper.

9. CRCAttachment.

10.TransportBlockConcatenationand

CodeBlock

Segmentation.

11.ChannelCoder.

12.RadioFrame

Equalizer.

13.1st

Interleaver.

14.RadioFrame

Segmentation.

15.RateMatching.

Table3.2:BlockswithinBasebandTransmitterSignalProcessingandControlforUMTS/FDD

Figure3-1showstheBasebandReceiverSignalProcessingandControlsignalflow,where:

AnalogueRxSignalisthereceivedsignalfromtheRFFrontEnd

RxSetGainrepresentstherequiredRFgaininordertooperatetheADCsatoptimumscalegain

FeedbackControlParametersusedforclose-loopfrequencyandtimecontrol.

CellParametersforUTRAFDDthisisjustthescramblingcodenumberthatwillbeusedto

generateDLTrainingSequences,PilotsandCodesSignatures(scramblingandOVSFcodes).

PhysicalChannelsSoftBitsarethebitmappedcodechannelsymbols.

TrChDe-MuxSoftBitsarethede-multiplexedTransportchannelssoftbits.

ReceivedDLDatarepresentsthereceived,decodedandCRCcheckedinformationbits.

Figure3-1:BasebandReceiverSignalProcessingandControl,SignalFlow

Figure3-2showstheBasebandTransmitterSignalProcessingandControlsignalflow,where:

ULDatarepresentsthehigherlayerdatathathastobetransmittedonuplink.

TrChRateMatchedBitsaretheratematchedTransportchannelsbits.

PhysicalChannelsBitsarethebitsthathavetobymappedtocodechannelsymbols,modulated

andspread.

Received

DLData

RxSample

Processing

RxChip

Processing

Transport

Channel

Processin

Chips

Cell

Parameters

FeedbackControl

Parameters

Physical

Channels

SoftBits

Analogue

RxSi nal

RxSetGain

Frame

Timing

Physical

Channel

Processin

TrCh

De-MuxSoftBits


21/63


AnalogueTxSignalisthesignalsenttotheRF-FrontEndtransmitter.

CodeChannelsGainsandTxPowerarethecodechannelnormalizedgainsandtherequired

transmissionpower.Theseareusedtosetthetransmittergains.

Figure3-2:BasebandTransmitterSignalProcessingandControl,SignalFlow

3.1.2 FDDBasebandSampleProcessingFigure 3-3showsthesignalflowwithintheTransmitterBasebandSampleProcessingwherethe

processflowcouldbedescribedasfollow:

TheUplinkchipstobetransmittedarepulseshapedandrateconvertedbytheTxPulseShaper

ThepulseshapedsamplesarebitequalizedatanoptimumwordlengthbytheTxTruncator.

ThelevelofwordtruncationoftheComplexSamplesissetbytheTxGainControllerandwill

dependonthenormalizedgainsofthecodechannels(CodeChannelsGains)describingthe

uplinkphysicalchannel.

FinallythedigitalsamplesareconvertedtotheAnalogueTxSignalbytheDACsandtheRF

Front-EndgainissetbytheTxGainController.

Figure3-3:TransmitterSampleProcessing,SignalFlow

Figure3-4showsthesignalflowwithintheReceiverBasebandSampleProcessing.Processflow

wise,theReceiverSampleProcessingcouldbedescribedasfollow:

ThegainseenattheADCinputismeasuredandcontrolledbytheRxGainController.

Assuminganearly-lateclose-looptimecontrol,theEarly,In -timeandLateChipsFingersare

obtainedbytheRxPulseShaperwhichfiltersanddecimatestheComplexSamplestochip

rate.Thechipfingeroffset(DLChipOffsets)andtheframetimingareadjustedbytheDLTimeControllerbasedonthemultipathgains(MPGains)feedback.

TheInitialTimingandtheCellParametersaregivenbytheCellSearcher.

DAC

TxPulse

ShaperchipsComplex

SamplesAnalogue

TxSignal

CodeChannels

Gains

TxGain

Controller

TxPower

TxSet

Gain

WordTruncation

Level

Tx

Truncator

Truncated

Samples

UL

Data

RxSample

Processing

RxChip

Processing

Transport

Channel

Processin

Chips

CodeChannels

Gains

Physical

Channels

Bits

Analogue

TxSi nal

TxSet

Gain

Physical

Channel

Processin

TrCh

Rate

MatchedBits

TxPower


22/63


FinallythechipfingersarefrequencysynchronizedandsenttotheRxChipProcessing.

Figure3-4:ReceiverSampleProcessing,SignalFlow

3.1.2.1 PulseShaping(TransmitandReceive)

Thepulseshapingfilteratthetransmitterisspecifiedin3GPP25.101asaroot -raised-cosine

(RRCos).Transmitandreceivepulseshapingfilterstogether ,trytominimizetheinter -chip-interference,bysatisfyingtheNyquistcriterionthroughtheappropriateraisedcosinepulseshaping.

However,someamountofinter-chip-interferencewillstillbeinducedthroughthefrequencyselective

behaviourofthemultipathchannel.

Figure 3-5and Figure 3-6showthetypicalsignalprocessingfortransmitterandreceiverpulse

shapingelements.ThereceiverdelayelementiscontrolledbythereceiverDLTimeControllerin

ordertomaximizetheSIRattheoutputoftheRAKEreceiver.

Figure3-5:TypicalTxpulseshaping(controlleddelayforTDDonly)

Figure3-6:TypicalRxpulseshaping(controlleddelayforbothFDDandTDD)

ForUL(transmitting)onlyonepulseshapingelementexistsatalltimes. ForDLtherecouldbemore

thanoneDLsourceswithdifferentchipoffsets(ifDLdiversityisconsidered).Awaytominimize

RRCos

Filtercomplex

samples

chips

Z-D

ULChipOffset

RRCos

Filter

complex

sampleschips

Z-D

DLChipOffset

Feedback

Control

Parameters

RxPulse

Shaper

CellSearcher

FeedbackFrequency

Synchronizer

RxGain

Controller

Early,In-

timeand

LateChips

Fingers

Initial

TimingD.LTime

Controller

M.P.

Powers

EarlySync

Chips

LateSync

Chips

In-TimeSync

ChipsA.D.C Complex

Sam les

FrameTiming

Feedback

Frequency

Offset

Chips

D.LChip

Offsets

AnalogueRxSignal

RxSetGainCell

Parameters


23/63


thenumberofPulseShapingElementsrequired,istouseaunionbasedmethodforgeneratingchips

withsameoffsets,butallocatedtodifferentsources.

3.1.2.2 CellSearching

ThepurposeofInitialCellSearcheristoacquiretiming informationofthenearest(orstrongest)basestation.In 3GPPspec ifications,thereare2synchronizationchannels usedinthe downlinkofeach

cell,namelyasPrimarySynchronizationChannel (P-SCH)andSecondarySynchronizationChannel

(S-SCH).Thereisalsoacommonpilotchannel(CPICH).Cellsearchprocessconsistsof3stepsusing

these3channelsforsynchronization,codegroupidentificationandcellidentification. Thefirststepis

tofindslottimingusingP-SCH,thesecondstepistofindframetimingandcodegroupusingS -SCH,

andthethirdstepistoidentifythe cellspecificscramblingcodeusingCPICH. DuringSTEP3ofthe

cellsearchprocedure,theUEdeterminestheexactprimaryscramblingcodeusedbythefoundcell.

Theprimaryscramblingcodeistypicallyidentifiedthroughsymbol -by-symbolcorrelationover the

CPICHwithallcodeswithinthecodegroupidentifiedin STEP2.Thereare8scramblingcodesin

eachcodegroup.Aftertheprimaryscramblingcodehasbeenidentified,thePrimaryCCPCHcanbe

detected.Andthesystem-andcellspecificBCHinformationcanberead.IftheUEhasreceivedinformationaboutwhichscramblingcodestosearchfor,steps2and3above

canbesimplified.

3.1.2.3 DLTimeControl

Thisblocktracksthetimevaryingdelayofeachpathassociatedwith thefingersoftherakereceiver.

Thistrackingcanbebasedonearly -latedelaydiscriminatorapproach.Inthisapproach,themetrics

fortimecontrolaretheM.P.Gains,whicharethepowersumsoftheearly,in -timeandlate

multipathweights(seesection 3.1.3.3).TheDLTimeControlwilladjustthetimingtofollowthe

highestofthesepowergains(peaksearchapproach).

ThistrackingstrategyimpliesthattheCellSearchdoesaninitialchiplevelsynchronization

(acquisition)andthereportedtimi ngiswithinthefractionaldelayresolutionrequirements.Ifthisisnotthecaseortheoffsetchangesbyavaluelargerthan thedelayresolutionrequirements,thetime

differencebetweenthechipfingersshallbesetatavaluelargerthan the PulseShapingDelay

Resolutionandgraduallyreduced(i.e.bisected).Inthiscase,thecurrenttimechangecouldbe

calculatedusinga2nd

orderpolynomialpeaksearchontotheM.P.Powers.

3.1.2.4 FeedbackFrequencySynchronization

Theneedofcarriersynchronizationatthispointonthesignalflowismainlymotivatedbythe needto

reducesinc-aliasingcode-channelsmearing(whichcausesco -channelinterference)andtoimprove

thequalityofthemulti -pathestimation.Implementation -wisethisprocesscouldem bedaDigital

ControlledOscillatoranddigitalcomplexmixersforcomplexsine -wavemultiplicationofthe

receivedchips.ThemaincontributiontothecarrierfrequencyoffsetaretheDopplerShift(vehicularspeedlimited

to250km/h)andinstabilitiesofbothNodeBandUserEquipmentlocaloscillators(constrainedbythe

conformancerequirements)andcouldbeshownthatmaximumcarrieroffsetisaround 20kHz.

Thereforethesynchronizationafterpulseshapingcausesanignorablespectraldistortion (compare

RRCosBW=3.84MHz1.22with20kHz),butreducestheamountofprocessing.

Notethatfrequencysynchronizationshallbedoneforallchipfingers(early,in-timeandlate).

3.1.3 FDDBasebandChipProcessing

Figure 3-7show sthesignalflowwithintheTransmitterBasebandSampleProcessingwherethe

processflowcouldbedescribedasfollows:

ThePhysicalChannelsbitsaremodulatedbytheSpreaderandModulatorintothetransmitted

chips.


24/63


TheSpreaderandModulato rmultiplexesthePilotBitswithinDCPCHandusestheCh

SignaturesgeneratedbytheULPilotsandCodesSignaturesGenerator.

Figure3-7:TransmitterChipProcessing,SignalFlow

Theblockdiagram of Figure 3-8showsthesignalflowwithintheReceiverBasebandChip

ProcessingandControl.

Processflowwise,theReceiverChipProcessingcouldbesummarizedasfollow:

TheMultipathSearcherestimatesthein -timemulti pathchannelcomplexweights(MP

Weights)andusesthein -time,earlyandlatepowergains(MPPowers) tosearchthe

multipaths.ThepowergainswillbefedbacktotheDLTimeControllerfortimetracking.

TheRAKEReceiverfirstcombinestheI n-TimeSyncChipswiththeMPWeightsandthen

descramblesanddespreadstheresultusingtheChSignatures.TheRAKEReceiver willoutput

theCodeChannelsSoftSymbols.Undercertainconditionsanoptionallevelofequalization

couldbeconsideredwithintherakereceiver.

TheresidualfrequencyoffsetisestimatedusingtheCodeChannelsSoftSymbols.

TheForwardSymbolsFrequencySynchronizercompensatesthechannelsresidualfrequency.

Finally,thePhysicalChannelsSoftBitsareobtained bybitmappinganddiversitycombiningof

theChannelsSyncSymbols.

U.L.PilotsandCodes

SignaturesGenerator.

Physical

ChannelsBits

chipsSpreaderandModulator

PilotBits ChSignatures

CodeChannels

Gains


25/63


Figure3-8:ReceiverChipProcessing,SignalFlow

3.1.3.1 TransmitterSpreadingandModulation

Spreadingisappliedtothephysicalchannels.It consistsoftwooperations.Thefirstisthe

channelisationoperation,whichtransformseverydatasymbolintoanumberofchips,thusincreasing

thebandwidthofthesignal.ThenumberofchipsperdatasymboliscalledtheSpreadingFactor(SF).

Thesecondoperationisthescramblingoperation,whereascramblingcodeisappliedtothespread

signal.

Withchannelisation,datasymbolsonso -calledI-andQ -branchesareindependentlymultipliedwith

anOVSFcode.Withthescramblingoperation,theresultan tsignalsontheI -andQ -branchesare

furthermultipliedbycomplex -valuedscramblingcode,whereIandQdenoterealandimaginary

parts,respectively.

j

I+jQ

Spreading

by

Channelization

Code

SetGainfor

EachChannelPhysicalChannelsbits

OVSFcodeCodeChGains

Scramblecode

chips

ChSignatures

Figure3-9:Spreadingforuplink

3.1.3.1.1 DPCCH/DPDCH/HS-DPCCH

Figure3-10illustratestheprincipleoftheuplinkspreadingofDPCCH,DPDCHs andHS -DPCCH.

ThebinaryDPCCH,DPDCHsandHS-DPCCHtobespreadarerepresentedbyreal-valuedsequences,

M.P.

Weights

RAKE

Receiver

LateSync

Chips

In-Time

SyncChips

MultiPath

Searcherand

Channel

Estimator

Training

Sequences,Pilots

andCodes

SignaturesGenerator

Feedback

FrequencyOffset

CodeChannelsSoftSymbols

ChSignatures

FrequencyOffsetEstimator

DLSoft

Bit

Mapper

EarlySync

Chips

Forward

Symbols

Frequency

Synchronizer

Channels

SyncS mbols

Physical

ChannelsSoftBits

M.P.

Gains

Training

Sequences

ChForward

FreqOffset

Frame

Timing

FeedbackControl

Parameters

chips


26/63


i.e.thebinary value"0"ismappedtotherealvalue+1,thebinaryvalue"1"ismappedtothereal

value 1,andthevalue"DTX"(HS -DPCCHonly)ismappedtotherealvalue0.TheDPCCHis

spreadtothechipratebythechannelisationcodec c.The n:thDPDCHcalledDPDC Hnisspreadto

thechipratebythechannelisationcodec d,n.TheHS -DPCCHisspreadtothechipratebythe

channelisationcodeC HS.OneDPCCH,uptosixparallelDPDCHs ,andoneHS -DPCCHcanbetransmittedsimultaneously,i.e.1n6.

I

j

c d,1 d

S dpch,n

I+jQ

DPDCH 1

Q

c d,3 d

DPDCH 3

c d,5 d

DPDCH 5

c d,2 d

DPDCH 2

c d,4 d

c c c

DPCCH

S

C HS HS -DPCCH (IfN max -dpdch =odd)

DPDCH 4

C HS HS -DPCCH (IfN max -dpdch =even)

HSPowersettin gforHS -

HSPowersettin gforHS -DPCCH

Figure3-10:SpreadingforuplinkDPCCH,DPDCHsandHS-DPCCH

Afterchannelisation,thereal-valuedspreadedsignalsareweightedbygainfactors, cforDPCCH,d

forallDPDCHsand HSforHS-DPCCH(ifoneisactive).

Aftertheweighting,thestreamofreal -valuedchipsontheI -andQ -branchesarethensummedand

treatedasacomplex -valuedstreamofchips.Thiscomplex -valuedsignalisthenscra mbledbythe

complex-valuedscramblingcodeSdpch,n.Theappliedscramblingcodeisalignedwiththeradioframes,

i.e.thefirstscramblingchipcorrespondstothebeginningofaradioframe. Formoredetails,seethe

specification3GPPTS25.213v5.1.0.

3.1.3.2 Modulation

Seethespecification3GPPTS25.213v5.1.0.

3.1.3.3 MultipathSearchingandChannelEstimation

Figure3-11showstheblockdiagramofaMultipathSearchingforasingledownlinksource.


27/63


Figure3-11:MultipathSearching

Themulti-pathchannelisestimatedforthein -timechipsforalldelaysoveramaximumsearching

rangeandonlythestrongestpathsareselected(bytheWeightsONSelector).Assuminganearly -

lateclosed -looptimesynchronization,thechannelisagainestimatedonlyatthedelaysassociated

withthein-timestrongestpaths(atPositionofDelaysON).

Theresultedpowervalues(seeFigure3-12)areusedasmetricsbytheDLTimeControllerfortime

trackingandtheMPWeightsareusedbytheRAKEreceivertoexploitthemultipathdiversityby

MaximalRatiocombiningthein-timechips.

Figure3-12:MultipathPowerEstimator,BlockDiagram

3.1.3.4 TheRAKEReceiver

Multipath

Power

Estimator

MPPowersEarlyPath

Weights

LatePath

Weights

in-time

chips

MPWeights

(In-time)

early

chips

TrainingSequence

MaximumSearchingRangeChannelEstimator

latechips

TrainingSequence

Weights

ON

Selector

SelectedTapsChannel

Estimator

SelectedTapsChannel

Estimator

TrainingSequence

Positionof

DelaysON

|| ||2

|| ||2

|| ||2LatePathWeights

EarlyPath

Weights

In-timePath

Weights

Early

Power

In-time

Power

LatePower

MP

Powers


28/63


In theRAKEreceiveraMaximalRatioCombiner(MRC) isusedtocombine themultipath sto

increasetheSIRofthereceivedsignal. Figure 3-13showssuchanarrangement,wherethelinear

MaximalRatioCombinerprecedestheDescramblerandDespreaderblock.

Figure3-13:RAKEReceiver

Forlowspreadingfactors,becauseofthelowprocessinggain ,theamountofinter-pathandinter-user

interferencecoul dbeconsiderable .Equalizationandinterferencecancellationmayberequired.For

example,iftheMPWeightsconvolutionmeasured inrespecttotheIn -timeGaindividedbythe

channelspreadingfactorislargerthanasetthresholdfurtherequalizatio nmaybeneeded.If

equalizationisperformed,aPreandPostcancellationmethodshouldbepreferredoverother

methodssuchasZero-Forcing(becauseofthespectralnullspresenceinamobileenvironment).

Figure3-14showsanexampleofanMRCandchiplevelPreandPostdecisionbasedequalization

where:

- TheDecisionBlockattemptstoestimatethetransmittedchips.Notethatonlythechannelsof

interestcouldbemonitored.

- EqualizationFilterisanodd -symmetricFIR withthecoefficientsgivenbythecircular

convolutionoftheMPWeightsnormalizedtotheweightspowergain(In -timeGain),butwith

thecentralcoefficient(tap)settozero.

- SF:themaximumspreadingfactor

- N:theMRCdelay

- |SF-N|:theabsoluteof(SF-N)

Figure3-14:ExampleofRAKEMRCandChipLevelPreandPostDecisionBased

Equalisation

Notethattheaboveexampleperformsequalizationatthechiplevel,butcouldbereducedtoasymbol

levelequalization.

3.1.3.5 ForwardSymbolsFrequencySynchronization

AsopposedtotheFeedbackFrequencySynchronization,thisblockoperatesinforwardmodeand

itsscopeistocompensatefortheresidualcarrieroffsetleftafterfeedbacksynchronizationat

channelsymbollevel.Thiswilltendtoreducethesymbolshiftingandcouldbethought of asa

In-time

SyncChips

Descramblerand

Despreader CodeChannels

SoftSymbols

Channel

Signatures

MRC

MPWeights

CodeChannels

SoftSymbols

M.R.C.

Decision

Block

+

_

Z-(SF+N)

Equalization

Filter

Descrambler

and

Despreader

Z-|SF-N|

In-time

SyncChips


29/63


refinementofthecarrierrecovery.ImplementationwisethisprocesscouldembedaDigital

ControlledOscillatoranddigitalcomplexmixersforcomplexsine -wavemultiplicationoftheCode

ChannelsSoftSymbols.

3.1.3.6 DLSoftBitMappingThisprocessmap sthereceivedcomplexchannelssymbolstothePhysicalChannelSoftBits.The

recommendedmethodforQPSKconstellationistheprojectionsofchannelsymbols intothe

decisionboundary.Forhigherordermodulation ,reliabilityofeachbitcanbecomputedby

averagingreliabilityofalltheconstellationsymbolsthathavethesamevalueforthatbit.

3.1.3.7 FrequencyOffsetEstimation

Variousmethodsforfrequencyes timationaredescribedandcomparedin[Agapciuc2002],[Hanzo

2000]and[Meyer1998].Ifadata -aidedmodeischosenforfrequencyestimation,onlythepilot

symbolsshouldbeconsideredattheinputoftheFrequencyOffsetEstimator.Amethodthatwork s

forbothdata -aidedandnotdata -aidedisthephasemultiplicationmethod,whichcouldbecombined

withaFitzestimator(referredin[Meyer1998]asD -Spacedestimator)togivethebestresults(see[Agapciuc2002]).ForthismethodalltheM -PSKmodu latedsymbolscouldbeused(meansthat

Type316-QAMHSDPAsymbolsshouldbeexcluded)wherethephasemultiplicationfactorequals

M.TheFeedbackFrequencyOffsetoutputistheangularfrequencyoffsetnormalizedtothechip

rate,wheretheChFor wardFreqOffsetistheangularfrequencyoffsetnormalizedtoeachcode

channelsymbolrate.

3.1.3.8 CodeGeneration

ForFFDDL(receiver)theCodeGenerationproducesthe:

FDDDLScramblingandOVSFcodes

TrainingsequencesforMultipathSearchingandChanne lEstimation(i .e,P-CPICH,DCHpilot

chips)

ForFFDUL(transmitter)theCodeGenerationproducesthe:

FDDULScramblingandOVSFcodes

FDDULDCPCHpilotbits

NotethatsameOVSFcodegenerationcouldbeusedforbothULandDL.

3.1.4 TransmitterTransportChannelProcessing

Figure3-15showstheprocessingchainofthetransmi tterTransportChannelProcessing,wherethe

ULDatabitsarecoded,interleavedandratematched.

CRCAttachment

TrBkConcatenation

CodeBlocksegmentation

ChannelCoding

RadioFrameEqualization

1stInterleaving

RadioFrameSegmentation

RateMatching

TrChRateMatched

Bits

U.LData

Figure3-15:TransmitterTransportChannelProcessing,BlockDiagram

3.1.4.1 CRCAttachment

TheCRCbitwillbeappendedtoeachtransportblock.CRCsize,whichvariesfrom24,16,12,8to0

willbedeterminedbyhigherlayercontrol.

3.1.4.2 Transportblockconcatenation/segmentationandchannelcoding

AlltransportblocksinaTransportTimeInterval(TTI)areseriallyconcatenated.Iftheconcatenated

stringsizeislargerthenthemaximumallowablesizeforthecodeblock,thencodeblock

segmentationwillbeperformed.Theallowableblocksizeforturbocodingis40 X5114andX


30/63


504forconvolutioncoding.Allsegmentedblocksmustbeofthesamesize.Ifthisisnotpossible,

thenfillerbitswillbeaddedtothestartofthe1st

block.Afterchannelcoding,iftherearemorethan1

encodedblock(i.e,morethen1segmentationblock),theywillbeseriallyconcatenated.

3.1.4.3 Radioframesizeequalisationand1

st

interleavingTheradioframesizeequalisationappendstheinputdatawith{0,1}sothat theoutputstreamcanbe

segmentedintothesamesizeframeforratematching.Bitsaresplitintocolumn/sinthe1st

interleaver

dependingontheTTIlength.Incompressmodebypuncturing,radioframesaremarkedinpositions

correspondingtothestartingbitsoftheradioframes.Bitsarereadintoamatrixinrows,column -wise

interleavingisdonethroughpermutationpatternsdependingontheTTIlength.Theoutputsareread

outincolumns.

3.1.4.4 RadioframesegmentationandRatematching

IftheTTIislong erthen10ms,theinputsequencewillbesegmentedandmappedontoconsecutive

radioframes.Theratematchingblockrepeatsorpuncturesbitsonatransportchannelsothatthe

channelbitratecanbemetaftertheTrCHmultiplexing.Bitseparationisdon eonlyonturboencodedTrCHinpuncturingcase.ForthecaseofturboencodedTrCHwithrepetitionandconvolutionally

encodedTrCH,bitseparationfunctionistransparent.Thedecisionofbitpuncturingandrepetitionis

controlledbyhigherlevelsignallingandisdoneattheratematchingalgorithmblock.Puncturingbits

willberemovedatbitcollection.

3.1.5 TransmitterPhysicalChannelProcessing

Figure3-16showstheprocessingchainofthetransmitterPhysicalChannelProcessi ng,wherethe

TrChRateMatchedBitsaremultiplexed,interleavedandmappedtothePhysicalChannelBits.

TrCh

Multiplex

Phys.ChannelSegmentation

2ndInterleaving

Phys.ChannelMapping

TrChRateMatchedBits

PhysicalChannelBits

Figure3-16:TransmitterPhysicalChannelProcessing,BlockDiagram

InTrCHmultiplexing,each10msradioframefromindividualTrCHwillbeseriallymultiplexedinto

acodedcompositetransportchannel(CCTrCH).TheCCTrCHarethenbeingdividedintodifferent

PhCHsduringPhCHsegmentation,whenmorethenonePhCHareus ed.Bitsthataremarkedbefore

the1st

interleaver,willberemoved.Atthe2nd

interleaver,inputisreadintoa30columnsmatrixin

rowwise.Blockinterleavingisdoneherethroughaninter -columnpermutationpattern.Outputisread

outcolumnwise.Duringphysicalchannelmapping,inputismappedontothephysicalchannel.Inthe

uplink,eachtransmissionframeiseithercompletelyfilledornotusedatall,exceptforcompress

modewheretransmissionisturnedoffduringTGL.However,thereisnosuc hrestrictioninthe

downlink.

3.1.6 ReceiverPhysicalChannelProcessing

Figure3-17showstheprocessingchainofthereceiverPhysicalChannelProcessing,where:

PhyCHde-

mapper

2ndDe-

Interleaving

PhyCHde-

segmentation

TrCHDe-

multiplexer

PhysicalCh

SoftBitsTrCHDe-Mux

SoftBits

Figure3-17ReceiverPhysicalChannelProcessing,BlockDiagram

ThedemappedPhCHisinputintothe2 nddeinterleavingblockwheretheinversionofthe2 ndinterleaverwillbedoneusingthesamepermutationpatternasthatinthetransmitter.

With morethen1PhCH,eachPhCHwillbecombinedtoformoneCCTrCHinthePhCH

desegmentationblock.


31/63


TheTrCHwillbedemultiplexedformthecodedcompositetransportchannel(CCTrCH)intheTrCHdemultiplexingblockaccordinglyintorespective10msradioframe.

3.1.7 ReceiverTransportChannelProcessing

Figure3-18showstheprocessingchainofthereceiverTransportChannelProcessing,where:

RadioFrameDe-

Segmentation

1stDe-

Interleaving

DTX

Removal

RateDe-

Matching

Channel

Decoding

TrBkDe-Concatenation

CodeBlockDe-

Segmentation

CRC

Check

TrCHRate

MatchedBits

DL

Data

Figure3-18ReceiverTransportChannelProcessing,BlockDiagram

Theradioframeisreconstructedfromthesegmentationdoneinthetransmissiontofitthe1 stdeinterleaverblocksize.

Aninversionofthe1stinterleavingisdoneusingasamepermutationpattern.

1stDTXRemovalisrequiredforfixedpositionsofTrCHs.

WhenpuncturingisdoneintheNodeBtransmitter,bitsinsertionwillbedonehere.Inthecaseofsoftbits,bitswithneutralweightagewillbeinserted.Forbitrepetition,therepeated

bitwillberemoved.

ThedecodingfortheconvolutionalcodewillmostlikelybedonethroughViterbidecodingandturbocodewillmostlikelybeprocessedwithiterativedecoder.Afterchanneldecoding,

thetransportblockwillbereconstructedforCRCcheck.

TheCRCbitsa recheckedandwillbedetachedfromeachtransportblock.IferroroccursintheCRCcheck,retransmissionwillbenecessary.Aswiththetransmitter,CRCsizewillbe

informedthroughhigherlayercontrol

3.2 BasebandArchitectureforUMTS/TDD

Ageneraldesc ription forthelinklevelUL/DLofUMTS/TDDwillbepresentedhere,and the

functionalityoftheconstituentblockswillbedescribed.Thissectionshouldgiveaclear

understandingofthereceiveralgorithmsintheUMTS/TDDmode.

3.2.1 Transmitter

Afirstorde rsubdivisionofthetransmittermoduleisshownin Figure 3-19.Manymodulesofthe

transmitterareidenticaltothoseusedby UMTS/FDDmode(channelcoding,spreading,etc.),and

havenotbeendescribedinthissectiontoavoidmultipledescriptions.


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TrCHCoding#1

TrCHCoding#K

TrChMultiplex

CCTrCH

PHYTX(Uplink)

Modulation

Spreading/Scrambling

MidambleInsertion

PHYCHFormation

Figure3-19:BlockDiagramoftheTransmitter.

3.2.1.1 TrCHCoding

Functionalities:thisblockreceivesthebinarysequencegeneratedbythedatasource,andperform s

processingtomakethetransmittedsequencemoreresistantagainstchannelimpairments.The

processingoperationsperformedwithinthisblockare:

Channelcoding

Interleaving

Datablocklength/sizemanagementoperations.Theseoperationsareintended torearrange

thedatasothattheblocksinternallyprocessedfollow3GPPspecifications,andenablematchingof

theinputsequencedatarateswithoneofthosespecifiedforUMTS.Amoredetailedblockdiagramof

thisunitisgiveninFigure3-20.

3.2.1.2 TrCHMultiplex

Functionalities:thefunctionofthisblockistomultiplexdatafromseveralTrCHs.

3.2.1.3 PhyChFormation

Functionalities:thisblockcreatesthephysicalchannelsaccordingto3GPPspecifications.The

operationsincludedwithinthisblockare:

Datablockmanagement,specifically ,segmentationoftheinputdataintoblockswiththeappropriatesize.

Secondlevelofinterleaving.


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Radioframesegmentation

Channelcoding

Ratematching

TrBkconcatenation/

Codeblocksegmentation

CRCattachment

Radioframe equalisation

1st

interleaving

Figure3-20:BlockDiagramofTrCHModule.

3.2.1.4 Spreading/Scrambling

Functionalities:theoperationsperformedwithinthisblockare:

MultiplicationofthecomplexalgebraicsequencesfromthePhyChFormationblockwitha

Walsh-HadamardcodeoflengthQ( 161 Q )andbaudrate3.84Mchip/s.Thisoperation

providesaspreadingfactorofQ.

Multiplicationofspreadsequencesbyarandomisationcodeatthesamebaudrate.Therandomisationcodesaredefinedin[3GPP25223320].

TheblockdiagramillustratingthesetwooperationsisshowninFigure3-21.

ComplexMultiplier ComplexMultiplier

Channelisation

CodeScramblingCode

Figure3-21:BlockDivisionofSpreading/ScramblingUnit.


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3.2.1.5 MidambleInsertion

Functionalities: thisblockmultiplexesthe sequencefromthespreading/scramblingunit,witha

deterministicsequenceknownasmidamblespecifiedby3GPP[RAN25.221].Twodifferenttypesof

midambleshavebeendefined,onewith512chipsisoftype1andanotherwith256chipsisoftype2.

Figure3-22andFigure3-23showhowtheyareinsertedinbursts1and2.Theyareusedtoestimate

multiplechannelimpulseresponseintheUL.IntheDL,whennoTxdiversityschemeisused,thereis

onlyonemidamblecommontoalltheburstsoftheslot.

Datasymbols976chips

Midamble512chips

Datasymbols976chips

GP96CP

2560*Tc

Figure3-22:StructureofBurstType1.

Datasymbols1104chips Midamble256chips

GP96CP

2560*Tc

Datasymbols1104chips

Figure3-23:StructureofBurstType2.

3.2.1.6 Modulation

Functionalities:thepurposeofthisblockis toadequatelyshapethesignalstobetransmittedoverthe

channel.3GPPspecifiesQPSKcarriermodulationwithrootraisecosinepulseformatting(roll -off

factor=0.22).Since3GPPspecifiescoherentdemodulation,thesimulati onsarecarriedusingthe

basebandcomplexenvelopesoftherealbandpasssignals.Consequentlynoblockinvolvingspecific

QPSKcarriermodulationisneeded.TheModulationblockhasonlytoprovidetheRRCshapetothe4-aryunitaryamplitudecomplexsamplesprovidedbytheblockMidambleInsertionblock.

3.2.2 Receiver

Figure3-24showstheblockdiagramofthereceiver.Thesub -modulesthatcomposethereceiverare

thefollowings:

Pulseshaping:squarerootraisedcosinefilteridenticaltotheoneusedbyFDDmode.

Channelestimation:eachuserschannelimpulseresponseh k=(h k[0],,h k[W-1])isestimatedwiththeaprioriknowledgeofthetransmittedmidamble.Thealgorithmexploitsthe

midambleconstructionmethodandisthereforespecifictotheTDDmode.

Rakereceiver:dependingonthechannelestimationstrategy,theRakereceiverfortheTDDmodecanhavethesamestructureastheoneusedforFDD.Ifthechannelestimation

algorithmestimatesthetap -delaylinemultipathmodel ,theRakereceiverhasthesame

structureasforFDD.Ontheotherhand,ifthechannelestimationalgorithmestimatesaTc/2

receivedchannel,therakereceiverwillhaveaFIRstructure.Asanoption,Multi -user

detectionalgorithmcanreplaceorbeaddedaftertheRakereceiver.AclassicalMUDreceiver

isthejointdetection,whichisablockmulti-userequalizer.

RxPhyCh:ThisblockperformstheinverseoftheoperationsdonebytheblockPhyChFormation,i.e.deinterleavingandunsegmentation.

TrCHDemultiplexing:ThisblockisthedualoftheTrCHcodingblock.Itperformschannel

decoding,deinterleavingandblockmanagementoperations.

TrCHdecoding:ThisblockisthedualoftheTrCHcodingblock.Itperformschanneldecoding,deinterleavingandblockmanagementoperations.


35/63


Pulseshaping

Channel

estimation:

hk

Rake RxPhyChTrCH

Demux

TrCH

DecodingPulseshaping

Channel

estimation:

hk

Rake RxPhyChTrCH

Demux

TrCH

Decoding

Figure3-24:ModuleidentificationofRx

3.2.2.1 Channelestimation

Letebeingthevectorcorrespondingtotheusefulpartofthereceivedmidamble,andhthevectorof

concatenatedchannelimpulseresponseoftheKuser:

])1[].......0[],1[],...,1[],0[],1[],...,1[],0[( 12111000 = WhhWhhhWhhhh K

The2vectorsarelinkedwiththemidamblesmatrixG,accordingtothefollowinglinearsystem:nGhe +=

ThematrixGisformedwiththecyclicshiftofalengthPsequences[0],,S[P-1]:

=

]1[]0[...]3[]2[

]2[]1[]3[

...

...

]2[]1[][]1[

]1[]1[][

]0[]1[..]3[]2[]1[

PssPsPs

PsPsPs

sPsoss

sPsos

ssPsPsPs

G

Toperformlowcostchannelestimation,weusedtheeigenvaluedecompositionofpropertiesof

circulantmatrix:theeigenvectorofGarethecolumnoftheFFTmatrixW.

WeWh

WWG

WWG

11

111

1

=

=

=

isthediagonalmatrixcontain ingtheeigenvaluesofG,andiscomputedaccordingtothefollowing

formula:

))(( 00 gDFTdiagQg ==

whereg0isthefirstcolumnofG.

3.3 BasebandArchitectureforHSDPA/FDD

AgeneraldescriptionofthelinklevelforHSDPA/FDDwillbepresentedhere,andfu nctionalityof

theconstituentblockswillbedescribed.

High-speeddownlinkpacketaccesshasbeenaddedtothe3GPPUMTSstandardsinordertoincrease

thedatathroughput,reducethedelayandtoachievehighpeakdatarates.Thereforetechniquessuch

asadaptivemodulationandcoding(AMC),hybridARQandfastschedulinghavebeenaddedtothe

standards.

Thischapterwillfocusonthehigh -speeddownlinkpacketaccess(HSPDA)enhancementsofthe

UMTS/FDDmode.ThereforeonlyHSPDAspecificadditionswil lbedescribed,inordertoavoidoverlappingwithChapter3.1


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3.3.1 HSDPAspecificUplinkChannelcodingandmodulation

HSDPAdoesnotuseadivergentchannelcodingcomparedtoUMTS.Thedifferencesareonly:

CQI(ChannelQualityIndicator)

ACK-NACK(HARQProtocol)

Additionaltimingvalues

Additional16-QAMmodulation

3.3.1.1 CQI-ChannelQualityIndicatordefinition

TheCQIspecificationcanbefoundin3GPPTS25.214inchapter7.1.2and7.2.

TheUEprocedureforreportingchannelqualityindication(CQI)isdefinedinthefollowingsteps:

1) TheUEderivestheCQIvalueasdefinedin3GPPTS25.214chapter7.2.

2) TheUE shalltransmitthe CQIvalueineachsubframethatstartsn 256chipsafterthestartofslotiontheassociateduplinkDPCCHwithisimultaneouslyfulfilling

( )

( ) 03modand0mod768025602565 ==++ ikchipchipichipnCFN ,

whereCFNdenotestheconnectionframenumberfortheassociatedDPCHandnbeing

thesmallestmfulfillingtherequirementdescribedinsubclause7.7in3GPP25.211.

3) TheUEshallrepeatthe transmissionof theCQIvalue derivedin1) overthenext

(N_cqi_transmit 1) consecutive HS-DPCCH subframes intheslotsrespectively

allocatedtotheCQIasdefinedin3GPP25.211.

4) TheUEshallnottransmittheCQIinothersubframesthanthosedescribedin2)and3).

TheUEshallreportthehighesttabulatedCQIvaluesuchthat,forthecurrentradioconditions,thetransportblockerrorprobabilitydoesnotexceed0.1forasingletransmissionwithaTFRC

correspondingtothereported,oralower,CQIv alue.DependingontheUEcategoryasdefinedin

3GPP25.306,eitherTable8,9,10,or11shouldbeused.ForthepurposeofCQIreporting,theUE

shallassumeatotalreceivedHS -PDSCHpowerof ++= CPICHHSPDSCH PP indB,wherethe

measurementpowero ffset issignaledbyhigherlayersandthereferencepoweradjustment isgivenbyTable8,9,10,or11,dependingontheUEcategory.IfS-CPICHisusedasaphasereference

forHS -PDSCHdemodulation, CPICHP isthereceivedpoweroftheS -CPICHusedbytheUE,

otherwise CPICHP isthereceivedpoweroftheP-CPICH.

3.3.1.2 ACK-NACK(HARQProtocol)

TheHARQspecificationcanbefoundin3GPPTS25.214inchapter7.1.1.

IftheUEdidnotdetectcontrolinformationintendedforthisUEonanyoftheHS -SCCHsintheHS-

SCCHsetintheprevioussubframe,theUEshallmonitorallHS -SCCHsintheHS -SCCHset.Ifthe

UEdiddetectcontrolinformationintendedforthisUEintheprev ioussubframe,itissufficientto

onlymonitorthesameHS-SCCHusedintheprevioussubframe.

IfaUEdetectsthatoneofthemonitoredHS-SCCHscarriescontrolinformationintendedforthisUE,

theUEshallstartreceivingtheHS -PDSCHsindicatedbythiscontrolinformation.Afterdecodingthe

HS-PDSCHdata,theUEshalltransmitahybridARQACKorNACKasdeterminedbytheMAC -hs

basedontheCRCcheck.TheUEshallrepeatthetransmissionoftheACK/NACKinformationover

N_acknack_transmitconsecutiveHS-DPCCHsub-frames,intheslotsallocatedtotheHARQ -ACKas

definedinthefollowingchapter.WhenN_acknack_transmitisgreaterthanone,theUEshallnotattempttoreceivenordecodetransportblocksfromtheHS -PDSCHinHS-DSCHsub-framesn+1to

n+(N_acknack_transmit -1)wherenisthenumberofthelastHS -DSCHsub -frameinwhicha


37/63


transportblockhasbeenreceived.IfcontrolinformationisnotdetectedonanyoftheHS -SCCHsin

theHS-SCCHset,neitherACK,norNACK,shallbetransmittedinthecorrespondingsubframe.

FurtherinformationabouttheadditionalMAC_hsisavailableinthe3GPPTS25.321Specification.

3.3.1.3 Additionaltimingvalues

Thesetimingspecificationscanbefoundin3GPPTS25.211inchapter7.7.

Figure3-25showsthetimingoffsetbetweenthe uplinkDPCCH,theHS-PDSCHandtheHS-DPCCH

attheUE .Thecode -multiplexedHS -DPCCH sub-framestarts 256m chipsafterthestartof an

uplinkDPCCHslotwithmselectedsuchtha ttheACK/NACKtransmissionstarts withinthefirst0 -

255chipsafter7.5slotsfollowingtheendofthereceivedHS -PDSCHsub -frame.UEandNodeB

shallonlyupdate m inconnectiontoUTRANreconfigurationofdownlinktiming. Notethatdueto

autonomousadjustmentsofthe DPDCH/DPCCHtransmissiontimeinstant bytheUEdescribedin

3GPP25.214 ,therelationshipsdescribedinthissectionmayceasetobevalid .Moreinformation

abouttheuplinktimingadjustmentscanbefoundin3GPP25.214.

UplinkDPCCH

HS-PDSCHat

UplinkHS-DPCCH

3Tslot7680chips

m256chips

UEP(7.5Tslot=19200chips)0-255chips

Tslot

2560chips

3Tslot7680chips Figure3-25:TimingstructureatUEforHS-DPCCHcontrolsignalling

3.3.2 HSDPAspecificDownlinkChannelcodingandmodulation

ThisChapterdescribestheHSDPAspecificsincontrasttothebasicUMTS algorithms.AfewUMTS

descriptions(e.g.Rake-MMSE)areincludedtodescribepossibleimprovementoptionsforHSDPA.

Inthedownlink,severalphysicalchannelsaremultiplexedsynchronouslytothetransmissionchannel

byusingorthogonalspreadingcodes .Inamultipathchannel,inter -pathinterferencesdestroythe

orthogonalityandcausemultiple-accessinterferences(MAI).Alongscramblingcodeoflength38400

chipsissuperimposedonthespreadingcodesinordertoreducetheimpactofthemulti -pathsandthe

MAI.

Thepartofthereceiverdescribedinthissectionbasicallyhastoperformfivetasks.Thefirsttask

consistsofthetimingsynchronizationwithrespecttothereceivedscramblingcode.Asasecondtask,thefrequencyerrorofthelocalclo ckoscillatorrelativetotheclockoscillatorofthetransmitteris

estimatedandcorrected.ThethirdtaskistosuppresstheMAIofthemultipathchannel.Afirstoption

isasimpleRakecombiner.TheproposedmorepowerfulsecondoptionisaMMSEchip -level

equalizer.InthefourthstepthedataoftheI -andQ -componentsaredetectedbymeansofde -

scramblingandde -spreading.HSDPAdatathatare16 -QAMmodulatedinordertoachievehighest

dataratesarereconstructedbya16-QAMde-mapperinafifthstep.

Figure3-26givesanoverviewofthispartofthereceiverthatisdividedintosynchronization,MAI

suppressionanddemodulation.Amoredetaileddescriptionisgiveninthefollowingsubsections.


38/63


Slotsync.

Framesync.

Scr.Codeidentify

Metricgenerationphaseerrorest.

CellSearch

Channelest.&

rakecombining

1.Option

MMSEchiplevelequalizer

2.OptionDescramble Despread

16QAMDe-Mapp

CPICHdespread

Synchronisation MAIcanceler Demodulation

Figure3-26:SynchronizationandDemodulation

3.3.2.1 Synchronization

ThispartinHSDPAisidenticaltoUMTSsynchronization.Thusnoadditionshavetobereported

here.

3.3.2.2 MAIsuppression

For3GPPoneimportantdistinctionfro mpreviousstandardsistherequirementofhighandvariable

datarate.Itispossibletoincreasethedataratewithoutbandwidthexpansionbyreducingthe

spreadingfactor.Alternatively,thespreadingfactormayremainfixedandallocatingseveralparal lel

spreadingcodesforthesameserviceincreasesthedatarate.Thestandardsupportsbothtechniques.

ThephysicallayerhasbeendefinedinsuchawaythataconventionalRAKEreceiver,formingthe

simplestmulti -pathdiversityreceiverthatcanbeuse d,wouldgivesufficientperformanceinmostcases.

Therefore,asafirstoptionaRakecombinercanbeused.Thisreceivertypesuffersfrommulti -user

interferencecausedbyotherchannels.Thus,aRAKEcombinerwouldrequireverypowerfulchannel

codingtoguaranteesufficientlowBERs.Advancedreceiveralgorithmscapableofsuppressingor

cancellinginterferencescansignificantlyimprovesystemcapacitywithlesschannelcodingneeded.

Thetargetrequirementof10Mbit/scouldbefulfilledwithaRake byalargeamountofpuncturing.In

ordertobeabletohandlethischallengingrequirementinamorehostileenvironment,anMMSEchip

levelequalizercanreplacetheRakecombinerinthemorepowerfuloption.

Rakecombiner

TheRakecombinercontainsach annelestimatorthatconsistsoftwoparts.The4strongestdelaysaredeterminedbyafullsearchwithrespecttotheCPICH.Thosepathsoutofthefourstrongestonesthat

exceedacertainthreshold(20%ofthepowerinthestrongestpath)aretrackedin separatefingersin

thesecondpart.Thetrackinginadistinctfingerisperformedusinganearlylateloopwithatiming

resolutionof8samplesperchip.Eachfingerisabletoestimatedopplershiftsofupto800Hz.Afast

estimationandcorrectionofthephaseerrorscausedbythedopplershiftsallowcorrelatingover4bits

ontheCPICHcorrespondingto1024chips.Theestimatesoftherespectivecoefficientsofthechannel

impulseresponse,buildfromtheactivefingers,aremaximumratiocombined.

MMSEchiplevelequalizer

ThepurposeoftheMMSEequalizeristoapproximatethesuperposedmulti -usersynchronoussignal

attheoutputofthedownlinktransmitterbymeansofalinearoperation.Theapproximationisdonebyminimizingthemeansquarede rrorbetweenthemulti -usersynchronoussignalandtheestimateat

theoutputoftheequalizer.Thisminimizationproblemcanbeformulatedasfollows:


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40/63


Subframe

Buffer

Symbolstosoft

values(LLR)Calculations

POWER

EST.

Const.re-

arrangement

De-

Interleaving

Physicalchannelde-Segmentation

Postdeinter-

leavingbuf.

2ndRatede

Matching

1stRatede-

Matching

Channel

Decoding

CRCcheck

LLR

HARQ

LLR

combining

HARQ

Buffers

HARQ

memory

manager

BlockReorderinginSW(MAC)

Figure3-27:ChannelDecodingchainsHSDPA/HS-DSCH

3.3.3.1 HSDPA(HS-DSCH)

TheHSDSCHconsistsofthefollowingblocks

Subframebuffer(16-QAMonly)

ThisbufferstoresthepartofthesubframeofHS -DSCH.Thebufferingisneededinordertoperformthepowerestimationforthe16 -QAMLLRcalculations.Thesizeofthebuffer

dependsonthereliabilityofestimates.

PowerEstimation(16-QAMonly)Usedtofindthedecisionvaluestobeusedin16-QAMLLRcalculations.Inawayitprovides

thebiasformappingfromsymbolstobits.

LLRCalculationsSymbolsaremappedtobitsbasedontheoutputsfromthepowerestimationblock.

ConstellationRearrangementSpecificationreference:TS25.212subclause4.5.7.

Itchangesthemappingfrombitstoconstellationpointstoachievebetterperformanceduringretransmissions.

DeInterleaving


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Specificationreference25.212subclause4.5.6.

ForQPSKtheInterleavingisperformedinthesamewayasinRel99.For16 -QAM2

Interleaversareused.

PhysicalchannelDeSegmentationSpecificationReference:25.212Subclause4.5.5Thebitsfromphysicalchanne lsareputtogether(concatenated)toformasingleHS -DSCH

block.

PostDeInterleavingBufferThenecessityofthisbufferdependsontheconstraintsindoinginverseHARQ.Itisneeded

forthebitseparation.

BitSeparationSpecificationreference25.212 Subclause4.5.5.Theincomingbitstreamisdividedintothree

streams,thesystematicbits,thefirstparityandthesecondparity.Itstheinverseofthe

transmitterBitcollectionfunction.

2ndRateDematchingSpecificationreference25.212Subclause4.5.4.3.

TheSecondRatedematchingmatchestheincomingbitstreamtoreciever'ssoftbuffering

capacity.ThesecondRateMatchingalsomakesdifferentredundancyversionsfor

Incrementalredundancy.

LLRcombiningSpecificationreference:NA.

TheLLRcombi ningcombinesdifferent(re)transmissionsofHSDSCHblockstoformone

softbitvalueforuseinturbodecoder.ForthefirsttransmissiontheHARQbufferneedstobe

nulledoutormadetransparent.

HARQbuffersSpecificationreference:NA.

HARQbuffersaredividedintoasetof8sub -buffers(tobeinvestigated)oneforeachHARQ

processthatisactive.Theactualsizeofthesebuffersissignalledbyhigherlayers.

1stRateDe-matchingSpecificationreference25.212Subclause4.5.4.2

Worksinthesamewas astheRateMatchinginRel99withTTI

IR

TTI

ilNNN = where

IRN istheUE'ssoftbufferingcapacity.Thisblockbasicallyrearrangesthesoftbitsintotheir

respectivecorrectpositionsbeforesending.

ChannelDecoderSpecificationreference25.212Subclause4.5.3

ThisblockconsistsofthecodeblocksegmentationandTurbodecoder.AHSDSCHblockcan

containupto4codeblockseachof(5114+tail)bits,whichareseparatelydecodedbythe

turbodecoder.

CRCdecoderSpecificationreference25.212Subclause4.5.1

24bitCRCisperformedtochecktheintegrityofthereceivedHSDSCHblock.Itsthesame

blockasusedinRel99.

3.3.3.2 HS-SCCHDecoding

TheHS -SCCHcarriesthecontrolsignalingfortheHS -DSCHandhastobedecodedbeforet he

HS.DSCHcanbedecoded.TheHS-SCCHcarriesthefollowinginformation

Thechanalizationcodeset ...., 2,1, CCSCCS XX (7bits)


42/63


ModulationschemeInformation msX (1bit)

HybridARQprocessinformation(3bits)

Redundancyandconstellationversion(3bits)

Newdataindicator(1bit)

UEidentity(16bits).TheUEidisnotexplicitlytransmittedonHS -SCCH,butitsusedinthecalculationofNE-specificmaskandCRC.

depuncture2

Viterbidecode2

Mask

depuncture1

Viterbidecode1

depuncture2

Viterbi

decode2

Mask

CRCdecode

if(CRC)DecodeAllHS-SCCH'SintheUE'Sdomain

DeMuxDeMux

MAC-hs

false

true

Xue

Xue

DeMUX

Slot1 Slot2,3

DeMux

DecodethisHS-

SCCHinNextslot

DE-

CodeEnXcss Xms Xnd Xhap

XtbsXrv

r s v

Figure3-28:HS-SCCHDecoding

ThedecodingprocessinvolvesthestepsasexplainedinTS25.211chapter4.6.44.6.7.Thetiming

specificationcanbefoundin3GPPTS25.211chapter7.7.

3.3.3.3 HS-SCCH/HS-PDSCHtiming

Figure3-29showstherelativetimingbetweentheHS -SCCHandtheassociatedHS -PDSCHforone

HS-DSCHsub-frame.TheHS-PDSCHstartsHS-PDSCH=2Tslot=5120chipsafterthestartoftheHS -SCCH.


43/63


HS-SCCH

HS-PDSCH

3Tslot7680chips

HS-PDSCH(2Tslot5120chips)

3Tslot7680chips

HS-DSCHsub-frame

Figure3-29:TimingrelationbetweentheHS-SCCHandtheassociatedHS-PDSCH


44/63


4 Multi-ModeSystemArchitecture

Ageneralhigh-leveldescriptionofthemulti -modesystemarchitecturewillbepresentedhere.Itwill

beinaformofm atrix-likeblockdiagram,withrowsrepresentativeofdifferentmodes,andcolumnscontainingafunctionalgroupacrossmodes.Amatrix -likeblockdiagramis providedforeach

sublayer inthe UplinkTxandDownlinkRx.Possiblere -configurabilityineachc olumnwillbe

discussedintheaspect ofwhethertheconstitutingfunctionsareidenticalortheyneedfurther

inspectionforidentifyingtheirre -configurabilitylevel(SWre -configurable,HWre-configurable,and

non-re-configurable).

4.1 FunctionalityMatrixforUplinkTransmitter

4.1.1 SampleProcessing

ThefunctionalblocksoftheUplinkTransmitter SampleProcessingarevirtualfunctionalidentical

forallmodes.

" # % ' )

1 2 3% 5 7

8

7 9

)

8

)

1 @

1 ) 7 C % 9

8

)

FDD

TDD

HSDPA-

FDD

" # % '

)

1 2 D 3

% 5 7

8

7 9)

8

)

1 @

1 )

7 C % 9

8

)

" # % ' )

1 2 D 3% 5 7

8

7 9

)

8

)

1 @

1 ) 7 C % 9

8

)

Figure4-1:BlockMatrixUplinkTransmitterSampleProcessing

4.1.2 ChipProcessing

ThetransmitterChipProcessingtopleveldescriptionshownin Figure4-2issimilarforbothFDD

andTDD.Onlyoneblock,theMidambleInsertionisuniquetoTDD.


45/63


G H P Q

R Q T Q U V X H U

Y ` U Q V P Q U

V T P

a

H P b c V X H U

G H P Q

R Q T Q U V X H U

Y ` U Q V P Q U

V T P

a

H P b c V X H U

G H P Q

R Q T Q U V X H U

Y ` U Q V P Q U

V T P

aH P b c V X H U

a f

P V g h c Q

p

T q Q U X

f

H T

FDD

TDD

HSDPA-

FDD

Figure4-2:BlockMatrixUplinkTransmitterChipProcessing

AnotherdifferencebetweentheFDDandTDDmodeisthegenerationofscramblingcodeandthe

midambleforTDDasopposedtoDCPCHpilotbitsforFDD.

4.1.3 TransportChannelProcessing

Thefunctionality

Documents

d31 Unis Dr Re 009 Final