Upload
alvin-edwards
View
217
Download
0
Embed Size (px)
Citation preview
2
Instructions Instructions are the language of the machine
We’ll be work with the MIPS instruction set architecture
Design goals find a language that make it easy to build the hardware and the
compiler maximizing performance and minimizing cost
Stored-program concept programs (= instructions and data) can be stored in memory as
numbers
Fetch & execute cycles Fetch the instruction from memory and put it into a special register (IR) The bits in the register “control” the subsequent actions required to
execute the task specified by the instructioncontinuewith “next” instruction
3
Instruction set characteristic
Small Few primitive instructions
Simple Few instruction formats
Regular Instructions can be handled in similar ways
Complete support all kind of high level language instructions
Efficient High level language instructions can be mapped efficiently
Compatible
4
Definition of the architecture
Data types- bit, byte, word, unsigned integer, char, …
Operations- arithmetic, logical, shift, flow control, data transfers, …
# of operands (3, 2, 1, or 0 operands)- number of operands affect the instruction length
Registers
Memory organization
5
MIPS arithmetic
all arithmetic instructions have 3 operands operands order is fixed (destination first)
Design principle: Simplicity favors regularity. Why ?
of course this complicate some things …
C code MIPS codec = a+b add $s0, $s1, $s2
C code MIPS code
f = (g + h) – (i + j) add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1
6
Registers vs. memory
Arithmetic operands must be registers,
- only 32 registers provided
- each register is 32 bits (word)
Design Principle: Smaller is faster. Why ?
Compiler associates variables with registers, but … What about programs with lots of variable or complex data
structures ?
Only a small amount of data can be kept in the computer’s registers, the rest is kept in memory
We’ll need instructions that transfer data between memory and registers
Absolute truth ?
Processor I/O
Control
Datapath
Memory
Input
Output
7
Memory organization
Viewed as a large, single-dimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory
0
1
2
3
4
5
6...
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8
Memory organization
Bytes are nice, but most data items use larger "words" For MIPS, a memory word is 32 bits wide (= 4 bytes)
232 bytes with byte addresses from 0 to 232 - 1 230 words with byte addresses 0, 4, 8, ... 230 – 4 Words are aligned (alignment restriction)
words start at addresses that are multiple of 4 what are the least 2 significant bits of a word address?
9
Bytes order within a word
Which byte is first and which is last ?
There are two choices Least significant byte is the at rightmost end (= little end) Least significant byte is the at leftmost end (= big end)
MIPS uses Big Endian
3 2 1 0
7 6 5 4
0 1 2 3
4 5 6 7
04
04
Big Endian
Little Endian
10
MIPS data transfer instructions
load (it copies data from memory to a register) store (copies data from a register to memory)
Memory address for load and store has two parts A register whose contents is known (called base register or
index register) An offset to be added to the base register content
This way the address is 32 bits
The offset can be positive or negative (2’s complement)
C code MIPS code Meaning
A[12] = h + A[8]
lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 48($s3)
$t0 = Memory[$s3 + 32]
$t0 = $s2 + $t0
Memory[$s3 + 48] = $t0
11
Machine language
MIPS assembly instructions are translated into machine instructions (“binary numbers”)
Instructions, like registers and words of data, are also 32 bits long Example: add $t1, $s1, $s2 registers are represented as numbers:
$t1=9, $s1=17, $s2=18, …
The format above is called R-format (for register) Can you guess what the field names stand for?
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
12
Machine language
Consider the load-word and store-word instructions We must specify two registers and a constant (=immediate operand) Regularity principle would suggest to use for the constant one of the
5-bit fields
Problem: the constant would be limited to only 32 !!!)
Solution: we introduce a new format called I-type (for immediate) The 16 bit number is in 2’s complement form
Design principle: good design demands good compromises
6 bits 5 bits 5 bits 16 bits
13
Examples
$t0(rt)
$s3(rs)
sw(op)
(op)lw
(rs)$s2
(rt)$t0
14
MIPS logical operations
The above instructions are all R-type
Logical operation Example Meaning
shift left logical sll $s1, $s2, 10 $s1 = $s2 << 10
shift right logical srl $s1, $s2, 10 $s1 = $s2 >> 10
bit-by-bit and and $s1, $s2, $s3 $s1 = $s2 & $s3
bit-by-bit or or $s1, $s2, $s3 $s1 = $s2 | $s3
bit-by-bit nor nor $s1, $s2, $s3 $s1 = ~ ($s2 | $s3)
15
Example
sll $s1, $s2, 10
srl $s1, $s3, 10
0 0 18 17 10 0op rt rd shamt func
0 0 19 17 10 2op rt rd shamt func
16
Control flow
Decision making instructions alter the program control flow, i.e., change the "next" instruction to be executed
MIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, Label
C code MIPS code
if (i==j) h=i+j;
bne $s3, $s4, Label
add $s5, $s3, $s4
Label: …
17
Control flow
MIPS unconditional branch instruction (jump) j Label
Can you build a simple for loop?
C code MIPS code
if (i==j) f=g+h; else f=g-h
bne $t0, $t1, Else
add $s5, $s3, $s4
j Exit
Else: sub $s5, $s3, $s4
Exit: …
18
Control flow
We have: beq (test for equality) and bne (test for inequality) But, sometime is useful to see if a variable is less than
another one (branch-less-than)
MIPS provides the instruction set-on-less-than (slt) The format is R-type
Meaning MIPS code
if (s1<s2) t0=1; else t0=0 slt $t0, $s1, $s2
19
Control flow
Case switch statement can be implemented as a chain of if-then-else
statements or more efficiently as a table of addresses
MIPS provides a jump register instruction (jr) It is an unconditional jump to the address specified in
a register
Example: jr $s0
20
Control flow – Instruction formats
slt and jr are R-format
0 18 19 17 0 42op rs rt rd shamt func
slt $s1, $s2, $s3
0 17 0 0 0 8op rs func
jr $s1
21
Control flow – Instruction formats
beq and bne are I-format instructions
The 16-bit number is in 2’s complement form
The 16-bit number specifies the # of instructions to be skipped
Most branches are local [Principle of locality]
Next memory address = PC + (16-bit number x 4)
4 17 18 25op rs rt 16-bit number
beq $s1, $s2, 100
22
Control flow – Instruction formats
The unconditional jump instruction requires a new instruction format (J-format)
Example: j 10000
The address of the next instruction is obtained by concatenating the 4 upper bits of the PC with the 26-bit address shifted left 2 bits
Next memory address = {PC[31:28], INS[25:0], 2’b00} Address boundaries of 256 MB = (228)
2 2500op 26-bit number
23
MIPS Registers convention
Name Register number Usage$zero 0 the constant value 0$v0-$v1 2-3 values for results and expression evaluation$a0-$a3 4-7 arguments$t0-$t7 8-15 temporaries$s0-$s7 16-23 saved$t8-$t9 24-25 more temporaries$gp 28 global pointer$sp 29 stack pointer$fp 30 frame pointer$ra 31 return address
Register 1 ($at) reserved for assembler, 26-27 ($k0-$k1) for operating system
24
Constants
Small constant operands occur quite frequently in programs (50% of operands)
By including constants inside instructions, execution become much faster than if constants were loaded from memory
Design Principle: make the common case fast
w/o immediate instruction with immediate instruction
lw $t0, AddrConstant4($s1)
add $s3, $s3, $t0
addi $s3,$s3,4
25
Constants
Why doesn’t MIPS have a subtract immediate operation ? Constants are frequently short and fit into the 16-bit field But, what if they are bigger ? It would be convenient to have a 32-bit constant or address !!!!
Category Instruction Example Meaning
Arithmetic add immediate addi $s1, $s2, 100 $s1 = $s2 + 100
Logicaland immediate andi $s1, $s2,100 $s1 = $s2 & 100
or immediate ori $s1, $s2, 100 $s1 = $s2 | 100
Conditional
branchset less than immediate
slti $s1, $s2, 100If ($s2<100) $s1=1 else $s1=0
26
How about large constants ? The compiler or the assembler must break large constants into
pieces and then reassemble them into registers We'd like to be able to load a 32 bit constant into a register Must use two instructions, new "load upper immediate" instruction
Then must get the lower order bits right, i.e.,
ori $t0, $t0, 1010101010101010
1010101010101010 0000000000000000
filled with zeros
1010101010101010 0000000000000000
1010101010101010
1010101010101010 1010101010101010
ori
lui $t0, 1010101010101010
27
Assembly Language vs. Machine Language
Assembly provides convenient symbolic representation much easier than writing down numbers e.g., destination first
Machine language is the underlying reality e.g., destination is no longer first
Assembly can provide 'pseudoinstructions' e.g., “move $t0, $t1” exists only in assembly would be implemented using “add $t0,$t1,$zero”
When considering performance you should count real instructions
28
Translating and starting a program
29
Overview of MIPS
simple instructions all 32 bits wide
very structured
only three instruction formats
rely on compiler to achieve performance
op rs rt rd shamt funct
op 26 bit number
R
I
J
op rs rt 16 bit number
30
Summary – MIPS operands
MIPS operands
Name Example Comments$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform
32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero alw ays equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants.
Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so
230 memory Memory[4], ..., sequential w ords differ by 4. Memory holds data structures, such as arrays,
words Memory[4294967292] and spilled registers, such as those saved on procedure calls.
31
Summary – MIPS instructionsMIPS assembly language
Category Instruction Example Meaning Commentsadd add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers
Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers
add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constants
load word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to register
store word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory
Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to register
store byte sb $s1, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memory
load upper immediate lui $s1, 100 $s1 = 100 * 216 Loads constant in upper 16 bits
branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC + 4 + 100
Equal test; PC-relative branch
Conditional
branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to PC + 4 + 100
Not equal test; PC-relative
branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0
Compare less than; for beq, bne
set less than immediate
slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else $s1 = 0
Compare less than constant
jump j 2500 go to 10000 Jump to target address
Uncondi- jump register jr $ra go to $ra For switch, procedure return
tional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call
32
Addressing modes in MIPS
Register addressing (e.g., add, sll, nor, slt, …) the operand is a register
Immediate addressing (e.g., addi, ori, …) the operand is a constant within the instruction
Base addressing (e.g. lw, sw) [register+offset] The operand is at the memory location whose address is
the sum of a register and a constant in the instruction
PC-relative addressing (e.g., bne, beq) [PC + offset] The address is the sum of the PC and a constant in the
instruction
Pseudo-direct addressing (e.g., j) [PC concatenation] The address is the concatenation of a value in the
instruction with the upper bits of the PC
33
Addressing modes in MIPS
Byte Halfword Word
Registers
Memory
Memory
Word
Memory
Word
Register
Register
1. Immediate addressing
2. Register addressing
3. Base addressing
4. PC-relative addressing
5. Pseudodirect addressing
op rs rt
op rs rt
op rs rt
op
op
rs rt
Address
Address
Address
rd . . . funct
Immediate
PC
PC
+
+
34
Alternative architectures
Design alternative:
provide more powerful operations
goal is to reduce number of instructions executed
danger is a slower cycle time and/or a higher CPI
RISC vs. CISC
virtually all instruction sets since 1982 are RISC
common architectures: 80x86, IA-32, PowerPC, …
35
“Spilling” registers
Many programs have more variables than computers have registers
The compiler tries to keep the most frequently used variables in registers and places the rest in memory
The process of putting less commonly used variables (or those needed later) into memory is called spilling registers
36
Supporting procedures
Goal: structure programs so that it is easier to understand and reuse code
Execution of a procedure1. place parameters in a place where the procedure can access them2. transfer control to the procedure3. acquire the storage resources needed for the procedure4. Place the result value in a place where the calling program can access it5. Return control to the point of origin
Basic MIPS facilities $a0-$a3 4 argument registers in which to pass parameters $v0-$v1 2 value registers in which to return values $ra return address register to return to the point of origin
jal ProcedureAddress jump-and-link (it saves PC+4 in $ra) jr $ra jump register
37
What if we need more registers ?
A compiler may need more registers for a procedure than the four argument and two return value registers
The local variables we need may not even fit in the MIPS registers
also any register needed by the caller must be restored to the values they contained before the procedure was invoked we need to spill the registers to memory
The ideal data structure for spilling registers is a stack (last in first out)
push – place data on the stack pop – remove data from the stack
38
The stack
MIPS allocate a register just for the stack: the stack pointer ($sp) it points to the most recently allocated address in the stack
Stacks grow from higher addresses to lower addresses push values on the stack by subtracting from the $sp pop values from the stack by adding to the $sp
39
Example – compiling a leaf procedure
int leaf_example (int g, int h, int i, int j)
{
int f;
f = (g+h) – (i+j);
return f;
}…
leaf_example
main
…
…
jal leaf_example
…
Memory
40
Example – compiling a leaf procedure
leaf_example:
addi $sp,$sp,-12 # adjust stack to make room for 3 items
sw $t1, 8($sp) # save $t1 for later us by the caller sw $t0, 4($sp) # save $t0 for later us by the caller sw $s0, 0($sp) # save $s0 for later us by the caller
add $t0,$a0,$a1 # t0 = g+h
add $t1,$a2,$a3 # t1 = i+j
sub $s0,$t0,$t1 # s0 = t0–t1 = (g+h)-(i+j)
add $v0,$s0,$zer0 # v0 = s0+0 (return f)
lw $s0, 0($sp) # restore $s0 for caller
lw $t0, 4($sp) # restore $t0 for caller
lw $t1, 8($sp) # restore $t1 for caller
addi $sp,$sp,12 # adjust stack to delete 3 items
jr $ra # jump back to calling routine
41
Reduce register spilling
To avoid saving and restoring a register whose value is never used, MIPS separate temporary registers from saved registers:
$t0-$t9: are not preserved by the callee (called procedure)
$s0-$s7: must be preserved on a procedure call (if used, the callee saves and restore them)
Thus, the assembly code generated for leaf_example by a compiler can be more compact !!!
Can you guess how the code should look like ?
When a compiler finds a leaf procedure it exhaust all temporary registers before using registers it must save
42
Concluding Remarks
Instruction complexity is only one variable lower instruction count vs. higher CPI / lower clock
rate
Design Principles: simplicity favors regularity smaller is faster good design demands compromise make the common case fast
Instruction set architecture a very important abstraction !
43
Common misconceptions and mistakes
More powerful instructions mean higher performance
Write in assembly language give the highest performance
Forgetting that sequential word addresses in machines with byte addressing do not differ by one
Using a pointer to an automatic variable outside its defining procedure