Chap8 Lecture

Differential Amplifiers (Chapter 8 in Horenstein) Differential amplifiers are pervasive in analog electronics Low frequency amplifiers High frequency amplifiers Operational amplifiers the first stage is a differential amplifier Analog modulators Logic gates Large input resistance High gain Differential input Good bias stability Excellent device parameter tracking in IC implementation

Advantages

Examples Bipolar 741 op-amp (mature, well-practiced, cheap) CMOS or BiCMOS op-amp designs (more recent, popular)R. W. Knepper SC412, slide 8-1

Amplifier With Bias Stabilizing Neg Feedback Resistor Single transistor common-emitter or common-source amplifiers often use a bias stabilizing resistor in the common node leg (to ground) as shown below Such a resistor provides negative feedback to stabilize dc bias But, the negative feedback also reduces gain accordingly

We can shunt the common node bias resistor with a capacitor to reduce the negative impact on gain Has no effect on gain reduction at low frequencies, however Large bypass capacitors are difficult to implement in IC design due to large area

Conclusion: try to avoid using feedback resistor R2 in biasing network

R. W. Knepper SC412, slide 8-2

Differential Amplifier Topology In contrast to the single device commonemitter (common-source) amplifier with negative feedback bias resistor of the previous slide, the differential ckt shown at left provides a better bypass scheme. Device 2 provides bypass for active device 1 Bias provided by dc current source Device 2 can also be used for input, allowing a differential input Load devices might be resistors or they might be current sources (current mirrors)

The basic differential amplifier topology can be used for bipolar diff amp design or for CMOS diff amp design, or for other active devices, such as JFETs


Differential Amplifier with Two Simultaneous Inputs The differential amplifier topology shown at the left contains two inputs, two active devices, and two loads, along with a dc current source We will define the differential mode of the input vi,dm = v1 v2 common mode of the input as vi,cm= (v1+v2)

Using these definitions, the inputs v1 and v2 can be written as linear combinations of the differential and common modes v1 = vi,cm + vi,dm v2 = vi,cm vi,dm

These definitions can also be applied to the output voltages Differential mode vo,dm = vo1 vo2 Common mode vo,cm = (vo1 + vo2)

Alternately, these can be written as vo1 = vo,cm + vo,dm vo2 = vo,cm vo,dmR. W. Knepper SC412, slide 8-4

Bipolar Transistor Differential Amplifier Q1 & Q2 are matched (identical) NPN transistors Rc is the load resistor Placed on both sides for symmetry, but could be used to obtain differential outputs

Io is the bias current Usually built out of NPN transistor and current mirror network rn is the equivalent Norton output resistance of the current source transistor

Input signal is switching around ground Vref = 0 for this particular design Both sides are DC-biased at ground on the base of Q1 and Q2

vBE is the forward base-emitter voltage across the junctions of the active devices Since Q1 and Q2 are assumed matched, Io splits evenly to both sides IC1 = IC2 = Io/2R. W. Knepper SC412, slide 8-5

NPN Bipolar Transistor Physical StructureDual-Polysilicon Bipolar Transistor Features: Two polysilicon layers P+ for extrinsic base, N+ for emitter Self-aligned with emitter window opening

Trench Isolation Oxide lined, polysilicon filled

Shallow Trench Isolation (STI) Isolate base/emitter active region from collector reach-thru

Yaun Taur, Tak Ning Modern VLSI Devicees

N-type Pedestal Implant for high fT device Self-aligned with emitter opening Limits base push-out (Kirk Effect)

Highly doped extrinsic base lower Rb Emitter (arsenic) diffused from N+ poly SiGe Heterojunction BJT: Typically 10-15% mole fraction of Ge graded into intrinsic base region (as shown), bandgap is narrowed in base, adding drift component to electron velocity


Bipolar Transistor Operation (1D Device)BJT operation: An external voltage (0.75-0.85 V) is applied to forward-bias the emitter-base junction Electrons are injected from the emitter into the base comprising the majority of the emitter current Holes are injected from the base into the emitter, as well, but their numbers are much smaller, since ND,e >> NA,b


Since XB = 50 Common-mode, single-ended gain < = 0.2

Completed design is shown above In class Exercise: 8.4, 8.5, & 8.6R. W. Knepper SC412, slide 8-26

BJT Diff Amp with BJT Current Source The expression for common-mode gain on slide 8-20 (-RC/2rn) shows that in order to reduce Acm, we want to make the effective impedance of the current source very high Using a resistor to generate the current source limits our design options in making rn (RE in this case) high

An alternate method of generating Io is to use an NPN transistor current source similar to that shown at the left Q3 is an NPN biased in the forward active region so that rn (given by the inverse slope of the collector characteristics) is very high RA and RB form a voltage divider establishing VB = VEE x RA/(RA + RB) where VEE is VT, Vgs VT > Vds

Ids = FN Vds (Vgs VT Vds/2) interface is inverted and not pinched off at drain (Fig. a) Pinch-off Point: Vgs > VT, Vds = Vdsat channel pinches off at the drain junction simple theory: Vdsat = Vgs VT (Fig. b) Saturated Region: Vgs > VT, Vgs VT < Vds

Ids = FN (Vgs VT)2 interface is inverted and pinched off at drain further increase in Vds occurs across pinchoff depletion region (Fig. c) FN = QNCox (W/L)N where QN is the mobility of electrons in the channel, Cox is the gate capacitance per unit area, W is the device width and L is the device effective channel lengthR. W. Knepper SC412, page 8-36

MOSFET DC Characteristics: linear vs saturation If the linear Ids expression from the previous chart is plotted with increasing Vds, one observes a maximum at Vds = Vgs Vt after the current reduces in a parabolic fashion. In fact, the charge in the channel Qn(y) goes to zero at Vds = Vgs Vt

The voltage Vds = Vgs Vt = Vdssat is the pinch-off voltage where the channel pinches off at the drain junction.Further increase in Vds simply increases the voltage between the drain and the channel pinchoff point, and does not increase the voltage V(y) along the channel.

Therefore, IDS remains constant for further increases in Vds and we say the device is in the saturation region (or active region) withIDS = Qn Cox (W/L) (Vgs Vt)2

The transconductance in saturation can be found by differentiating the expression for IDS with Vgs, giving gm = QnCox (W/L) (Vgs Vt) = [2 QnCox (W/L) IDS]


IDS versus VDS for A Real DeviceChannel length modulation: As VDS increases, in fact, there is some non-zero slope on the IDS vs VDS characteristic The increase in IDS with VDS is caused by a shortening of the effective channel length Leff with increasing VDS due to an increase in the depletion region thickness from the channel tip to the drain junction Substituting for L, from the expression for the thickness of an abrupt junction (with a square root dependence on reverse biased voltage), one can obtain a modified expression for the current IDS in saturation (active region) as shown below.

From this new expression one can derive an expression for the output drain-source resistance of the NMOS transistor in the saturation region as rds = 1/(dIDS/dVDS) = 1/(PIDS) where P is defined below and kds = [2ISIIo/qNA]


MOSFET Capacitance Model The MOSFET capacitances (gate-tosource, gate-to-drain, gate-to-substrate, source-to-substrate, and drain-tosubstrate) are illustrated in the drawing at left and summarized in the table below Cov is an overlap capacitance due primarily to lateral diffusion of the source and drain junctions, but also includes fringing capacitance Cov =~ 2/3 Cox W xj where xj is the junction depth

The gate-to-channel capacitance is evenly divided between source and drain in the linear (triode) region, but is effectively connected only to the source at pinchoff Integration of the channel charge shows that only 2/3 of Cgc becomes part of Cgs in the saturation (active) region A similar reasoning is used to partition Ccx (CCB in picture) between Csx and Cdx


Cgx (gate-to-substrate) is zero when Vgs > Vt, but increases to CoxW(L - 2(L) in the accumulation region.

MOSFET High Frequency Figures of MeritUnity gain bandwidth product fT (frequency where current gain falls to 1): Assume that a small signal sinusoidal source vGS = Vpsin([t) is applied to the gate Input current is given by iG = CG (dvGS/dt) = CG [ Vpcos([t) = (Cgs + Cgd) [ Vpcos([t) Output current is given by iDS = gm vGS from the definition of gm If we write the magnitude of the ac current gain, we have |iDS/iG| = |gmvGS / (Cgs + Cgd)[Vpcos([t)| = gm/[(Cgs + Cgd) Where we have replaced Vpcos([t) with vGS since we are using only the magnitudes

Setting the magnitude of the current gain to unity, we obtain fT = gm/2T(Cgs + Cgd)

Because of the manner in which it is derived, fT neglects series gate resistance rg and capacitance on the output, such as Cgd. Unity power gain bandwidth product fmax (frequency where power gain falls to 1): A useful expression for the unity power gain point fmax is given byfmax = [fT / 8TrgCgd]

These figure of merits are useful for technology comparisons and are also often used in high frequency amplifier design


Long-Channel versus Short-Channel Considerations Consider the current gain bandwidth product fT as a function of device parameters:fT = gm / 2TCgs = nCox(W/L)(Vgs Vt) / (2/3)WLCox = 1.5n(Vgs Vt) / L2 where we have assumed the gate capacitance is predominantly the Cgs portion

Note that fT increases with small L (inverse with L2) and with increasing Vgs This is a result based only on a long-channel assumption.

As the channel shortens, the electric field increases beyond the point where mobility is constant any longer (typical of todays advanced CMOS technology) Scattering of electrons by optical phonons causes the drift velocity to saturate at about 1E7 cm/sec, occurring at an electric field Esat = ~ 1E4 V/cm. Beyond this point further increases in E field result in diminishing increases in carrier velocity

This effect represents itself in the IDS current equation by a reduction in Vdssat below Vgs Vt thus reducing IDSsat to less than nCox(W/L)(Vgs Vt)2 If we redefine Vdsat to be determined by the minimum of (Vgs Vt) and LEsat (i.e. sort of having (Vgs Vt) and LEsat in parallel), we can write Vdsat = [(Vgs Vt)(LEsat)] / [(Vgs Vt) + (LEsat)] We can then rewrite the current equation as IDS = nCox(W/L)(Vgs Vt)(Vdsat) = WCox(Vgs Vt) vsat [1 + LEsat/(Vgs Vt)]1 where vsat is the saturation velocity given by nEsat and n is the low field mobility

At short L, the equation becomes IDS = nCoxW(Vgs Vt)Esat which is independent of LR. W. Knepper SC412, slide 8-41

Small Signal Model for a MOSFET The main contribution to the output current is the source gmvgs and is given by the expression below The current source gsvsx is due to the possibility that the source and substrate (bulk) voltages may not be the same.gs = IDS/ VSX = K gm / [2(Vsx + |2JF|)] where K = [ {2qINA}]/Cox and 2JF is the band bending at strong inversion (from Vt equation) In essence gs is a back-gate transconductance which contributes current due to bulk-charge voltage change

rds accounts for the finite output impedance and is given byrds = 1 / P IDS where P is the output impedance constant (defined on slide 8-38)


MOSFET SPICE Model Level 3 SPICE model parameters are shown in the table at the left. The following parameters are given in text for a 0.5 um technology:(PMOS in parentheses if different than NMOS)

PHI=0.7, TOX=9.5E-9, XJ=0.2U TPG=1 (-1), VTO=0.7 (-0.95) DELTA=0.88(0.25), LD=5E-8 (7E-8) KP=1.56E-4 (4.8E-5), UO=420 (130) THETA=0.23 (0.20), RSH=2.0 (2.5) GAMMA=0.62 (0.52) NSUB=1.4E17 (1.0E17) NFS=7.2E11 (6.5E11) VMAX=1.8E5 (3E5) ETA=0.02125 (0.025) KAPPA=0.1 (8) CGDO=CGSO=3.0E-10 (3.5E-10) CGBO=4.5E-10, CJ=5.5E-4 (9.5E-4) MJ=0.6 (0.5), CJSW=3E-10 (2E-10) MJSW=0.35 (0.25), PB=1.1 (1.0)R. W. Knepper SC412, slide 8-43

MOSFET Transistor at Threshold (N-FET)

Kang & Leblebici, CMOS Digital Integrated Circuits, 1999

MOSFET with Vgs > VT causes formation of a channel (inversion layer) connecting source to drain With Vds > 0, a positive current Ids flows from drain to source (N-FET) Depletion layer exists from source, drain, & channel N region to P substrate

At Vgs = VT, bands are bent by |2JF| at oxide-silicon interface Threshold definition (by summation of charges in gate, oxide, channel, and bulk:

VTN = - Qfc/Cox + {2qINA(2JF + Vsx)}/Cox + JMS + 2JF for N-FETs VTP = - Qfc/Cox - {2qINA(|2JF + Vsw|)}/Cox + JMS + |2JF| for P-FETsR. W. Knepper SC412, page 8-44

CMOS NFET and PFET Transistorsoxide gateN+ N N+

oxide gateP+ P+

source

P substrate

drain

source

N well

drain

N channel device

P channel device

VTN = - Qfc/Cox + {2qINA(2JF + Vsx)}/Cox + JMS + 2JF for N-FETs VTP = - Qfc/Cox - {2qINA(|2JF + Vsw|)}/Cox + JMS + |2JF| for P-FETsThreshold Voltage is a square root function of sourceto-substrate per chart at left. Applies to both N and P devices using |Vsx+2JF| Implications for circuit applications where the source voltage rises significantly above ground potential.

R. W. Knepper SC412, page 8-45

DC Bias Considerations for NMOS Diff Amp It is desired to design the NMOS diff amp (below) with device symmetries in such a way that VDS3 = VDS4 = VDSref Since Io/2 = Iref/2 flows through Q3 and Q4, and since Qref, Q3, and Q4 are all biased in their saturation (active) regions where IDS = QnCox (W/L)(VGS VT)2 = K(VGS VT)2 , we can obtain VGS3 = VGS4 = VGSref if W3 = W4 = Wref This condition will be met independent of other device parameter values as long as their ratios remain fixed, i.e. good tracking between devices exists

Assuming that the W of Q6 and Q7 are identical to that of Qref, then we can see that the above current equation will require that VGS6 = VGS7 = VGSref = 1/3 (VDD VSS), where we have neglected any dependence of VT on Vsx. If we set the current in Q3 to that in Qref, we can obtain the following expression VDS3 = E(VDD VSS)/3 + [1 - E]VT where E = (Kref/2Kpu) Thus, setting Kref = 2Kpu leads to VDS3 = 1/3 (VDD VSS) or Vout1 = VDD VDS3 = 2/3 VDD + 1/3 VSS


Modified MOSFET Current Mirror Reference Ckt At left is a modified current mirror reference circuit in which four saturated NMOS transistors split the voltage between VDD and VSS Assuming that each transistor is designed with the same W/L ratio, the reference device VDS will be of VDD VSS Assuming we design transistor Q3 with the W of Qref (as on the previous chart), then we will have VDS3 = (VDD VSS) and Vout1 = (3VDD + VSS)/4 For n reference devices in series, we can generalize the above to Vout1 = [(n-1)/n]VDD + VSS/n Exercises 8.15 and 8.16


Small-Signal Model for the NMOS Diff Amp Ckt The small signal model below is the starting point for deriving the gain expressions for the NMOS differential amplifier Each transistor is modeled by the gate transconductance current source, the back-gate transconductance current source, and the incremental ac impedance of the device in saturation Note the opposite direction of the back-gate (body effect) term is due to the use of bulk-to-source voltage rather than source-to-bulk voltage

The current mirror current source is modeled simply by its output impedance (in saturation) Each transistor is presumed to be in its saturation (constant current) region


Small-Signal Model for NMOS Diff Amp Load Imp We can simplify the equivalent circuit of the previous chart by replacing the load transistors by their Thevenin equivalent resistance looking into their source nodes. Using the test voltage method (shown at left), we can obtain rth = 1/[gm + gmb + (1/ro)] = [1/gm(1 + ')] || ro where gmb = 'gm and ' = {(2I/qNA)/(Vsx + 2JF)} Generally we can assume ' = 0.2, I.e. the back-gate (body) effect adds about 20% to the gate transconductance (if we define the voltage as bulk-to-source) or reduces the gate transconductance about 20% (using the voltage as source-to-substrate).

With the above approximation for the load device, we can simplify the NMOS diff amp incremental model to that shown on the following slideR. W. Knepper SC412, slide 8-49

Simplified Small-Signal Circuit Model of NMOS Diff Amp Differential mode gain can be found from the small signal circuit belowAdm-se1 = -Adm-se2 = - gm1 [(1/gm3(1 + '3)) || ro3 || ro1] Adm-diff = - gm1[(1/gm3(1 + '3)) || ro3 || ro1] and gm = [2QnCox (W/L) IDS] where we have assumed matched pairs Q1 & Q2 and Q3 & Q4 Resistances r01 and r03 are often large enough to be neglected relative to 1/gm

Common mode gain can also be found from the small signal circuit belowAcm-se1 = Acm-se2 = -gm1rth3/[1 + 2ro5gm1(1 + '1)] = ~ rth3/2ro5(1 + '1)

Input impedance is assume to be infinite Output impedance is given byrout-se = rth3 = 1/gm3(1 + '3) and rout-diff = 2/gm3 (1 + '3)


Generic CMOS Differential Amplifier A simple version of a CMOS differential amplifier is shown at the left The load devices Q3 and Q4 are built with PMOS transistors Q3 and Q4 operate as a form of current mirror, in that the small signal current in Q4 will be identical to the current in Q3 Q3 has an effective impedance looking into its drain of 1/gm || ro3 since its current will be a function of the voltage on node vd1 Q4 has an effective impedance looking into its drain of ro4 only, since its current will be constant and not a function of vout

The gain of the right hand (inverting) leg will be higher than the gain of the left side Since all transistors have grounded source operation, there is no body effect to worry about with this CMOS diff amp circuit


CMOS Diff Amp Equivalent Circuit Model


CMOS Diff Amp with Current Mirror Sources


BiCMOS Differential Amplifier


Small Signal Model of BiCMOS Diff Amp


BiCMOS Diff Amp with Cascode BJT EF Devices


JFET Differential Amplifier Circuit


Large Signal Analysis of Bipolar Diff Amp


Large Signal Analysis of MOSFET Diff Amp


Large Signal Analysis of CMOS Diff Amp


Bipolar Diff Amp DC Design Analysis


Bipolar Diff Amp DC Design Example 8.11


NMOS Diff Amp SPICE Simulation Example



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