Ch12 Com Bi National Logic

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CHAPTER 12

COMBINATIONAL LOGIC

Decisions generated by combinational logic involve only the inputs, which constituteinformation supplied in the form of statements. Such a problem may either be the

outcome of a mathematical formulation, resulting in a logic statement for each of the

bits constituting the output, or be an actual set of statements made in English or any

other common language. In the latter case, one has first to assign a binary variable

(symbol) to each of the binary quantities involved, and then obtain a logical

description of the problem in a mathematical language.

12.1 Truth Table

The simplest way to describe the problem in a mathematical form is to list the values

of each (binary) output variable corresponding to all the possible combinations of the

(binary) input variables. Such a listing is known as Truth Table of the system. Let us

illustrate this method by the example of a Half-adder, used to add two 1-bit numbers

A and B to generate a (1-bit) SUM and a (1-bit) CARRY as the output. Table 12.1.1

shows the resulting Truth Table.

Table 12.1.1. Truth Table of Half-adder

A B CARRY SUM

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

The outputs SUM and Carry can be expressed as logical functions of the input

variables A, B and C as follows:

SUM = 1 either if A = 0 and B = 1

or if A = 1 and B = 0

CARRY = 1 only if A = 1 and B = 1.

It is easy to see that the statement for any combinational logic can be expressed in a

similar manner in terms of three basic operations:

(a) OR for expressing a condition which is satisfied when any one or more of

the given conditions are satisfied.

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(b) AND for expressing a condition which is satisfied only if all of the given

conditions are satisfied.

(c) NOT for expressing a condition which is satisfied if a given condition is not

satisfied.

12.2 Basic Postulates of Boolean Algebra

An algebra suitable for expressing problems of combinational logic in a compact

form as well as for convenient manipulation of such logic statements was suggested

by Shannon in 1938, following the original structure proposed by George Boole

(1815-1864), a logician, who had developed an algebra for handling problems of

symbolic logic. Although the simplified form of the original Boolean algebra should

strictly he called Switching Algebra, the name Boolean Algebra is used more or less

universally for this.

The basic postulates of Boolean algebra are as follows.

(1) Variables are restricted to have only one of two possible values 0 and 1

(2) Two arithmetic operations, denoted by the symbols + and . are defined on

Boolean variables so that,

(a) 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1 and 1+1 = 1;

(b) 0 + 0 = 0, 0.1 = 0, 1.0 = 1 and 1.1 = 1.

It is obvious that each of these operations is commutative as well as

associative i.e.

A+B = B+A, A.B = B.A., (A+B)+C = A+(B+C) and A.(B.C) = (A.B.).C

It can also be shown that each of these operations is distributive over the

other i.e.

A.(B+C) = (A.B) + (A.C) and A+(B.C) = (A+B).(A+C).

(3) A complementing operation, indicated by a bar above the symbol, is defined

so that

0 = 1 and 1 = 0.

The two identities given below follow directly from these postulates: __ __

A + A = 1 and A.A = 0. (12.2.1)

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Y = A + B + C

(a) OR (shown with 3 inputs)

(b) AND (shown with 2 inputs)

__

Y = A

A B C Y

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 11 0 1 1

1 1 0 1

1 1 1 1

A B Y0 0 0

0 1 0

1 0 0

1 1 1

A Y

0 1

1 0

=

(c ) NOT (complementation)

Fig. 12.2.1 Basic Logic Functions

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It is obvious that the logic functions OR, AND and NOT correspond to the operations

+, . and complementation respectively. The symbolic representations of these

basic logic functions and their truth tables are shown in Fig. 12.2.1.

12.3 De Morgans Theorem:

It follows from the logic statement for the OR function that a function

Y = A + B + C +

has a value 0 only if all the variables A,B, C, are 0; i.e. one can also express Y

in the following equivalent form: __ __ __ __

Y = A.B.C......

This equivalence may therefore be written as the following identity:

A + B + C + = A B C (12.3.1)

Similarly, from the logic statement for the AND function, one can obtain the

following equivalence:

A B C = A + B +C + (12.3.2)

These are statements of De Morgans theorem and are found to be extremely useful

in the design and analysis of digital circuits. The equivalences expressed by Eqns.12.3.1 and 12.3 2 can be symbolically represented as shown in Fig. 12.3.1. Thus an

alternative way of stating De Morgans theorem is that Positive-Logic AND is

equivalent to Negative-Logic OR and vice-versa.

12.4 Boolean Expressions

Boolean expressions can be obtained for any combinational logic performing a

prescribed function by the following procedure:

(1) For each output variable, construct a truth table giving the different values ofthe output in question for different combinations of the inputs.

(2) Write down the condition for the output in question to be 1 in the form of a

Boolean expression involving the various input variables combined by means

of the OR, AND and NOT operations.

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Let us illustrate this procedure by considering the design of a 1-bit Full Adder. The

circuit has three inputs A, B, C, (one being the carry bit from the next less

significant bit) and two outputs SUM and CARRY. The truth tables for these

outputs for the eight possible combinations of the values that the inputs A, B, C, can

take are shown in Table 12.4.1.

Table 12.4.1. Truth Table of Full Adder

A B C CARRY SUM MINTERM

0 0 0 0 0A B C

0 0 1 0 1 A B C

0 1 0 0 1 A B C

0 1 1 1 0 A B C

1 0 0 0 1 A B C

1 0 1 1 0 A B C

1 1 0 1 0 A B C

1 1 1 1 1 A.B.C.

The last column in Table 12.4.1 lists the AND functions of the 3 input variables A,

B, and C that have to be equal to 1 for the different combinations of the input

variables. Each such AND function is called a .

The Boolean expression for the SUM output can therefore be written down simply by

combining the minterms corresponding to the input combinations resulting in SUM =

1 by an OR statement, as follows: __ __ __ __ __ __

SUM = A.B.C + A.B.C + A.B.C + A.B.C (12.4.1)

Similarly, the minterms corresponding to CARRY = 1 can be combined to obtain the

Boolean expression:

CARRY A B C + A B C + A B C A B C= + (12.4.2)

The expressions given in Eqns. 12.4.1. and 12.4.2. are in the (SOP)

form. An alternative form of Boolean expression can be obtained if one considers the

input combinations leading to output 0. Clearly, the output will be 0 if an OR

combination of all such terms will be 0. Thus one can write the following

expression from the truth table given in Table 12.4.1.

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SUM = A B C + A B C + A B C + A B C

Application of De Morgans theorem then gives

SUM (A + B + C) (A + B + C) (A + B + C) (A + B + C)= (12.4.3)

Similarly, the 0 entries in the Truth Table for CARRY can be combined to obtain

the expression

CARRY A B C + A B C + A B C A B C= +

By applying De Morgans theorem, one therefore obtains

CARRY (A + B + C) (A + B + C) (A + B + C) (A + B + C)= (12.4.4)

Eqns. 12.4.3 and 12.4.4 are in the (POS) form. An OR function of

n literals in an n-variable problem is called , just as an AND function of n

literals is called a minterm; e.g. for the Full Adder (A + B + C) is a maxterm. It

should be noted that each product term in Eqns. 12.4.1 and 12.4.2 is a minterm, and

each sum term in Eqns. 12.4.3 and 12.4.4 is a maxterm. Such expressions constitute

the two canonical forms of Boolean expressions, and are referred to as the standard

SOP and POS forms respectively. In many cases, these Boolean expressions can be

simplified by using the basic postulates of Boolean algebra, resulting in expressions

in the minimal SOP and minimal POS forms respectively.

A systematic method for obtaining a Boolean expression directly in the minimal sum

of products form is based on a geometric representation of the truth table called the

. The resulting expression is minimal in the sense that it contains the

minimum number of (not the minimum number of minterms).

12.5 Karnaugh Map (K-Map)

A K-map is a two-dimensional representation of the truth table of any combinational

logic. It can be constructed for any number of input variables, though it is useful as a

design tool only up to 4 variables. In general, an n-variable K-map is constructed by

listing the various combinations of m input variables along one co-ordinate axis andthose of the remaining n-m input variables along the other co-ordinate axis. If n is

even, one chooses m = n/2 for the sake of symmetry and convenience, while for odd

values of n, m and nm and made to be consecutive integers. Along either axis, the

input combinations are so ordered that only one bit has different values in two

neighbouring input combinations. The configurations of 2-variable, 3-variable and 4-

variable K-maps are given in Fig. 12.5.1.

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The K-map for a given Boolean function of a variables is constructed by entering 1

and 0s in the squares of an n-variable K-map, where the given Boolean function has

the values 1 and 0 respectively. This is illustrated by the K-maps for the SUM and

CARRY outputs of full-adder, as shown in Fig. 12.5.2. Each of these K-maps is a 3-

variable K-map, as a full-adder has 3 inputs. Note that each minterm in Eqns. 12.4.1

and 12.4.2 corresponds to a square having an entry 1 in the K-maps for SUM and

CARRY respectively. It is thus possible to write Eqns. 12.4.1 and 12.4.2 directly

form the K-maps.

Let us now see how a Boolean expression in a minimal form can be written down

directly from the K-map. It follows from the ordering of the input variables along the

axes of the map that two adjacent squares are represented by input combinations

differing only in one variable. Hence if the K-map for a given Boolean function has

1 entered in any two adjacent squares, one can combine the two (n-variable)

minterms representing these two squares into a single (n-1)-variable term. This

would clearly lead to a reduction in the number or literals appearing in the final

Boolean expression.

Let us consider the CARRY output of a full-adder to illustrate this process. The 3-

variable K-map is shown in Fig. 12.5.2 with the 3 sets of adjacent pairs to squares

indicated by loops. Clearly, by virtue of the distributive property of the AND and OR

operations and the identities given in Eqn. 12.2.1, __ __

A.B.C + A.B.C = A.B. (C + C) = A.B, __ __

A.B.C + A.B.C = A.C. (B + B) = A.C and __ __

A.B.C + A.B.C = B.C. (A + A) = A.C,

i.e. a single 2-variable term (A.B, A.C, B.C) represents a pair of two squares

corresponding to two minterms differing only one of the three literals.

The simplified Boolean expression for CARRY thus becomes.

CARRY = A.B + A.C + B.C, (12.5.1)

which is in the minimal sum of products form.

It is obvious from the foregoing algebraic considerations that the two extreme

columns in a 3-variable K-map have to be treated as adjacent. Indeed, it is as though

the rectangle is wrapped around a cylinder so that the two vertical edges coincide.

The combination of two adjacent squares to simplify the Boolean expression can

obviously be extended to the combination of two such adjacent pairs of squares,

which would then be represented by an (n-2)-variable term. Two adjacent pairs ofpairs can again be combined, to yield an (n-3)-variable term, and so on. The number

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of squares which can thus be grouped together so as to be represented by a single

term is therefore a power of 2, e.g. 2, 4, termtermtermtermtermtermtermtermtermtermtermtermtermter


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(3) Write down the minterms for the selected squares which do not have any

adjacent selected or square.

(4) Form binary groups of 2 with those of the remaining selected squareswhich are not members of any larger binary group, and write down the

(n-1)-variable terms required to include all such selected squares.

(5) If n > 2, repeat step 3 for binary groups of 4, and obtain the necessary

(n-2)-variable terms.

(6) If n > 3, repeat step 3 for binary groups of 8, and obtain the necessary

(n-3)-variable terms.

(7) Continue the process with larger binary groups, if necessary; such a

situation will generally not arise as a K-map becomes unwieldy for n > 4.

(8) In the formation of binary groups in any of the foregoing steps, any of the

selected squares can be repeatedly included in as many groups as

necessary for forming the largest possible group.

The procedure for obtaining the minimal Boolean expressions using the K-map

technique is illustrated by the following example.

12.7 BCD to 7-segment Decoder

A 7-segment display consists of 7 bars arranged in a manner that permits the display

of any of the decimal numbers by lighting up a selected few of the 7 segments. Theconfiguration of the 7-segments, their usual nomenclature and the requirement for

each of these segments to be lighted are given in Fig. 12.7.1. These requirements are

directly put in the form of four K-maps, one for the segment and one each for the

pairs of segments , and . The corresponding variables are assumed to have the

value 0 when the segment is lighted, simply as a conventional choice. Reading the

1s, including the squares wherever convenient, from these K-maps gives

Boolean expressions for the 7 outputs in the minimised SOP form, as given below.

a = D C B A + C B A (12.7.1)

b = C B A + C B A (12.7.2)

c = C B A (12.7.3)

d = D C B A + C B A + C B A (12.7.4)

e = C B + A (12.7.5)

f = D C A + C B + B A (12.7.6)

g = D C B + C B A (12.7.7)

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A complementary reading of the same K-map, considering the squares with 0 s as

the selected squares, including the squares as convenient for combining

with the 0s, yields the following expressions.

a = C A + C A + D + B

b = B A + B A + C

c = C + B + A

d = C B A + C A + C B + B A + D

e = C A + B A

f = C B + C A + B A + D

g = C B + C B + B A + D

These expressions in the product of sums form are obtained by applying De

Morgans theorem.

a = (C + A) (C+ A) D B (12.7.8)

b = (B + A) (B + A) C (12.7.9)

c = C B A (12.7.10)

d = (C + B + A ) (C + A) (C + B) (B + A) D (12.7.11)

e = (C+ A) (B+ A) (12.7.12)

f = (C+ B) (C+ A) (B+ A) D (12.7.13)

g = (C+ B) (C + B) (B+ A) D (12.7.14)

It can be shown by algebraic expansion and reduction of these expressions that while

Eqns. 12.7.9,12.7.10 and 12.7.12 give identical expressions for b, c and e as Eqns.

12.7.2, 12.7.3 and 12.7.5, the expressions for the variables a, d, f and g obtained by

the complementary K-map method are not the same as those obtained earlier. This is

typical of problems involving incompletely specified functions.

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12.8 Commercially available Gates

A combinational circuit is the circuit realisation of any combinational logic. The

method of obtaining such a realisation depends on the nature of the logic modules to be used as building blocks. A study of the available logic modules is therefore

necessary before one can proceed with the design procedure of combinational circuits

using gates. Besides OR, AND and NOT gates, NOR (OR followed by NOT) and

NAND (AND followed by NOT) gates are also considered as basic gates. In

addition, combination gates like AOI (AND-OR-INVERT) gates are also available as

commercial gate chips. The circuit symbols and logic functions of these gates are

given in Fig. 12.8.1. Inverting gates (NOR/NAND) have the advantage that all the

three basic logic functions NOT, OR and AND can be obtained using any onetype (NOR or NAND) of inverting gate, as shown in Fig. 12.8.2. The cost or any gate

chip is the same irrespective of the actual type of gate it contains. This uniformity in

cost is consequence of the fact that the tremendously successful mass production

technology employed by the manufacturers of semiconductor devices has or ought

the production cost of the actual semiconductor chip down to less than 1/10 of the

ultimate cost of the packaged device which depends mainly on three factors- (i) the

cost of the package itself, (ii) the volume of production, and (iii) the yield of the

product. Of these three, only the last one depends on the complexity of the circuit

employed. To reduce the package cost, the semiconductor houses have standardised

the package for gates to a 14-pin dual in-line plastic (DIP) package. Leaving two

pins for the d-c power supply, 12 pins are thus available in this package for the actual

gates. As a result of this standardisation, NOT/OR/ AND/ NOR/ NAND gates are

available in the following standard chip configurations:

1. Hex inverters a total of 6 inputs and 6 outputs per chip.

2. Quad 2 - input gates a total of 8 inputs and 4 outputs per chip.

3. Triple 3- input gates a total of 9 inputs and 3 outputs per chip.

4. Dual 4- input gates a total of 8 inputs and 2 outputs per chip.

5. Single 8- input gates a total of 8 inputs and 1 output per chip.

12.9 Multiplexers

Multiplexers were logically designed and used as electronic selector switches, e.g.

the 4-input multiplexer shown in Fig. 12.9.1 has its output Y equal to one of its four

(data) inputs I0, I1, I2 and I3 depending on whether the value of the 2-bit control

(input) BA is 00, 01, 10 or 11. A 4-input multiplexer can therefore be represented by

the Boolean function0 1 2Y = B. A. I + B. A. I + B. A. I + B. A. I3 (12.9.1)

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In general, a multiplexer having a k-bit control input and 2k (data) inputs I0, I1 ,

will have its output Y= Im if the k-bit control input, treated as a binary-coded

number, has a value m. It is obvious that a multiplexer is in fact a direct embodiment

of a truth table. Considering the truth table of a Half-adder given in Table 12.1.1 as

an example, one finds that two 4-input multiplexers, with inputs and control as

shown in Fig. 12.9.1, indeed represent the truth table. Multiplexers thus provide a

viable alternative of gates for the design of combinational circuits. Like gates,

multiplexers are also available in quad 2-input, dual 4-input and single 8-input

packages, the standard package for multiplexers being a 16-pin DIP package.

12.10 Circuits Using Gates Only

Once a given problem of combinational logic has been expresses in terms of Boolean

expressions for the output variable, circuit realisations using AND gates, OR gatesand inverters follow in a straightforward fashion. This is illustrated in parts (a) and

(b) of Fig. 12.10.1, which give two alternate circuit realisations of the CARRY

output of a Half-adder. The two alternative forms of the simplified Boolean

expression for the CARRY output are reproduced below for reference.

CARRY = A.B. + A.C + B.C (12.5.1)

and CARRY = (A+B) . (A+C) . (B+C) (12.5.3)

One notes that each of the two circuits needs both AND and OR gates.

It is possible to obtain realisations of Boolean expressions using only one kind of

gate NAND or NOR, by virtue of De Morgans theorem. Eqn. 12.5.1. can be

written in the equivalent form

CARRY = A.B . A.C . B.C (12.10.1.)

Which immediately leads to the circuit realisation given in Fig. 12.10.1(c), using

NAND gates only. Circuits having such structures are called two-level NAND or

NAND-NAND realisations. As the K-map technique can always be used to express

the output variable of any combinational logic problem in the minimal sum of

products form, it follows that any combinational logic problem can be realised in the

NAND-NAND structure.

An alternative realisation using NOR gates only results if De Morgans theorem is

applied to Eqn. 12.5.3, yielding the equivalent expression

CARRY = A B + A C B C+ + + + , (12.10.2.)

which has the two-level NOR or NOR-NOR realisation shown in Fig. 12.10.1 (d).

Like to NAND-NAND realisation, the NOR-NOR realisation is also possible for any

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combinational logic problem, as the Boolean expression for any output variable can

always be obtained in a minimal product of sums form.

As has been pointed out in Sec. 12.8, the cost of any circuit realisation is determined

by the chip count, i.e. the number of IC chips required. A comparison of the fourcircuits given in Fig. 12.10.1 on this count shows that all of them require 2 chips

one for the three 2-input gates at the first (or input) level and the other for the 3-input

gate at the second (or output) level. However, one should not generalise on the basis

of this comparison that the four alternative circuit realisations always require the

same chip count. Realisations based on a single inverting gate NAND or NOR

will in general give lesser chip count than the AND-OR or OR-AND realisations,

because of the possibility of sharing gates on the same chip at both levels of these

configurations.

12.11 Circuits Using Multiplexers

Multiplexers can be used to obtain the circuit realisation of any given truth table as

given in Sec. 12.9. Such a scheme requires a multiplexer with n-bit control i.e. a 2n-

input multiplexer, for an n-variable problem. The inputs to the multiplexers in this

scheme are simply the 0 s and 1 s appearing is the corresponding entries in the

truth table. A more practical scheme for realising any combinational logic with

multiplexers is to generate inputs from one of the n variables, using the remaining (n-

1) variables as the control inputs. Clearly, the chip count would be reduced in thisapproach. The exact procedure for generating the necessary input from the K-map(s)

pertaining to a given problem is outlined in Fig. 12.11.1, which depicts a 3-variable

problem with A and B used as the control inputs of a 4-input multiplexer. The

functional dependence of the inputs I0, I1, I2 and I3 on the variable C would be

determined by the entries in the pairs of squares indicated by I0, I1, I2 and I3

respectively in the K-map. This is illustrated by the realisation of a Full Adder,

having the K-maps given in Fig. 12.11.2. By simple inspection, one can write the

following expressions for the inputs necessary for each of the two 4-input

multiplexers one giving SUM and the other giving CARRY as the output:

SUM MUX : 0 1 2 3I = C, I = C, I = C and I = C,

CARRY MUX : 0 1 2 3I = O, I = C, I = C and I = 1.

__

Thus if both C and C are available, a Full Adder can be realised by a dual 4-input

multiplexer, resulting in half the chip count in comparison with a realisation using 8-

input multiplexers.

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One could go a step further and consider the possibility of realising an n-variable

combinational logic with multiplexers having (n-2)bit control, using the remaining

two bits to generate the necessary inputs. Fig. 12.11.3 shows how a 4-variable K-map

can partitioned into four parts, each part corresponding to four squares having the

same values of A and B. Thus if a 4-input multiplexer is used to realise a 4-variable

K-map, using A as the control of the multiplexer, the four inputs I0, I1, I2 and I3 can

be read off from these four parts in the same manner as any K-map is read, and

Boolean expressions written for these four inputs in terms of the remaining variables

C and D, This would of course require some gates besides as many multiplexers as

the number of output variables, but the total chip count would in general be lower in

this approach. This technique is best-suited for large problems involving a number of

outputs, and the BCD to 7-segment Decoder discussed in Sec. 12.7 is taken up for an

illustration. Referring back to the K-maps given in Fig. 12.7.1. and using BA as the

control, one can prepare a table of the required input functions I0 to I3 from the K-

maps of the seven segments, as given in Table 12.11.1. These inputs have been read

off from the respective maps in their simplest form just as through each column were

a K-map in two variables. As seen from the table, there is only one nontrivial input

function D.C = D + C required to provide I0 for the segment g and I1 for the

segments a, d, f and g, which can be generated by a single 2-input NOR gate.

Segment c has the simplest Boolean expression, which can be realised by a 3-input

NOR gate:c = C . B . A = C + B + A

Assuming the complements of the variables to be available, this leads to a chip count

of 4, as compared to 7 chips in a NAND-NAND realisation.

Table 12.11.1. Multiplexer input functions for BCD to 7-segment decoder

Input No a b c d e f g

I0 C 0 0 C C 0 __ __

D.C

I1 __ __D.C C 0 __ __D.C 1

__ __D.C

__ __D.C

I2 C C C 0 0 C 0

I3 0 0 0 C 1 1 C

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Ch12 Com Bi National Logic