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Binary Logic and GatesBoolean AlgebraStandard Forms
Map SimplificationTabulation Method
NAND and NOR GatesExclusive-OR GatesIntegrated Circuits
Lesson 2Combinational Logic Circuits
Binary Logic
� Deals with variables that take on two discrete values and with operation that assume logical meaning.
� The manipulation and processing of binary information.
� Uses values, variables and operations:� True is represented by the value 1 (ON).� False is represented by the value 0 (OFF).
Binary Logic
� Digital circuits are implemented using transistors and interconnections in complex semiconductor devices called integrated circuits .
� Each basic circuit is referred to as a logic gate .
Basic Logical Operators
� AND� Represented by a dot (.) or no operator� Will yield 1 if all the inputs are 1
� OR� Represented by a plus (+) symbol� Will yield 1 if at least one of the inputs is 1
� NOT� Represented by a bar or prime (‘) � It will complement the input
Other Logic Gates
� NAND� Performs the complement of AND� Will yield 0 if all the inputs are 1
� NOR� Performs the complement of OR� Will yield 0 if at least one of the inputs is 1
� Buffer� Retains the input value
Other Logic Gates
� XOR� Will yield 1 if the inputs are complementing each
other
� XNOR� Will yield 1 if the inputs are the same� Opposite of XOR
Binary Logic
� Variables are represented by letters and can have one of two values, either 0 or 1.
� Operations are functions of one or more variables.� AND is represented by X.Y� OR is represented by X + Y � NOT is represented by X'
� These basic operations can be combined to give expressions.
Switching Circuit
LAMP
1 2
SW2
1 2
AND gate
12
SW1
1 2
Switching Circuit
OR gate
SW1
12
12
SW2
12
LAMP
1 2
Switching Circuit
SW1
12
NOT gate
12
LAMP
12
Truth Tables
� A means of representing the results of a logic function using a table.
� They are constructed by defining all possible combinations of the inputs to a function, and then calculating the output for each combination in turn.
Truth Tables
AND OR NOT
X Y Z X Y Z X Y
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1
Truth Tables
NAND NOR Buffer
X Y Z X Y Z X Y
0 0 1 0 0 1 0 0
0 1 1 0 1 0 1 1
1 0 1 1 0 0
1 1 0 1 1 0
Truth Tables
XOR XNOR
X Y Z X Y Z
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
Assignment 2-1
� Construct the equivalent switching circuit of the following gates:
� NAND� NOR� Buffer� XOR� XNOR
Boolean Algebra
� It deals with binary variables and logic operations.
� In honor of George Boole� English mathematician� Published a book introducing the mathematical
theory of logic in 1854
Boolean Algebra
� Duality Principle
� The duality principle of Boolean algebra states that a Boolean equation remains valid if we take the dual of the expressions on both sides of the equals (=) sign.
� To get the DUAL of a Boolean Expression:Interchange:
o OR = ANDo 1 = 0
Boolean AlgebraIdentities
X + 0 = X X . 1 = X
X + 1 = 1 X . 0 = 0
X + X = X X . X = X
X + X’ = 1 X . X’ = 0
X’’ = X
Commutative Law
X + Y = Y + X XY = YX
Associative Law
X + (Y + Z) = (X + Y) + Z X(YZ) = (XY)Z
Distributive Law
X(Y + Z) = XY + XZ X + YZ = (X + Y)( X + Z)
DeMorgan’s Theorem
(X + Y)’ = X’Y’ (XY)’ = X’ + Y’
Examples
� X + XY = X
� XY + XY’ = X
� X + X’Y = X + Y
� (X + Y)(X + Y’) = X
� X(X’ + Y) = XY
Consensus Theorem
� A consensus or redundant term can be eliminated.
� Examples:
XY + X’Z + YZ = XY + X’Z
and its dual:
(X + Y)(X’ + Z)(Y + Z) = (X + Y)(X’ + Z)
Consensus Theorem
� Proof:
XY + X’Z + YZ= XY + X’Z + (X + X’) YZ= XY + X’Z + XYZ + X’YZ= XY (1 + Z) + X’Z (1 + Y)= XY + X’Z
Boolean Functions
� An expression formed with binary variables (0 or 1) and its logical operands (logic gates).
� Example: F = xyz’F = AB + CDF = (wx’ + y) z
Algebraic Manipulation
Original Function: F = X’YZ + X’YZ’ + XZ
345
6
1 2
X
123
1213
5
1 212
1312
Y
1
23
F
Z
Algebraic Manipulation
Simplified Function: F = X’Y + XZ
Z
X
Y
4
56
F
1
23
1
23
1 2
Complement of a Function� It is obtained from an interchange of 1’s to 0’s and 0’s
to 1’s for the values of F in the truth table.
� It can be derived algebraically through the use of DeMorgan’s theorem.
� The generalized form is to interchange the AND andOR operations and complement each variable and constant.
� A simpler method is to take the dual of the function and complement each literal.
Example
� Find the complement of the following functions:
1. F1 = X’YZ’ + X’Y’Z
2. F2 = X (Y’Z’ + YZ)
Seatwork 2-1 (30 minutes)
� Simplify the following Boolean expressions to a minimum number of literals:
1. ABC + ABC’ + A’B2. A’BC + AC3. BC + B(AD + AD’)
� Find the complement of the following expressions:1. A’B + A’B2. ABC + A’C’ + (AB)’3. (V’W + X)Y + Z’
4. (A + B’ + AB’)(AB + A’C + BC)5. ((A + B) + A’B’)(C’D’ + CD) + (AC)’6. W’X(Z’ + Y’Z) + X(W + W’YZ)
4. WX(Y’Z + YZ’) + W’X’(Y’ + Z)(Y + Z’)5. (A + B’ + C)(A’B’ + C)(A + B’C’)6. A(B’C + B’C) + C(BD + (B’D’)’)
Standard Forms
� It facilitate the simplification procedures and would result in more desirable logic circuits
� It contain:�Product terms (Minterms)
� AND operation� Example: x’yz’
�Sum terms (Maxterms)� OR operation� Example: x + y’ + z
Minterms and Maxterms
� Minterm� A product term in which all the variables appear
exactly once, either complemented or uncomplemented.
� Has a value of 1 (uncomplemented).
� Maxterm� A sum term that contains all the variables in
complemented or uncomplemented form.� Has a value of 0 (uncomplemented).
Minterms and Maxterms
� Characteristic property: Minterms and maxterms represent exactly one combination of the binary variables in a truth table
� There are 2n distinct minterms/maxterms for n variables
Minterms and Maxterms
Product
TermX Y Z
0 0 0 X’Y’Z’
0 0 1 X’Y’Z
0 1 0 X’YZ’
0 1 1 X’YZ
1 0 0 XY’Z’
1 0 1 XY’Z
1 1 0 XYZ’
1 1 1 XYZ
Sum
TermX Y Z
0 0 0 X+Y+Z
0 0 1 X+Y+Z’
0 1 0 X+Y’+Z
0 1 1 X+Y’+Z’
1 0 0 X’+Y+Z
1 0 1 X’+Y+Z’
1 1 0 X’+Y’+Z
1 1 1 X’+Y’+Z’
Minterms for Three Variables
Product
Term SymbolX Y Z m0 m1 m2 m3 m4 m5 m6 m7
0 0 0 X’Y’Z’ m0 1 0 0 0 0 0 0 0
0 0 1 X’Y’Z m1 0 1 0 0 0 0 0 0
0 1 0 X’YZ’ m2 0 0 1 0 0 0 0 0
0 1 1 X’YZ m3 0 0 0 1 0 0 0 0
1 0 0 XY’Z’ m4 0 0 0 0 1 0 0 0
1 0 1 XY’Z m5 0 0 0 0 0 1 0 0
1 1 0 XYZ’ m6 0 0 0 0 0 0 1 0
1 1 1 XYZ m7 0 0 0 0 0 0 0 1
Maxterms for Three Variables
Sum
Term SymbolX Y Z M0 M1 M2 M3 M4 M5 M6 M7
0 0 0 X+Y+Z M0 0 1 1 1 1 1 1 1
0 0 1 X+Y+Z’ M1 1 0 1 1 1 1 1 1
0 1 0 X+Y’+Z M2 1 1 0 1 1 1 1 1
0 1 1 X+Y’+Z’ M3 1 1 1 0 1 1 1 1
1 0 0 X’+Y+Z M4 1 1 1 1 0 1 1 1
1 0 1 X’+Y+Z’ M5 1 1 1 1 1 0 1 1
1 1 0 X’+Y’+Z M6 1 1 1 1 1 1 0 1
1 1 1 X’+Y’+Z’ M7 1 1 1 1 1 1 1 0
ExampleInput Output
x y z F F’
0 0 0 1 0
0 0 1 0 1
0 1 0 1 0
0 1 1 0 1
1 0 0 0 1
1 0 1 1 0
1 1 0 0 1
1 1 1 1 0
Important Properties
1. There are 2n minterms (maxterms) for n Boolean variables.
2. Any Boolean function can be expressed as a logical sum of minterms (product of maxterms).
3. The complement of a function contains those minterms (maxterms) not included in the original function.
4. A function that includes all the 2n minterms(maxterms) is equal to logic 1 (0).
Sum of Products (Sum of Minterms)
� An alternative standard form of expression that contains product terms with any number of literals/variables.
� Gate structure consists of a group of AND gates followed by an OR gate.
� Example:F = y’ + x’yz’ + xy
Product of Sums (Product of Maxterms)
� An alternative standard form of expression that is obtained by forming a logical product of sum terms.
� Gate structure consists of a group of OR gates followed by an AND gate.
� Example:F = x (y’ + z) (x + y + z’)
Function from Truth Table
� SOP form:F = Σ m(0, 2, 6, 7)
� POS form:F = Π M(1, 3, 4, 5)
X Y Z F
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Map Simplification
� Karnaugh map , or K-map , is a diagram made up of squares, with each square representing one minterm of the function.
� It is a straightforward procedure for simplifying Boolean functions up to four variables.
� But cumbersome to use for functions with five to six variables.
Two-Variable Map
yx 0 1
yx 0 1
0 m0 m1 0 x’y’ x’y
1 m2 m3 1 xy’ xy
(a) (b)
Three-Variable Map
yz
x 00 01 11 10
yz
x 00 01 11 10
0 m0 m1 m3 m20 x’y’z
’x’y’z x’yz x’yz’
1 m4 m5 m7 m61 xy’z’ xy’z xyz xyz’
(a) (b)
Four-Variable Map
yz
wx00 01 11 10 yz
wx00 01 11 10
00 m0 m1 m3 m200 0 1 3 2
01 m4 m5 m7 m601 4 5 7 6
11 m12
m13
m15
m14
11 12 13 15 14
10 m8 m9 m11
m10
10 8 9 11 10
(a) (b)
Simplification using K-maps
Simplify the following Boolean functions:
1. F(x, y, z) = Σm(2, 3, 4, 5)2. F(x, y, z) = Σm(3, 4, 6, 7)3. F(x, y, z) = Σm(0, 2, 4, 5, 6)4. F(w, x, y, z) = Σm(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)5. F(A, B, C, D) = Σm(0, 2, 4, 5, 6, 7, 8, 10, 13, 15)6. F(w, x, y, z) = ΠM(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)
Prime Implicants
� A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map.
� If a minterm in a square is covered by only one prime implicant, that prime implicant is said to be essential .
Prime Implicants� F (A, B, C, D) = Σ (0, 2, 3, 5, 7, 8, 9, 10, 11, 13,
15)
CDAB
00 01 11 10 CDAB
00 01 11 10
00 1 1 1 00 1 1 1
01 1 1 01 1 1
11 1 1 11 1 1
10 1 1 1 1 10 1 1 1 1
Essential prime implicants
Prime Implicants
Selection Rule
� Minimize the overlap among prime implicantsas much as possible. In particular, in the final solution, make sure that each prime implicantselected includes at least one minterm not included in any other prime implicant selected.
Prime Implicants
� Examples:
1. F(A,B,C,D) = Σm (0, 1, 2, 4, 5, 10, 11, 13, 15)
2. F(W,X,Y,Z) = WX’ + WXZ + W’Y’Z’ + W’XY’ + WXZ’
Don’t-Care Conditions
� Two cases of occurrence:1. The input combinations never occur2. The input combinations are expected to occur,
but we do not care what the outputs are in response to these combinations
� Functions that have unspecified outputs for some input combinations are called incompletely specified functions .
� The unspecified minterms of a function are called don’t-care conditions .
Simplification with Don’t Care Conditions
� Example:F(A, B, C, D) = Σm (1, 3, 7, 11, 15)
d(A, B, C, D) = Σm (0, 2, 5)
Five-Variable Map
� F (A, B, C, D, E) = Σ (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)
Seatwork 2-2 (30 minutes)� Simplify the following Boolean functions by finding all
prime implicants and essential prime implicants and applying the selection rule:
1. F(W,X,Y,Z) = Σm (1, 5, 6, 7, 11, 12, 13, 15)
2. F(W,X,Y,Z) = ΠM (1, 3, 5, 6, 7, 9, 10, 11, 14)
3. F(A,B,C) = A’B’ + AC’ + B’C + A’BC’
4. F(A,B,C,D) = (A’+B’+D)(A’+D’)(A+B+D’)(A+B’+C+D)
5. F(A, B, C, D, E) = Σm (0, 1, 4, 5, 16, 17, 21, 25, 29)
Simplifying a Boolean Function through Tabulation (Quine-McCluskey Method)
� The tabular method consists of two parts:� Finding the all the terms that are candidates for
inclusion in the simplified function (prime implicants)� Choosing among the prime implicants those that give
an expression with the least number of literals
� Example:
1. F (W, X, Y, Z) = Σm (0, 1, 2, 8, 10, 11, 14, 15)2. F (W, X, Y, Z) = Σm (1, 4, 6, 7, 8, 9, 10, 11, 15)
For the function F(W,X,Y,Z) = Σm(0,1,2,8,10,11,14,15)
(a) (b) (c)
WXYZ WXYZ WXYZ
0 0000 / 0, 1 000- 0,2,8,10 -0-0
0,2 00-0 / 0,8,2,10 -0-0
1 0001 / 0, 8 -000 / 10,11,14,15 1-1-
2 0010 / 10,14,11,15 1-1-
8 1000 / 2, 10 -010 /
8, 10 10-0 /
10 1010 / F = W’X’Y’ + X’Z’ + WY
10, 11 101- /
11 1011 / 10, 14 1-10 /
14 1110 /
11, 15 1-11 /
15 1111 / 14, 15 111- /
For the function F(W,X,Y,Z) = Σm(1,4,6,7,8,9,10,11,15)
(a) (b) (c)
0001 1 / 1, 9 (8) 8, 9, 10, 11 (1, 2)
0100 4 / 4, 6 (2) 8, 9, 10, 11 (1, 2)
1000 8 / 8, 9 (1) /
8, 10 (2) /
0110 6 /
1001 9 / 6, 7 (1)
1010 10 / 9, 11 (2) /
10, 11 (1) /
0111 7 /
1011 11 / 7, 15 (8)
11, 15 (4)
1111 15 /
Decimal W X Y Z Term
1, 9 (8) - 0 0 1 X’Y’Z
4, 6 (2) 0 1 - 0 W’XZ’
6, 7 (1) 0 1 1 - W’XY
7, 15 (8) - 1 1 1 XYZ
11, 15 (4) 1 - 1 1 WYZ
8, 9, 10, 11 (1, 2) 1 0 - - WX’
1 4 6 7 8 9 10 11 15
/ X’Y’Z 1, 9 X
/ W’XZ’ 4, 6 X X X
W’XY 6, 7 X X
XYZ 7, 15 X X
WYZ 11, 15 X X
/ WX’ 8,9,10,11 X X X X
/ / / / / / /
Seatwork 2-3 (30 minutes)
� Simplify the following Boolean functions by means of the tabulation method:
1. F (A, B, C, D, E) = Σm (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)
2. P(A,B,C,D,E,F) = Σm (6, 9, 13, 18, 19, 25, 27, 29, 41, 45, 57, 61)
NAND and NOR Gates
� Used extensively as standard logic gates� More popular than AND and OR gates� Natural functions for the simplest electronic
circuits
Logical Operations with NAND Gates
Y
X
1 2
1
23 X'
1 2
OR
AND
(XY)'' = XY
NOT
X
(X'Y')' = X + Y
Y
X
1
23
1 2
1
23
Graphic Symbols for NAND and NOT Gates
X
(c) NOT
1 2
(a) AND-NOT20 1
Y
X'
X(XY)'
X' + Y'1
23
(b) NOT-OR
X
Y
X
1
23
X'
Procedure for two levels
1. Simplify the function and express it in sum-of-products form.
2. Draw a NAND gate for each product term of the expression that has at least two literals (1st level).
3. Draw a single gate using the AND-NOT or the NOT-OR graphics symbol at the 2nd level, with inputs coming fro outputs of 1st level gates.
4. A term with a single literal requires a NOT at the first level. However, if the single literal is complemented from its original appearance it can be connected directly to an input of the 2nd level NAND gate.
Implementation with NAND Gates
� Examples:
1. F = XY’ + X’Y + Z2. F = (AB’ + A’B)E(C + D’)
1
23
4
56
Y'
F
X'
Y'
X 1
23
X'
X
4
56
Y'
F1
23
X
F4
56
Y
1
23
4
56
Z'
Y
Y
1 2
Z'
Z
1
23
X'
F = XY’ + X’Y + Z
General Procedure
1. Convert all AND gates to NAND gates with AND-NOT graphic symbols.
2. Convert all OR gates with NOT-OR graphic symbols.
3. Check all the bubbles in the diagram. For every bubble that is not counter-acted by another bubble along the same line, insert a NOT gate or complement the input literal from its original appearance.
1
23
4
56
D'
B
4
56
F
4
56
C
4
56
9
108
A'
B'
F
E
B'
1
23
1
23
9
108
1
23
A
E
12
1311
D'
A'B
A
C
1 2
12
1311
3 4
F = (AB’ + A’B)E(C + D’)
12
1311
E
9
108
A'
C
12
1311
12
1311
B'
F
B
1
23
A
12
1311
4
56
12
1311
D'
Logical Operations with NOR Gates
(X + Y)'' = X + Y
X
2
31
Y
1 2
1 2
2
31
AND
X
Inverter
X
X'2
31
1 2
X'
Y
(X' + Y') = XY
OR
1 2
X
Graphic Symbols for NOR Gate
X 2
31
Y
(b) NOT-AND
Y
(X + Y)'
X'Y' = (X + Y)'X 1
23
(a) OR-NOT
Implementation with NOR Gates
� Examples:
1. F = (A + B)(C + D)E2. F = (AB’ + A’B)E(C + D’)
1
23
C
E'
2
31
5
64
12
1312
F
FC
2
31
5
64
1
23
D
B
AB
D
1
23
D
F
E'
4
56
E'
A
A
C
BF = (A + B)(C + D)E
E
4
56
12
1311
1 29
108
E'
B
C
12
1311
1
23
B'
F
4
56
D'
A
1
23
A'
C
4
56
D'
1
23
1
23
FB
4
56
A'
AB'
9
108
8
910
8
910
5
64
11
1213
A 2
31
B'
C
A'
2
31
FB
D'
5
64
E'
F = (AB’ + A’B)E(C + D’)
Seatwork 2-4 (30 minutes)
� The following function is to be implemented with a minimum gate multilevel circuit (three or more levels of gates not counting inverters on the inputs or output). Assume the complements of the inputs are not available.F(A,B,C,D) = A’B’CD + A’BCD’ + AB’C’D + ABC’D’
� Use NAND gates only.� Use NOR gates only.
Exclusive-OR Gates� XOR is a logical operation that performs the
functionF = X + Y = XY’ + X’Y
� Equal to 1 if exactly one variable is equal to 1.
Exclusive-OR Gates� XNOR is the complement of the XOR function.
� Expressed by the functionF = X + Y = XY + X’Y’
� Equal to 1 if both X and Y are equal to 1 or if both are equal to 0.
� Also known as the equivalence.
Exclusive-OR Gates� Identities:
X + 0 = X X + 1 = XX + X = 0 X + X = 1X + Y = X + Y X + Y = X + Y
� Properties:� Commutative� Associative
Odd and Even Function� Odd function is a function that has a value of 1 if
the number of 1s in the input is ODD.� Example: XOR
� Even function is a function that has a value of 1 if the number of 1s in the input is EVEN.� Example: XNOR
Parity Generation and Checking
� The circuit that generates the parity bit in the transmitter is called a parity generator .
� The circuit that checks the parity in the receiver is called a parity checker .
Truth table for an Even Parity Generator
Three-bit Message Parity bit
X Y Z P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Boolean functions and logic diagram
ZP
1
23
P
Y
C
X
1
23
Y
1
23
Z
X
1
23
1
23
P = X + Y + Z
C = X + Y + Z + P
Seatwork 2-5 (30 minutes)
� Construct a 3-bit odd parity generator and checker. Show the following:
� Truth table� Boolean functions� Logic diagram
Integrated Circuits� Levels of Integration
1. Small-scale integrated (SSI) � Number of gates is usually less than 10� Limited by the number of pins available on the
IC
2. Medium-scale integrated (MSI)� About 10 to 100 gates in a single package� Usually performs elementary digital functions
(addition)
Integrated Circuits� Levels of Integration
3. Large-scale integrated (LSI) � Contains between 100 and a few thousand
gates in a single package� Examples: microprocessors, memory
4. Very large-scale integrated (VLSI)� Contains several thousands to over 100 million
gates in a single package� Examples: microprocessors, DSP chips
Digital Logic Families
� The circuit technology is referred to as a digital logic family .
� The primitive circuits in each technology are typically NAND, NOR, and NOT gates.
� The electronic components used in the construction of the basic circuit usually give the name of the technology.
Most Important Logic Families� RTL Resistor-transistor logic� DTL Diode-transistor logic� TTL Transistor-transistor logic� ECL Emitter-coupled logic� MOS Metal-oxide semiconductor� CMOS Complementary metal-oxide
semiconductor� BiCMOS Bipolar complementary metal-oxide
semiconductor� GaAS Gallium-Arsenide
Most Important Logic Families� RTL and DTL
� Earliest logic families� obsolete
� TTL� Widely used for decades� Declining rapidly in use
� ECL� Advantageous in systems requiring high-speed
operation� Rapidly overtaken by CMOS
� MOS� For circuits that need high component density
Most Important Logic Families� CMOS
� For systems requiring low power consumption� Dominant technology
� BiCMOS� Combines CMOS with a bit of TTL� Used in cases in which CMOS cannot provide
adequate current or the necessary speed
� GaAS� Used selectively for very high speed circuits
Most Important Parameters
� Fan-in specifies the number of inputs available on a gate.
� Fan-out specifies the number of standard loads that the output of a typical gate can drive without impairing its performance.
� Noise margin is the maximum external noise voltage superimposed on a normal input value that will not cause an undesirable change in the circuit output.
Most Important Parameters
� Power dissipation is the power consumed by the gate and made available from the power supply.
� Propagation delay is the delay time for the change in value of a signal to propagate from input to output.
Propagation Delay Parameters
� The high-to-low propagation time t PHL is the delay measured from the reference voltage on the input voltage IN to the reference voltage on the output voltage OUT, with the output voltage going from H to L.
� The low-to-high propagation time t PLH is the delay measured from the reference voltage on the input voltage IN to the reference voltage on the output voltage OUT, with the output voltage going from L to H.
Two Models Used During Simulation� Transport delay , the change in an output in
response to the change of an input occurs after a specified propagation delay.
� Inertial delay , the change in an output in response to the change of an input also is delayed by a specified propagation delay. But if the input changes cause the output to change twice in an interval less than the rejection time , then the first of the two output changes does not occur.� The rejection time is a specified value no large
than the time delay and is often equal to the time delay.
Quiz #2 Coverage
� Simplification of Boolean functions� Boolean algebra� Karnaugh map� Tabulation method
� Implementation of Boolean functions using only NAND or NOR gates
