Com Bi National Logic

8/8/2019 Com Bi National Logic

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COMBINATIONAL &

SEQUENTIALLOGIC

CIRCUITS

NISHA PRAKASH

ADE (EEC 309)


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Boolean Algebra/Logic Circuits

Why are they called logic circuits?

Logic: The study of the principles ofreasoning.

The 19th Century Mathematician,George Boole, developed a mathsystem (algebra) involving logic,Boolean Algebra.

His variables took on TRUE, FALSE

Later Claude Shannon (father ofinformation theory) showed (in hisMasters thesis!) how to map Boolean

Algebra to digital circuits: like gates(AND, OR NOT,ETC)


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An Introduction to Digital Logic

Integrated Circuits

The building blocks of computers

Designed for specialized functions

Examples: the CPU, bus interface, memorymanagement unit

Transistors: primary components of ICs

Motorola MPC 7400 PowerPC modules: 6.5million transistors in less than in2


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Transistors

Boolean algebra: basis for computer logic design

Transistors: means for implementing Booleanalgebra

Switches: on/off to represent the 0s and 1s ofbinary digital circuits

Combined to form logic gates


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Digital Circuits

Combinatorial logic

Results of an operation depend only on the

present inputs to the operation Uses: perform arithmetic, control data movement,

compare values for decision making

Sequential logic

Results depend on both the inputs to the

operation and the result of the previous operation Uses: counter


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Boolean Algebra

Rules that govern constants and variables that cantake on 2 values

True/false; on/off; yes/no; 0/1 Boolean logic

Rules for handling Boolean constants andvariables

3 fundamental operations:

AND, OR and NOT Truth Table: specifies results for all possible input

combinations


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LOGIC GATES


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DIGITAL LOGIC

COMBINATIONAL

LOGIC

SEQUENTIAL

LOGIC


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Digital systems

A digital system is a system whoseinputs and outputs fall within adiscrete, finite set of values

Two main types

Combinational

Outputs dependent only oncurrent input

Sequential

Outputs dependent on bothpast and present inputs


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Combinational or Sequential?

A circuit is combinatorial if and only if its outputdepends exclusively on its input:

Out = fn (In) A circuit is sequential otherwise, that is, if its

output depends on some internal state (andpossibly on the input too):

Out = fn (In, State)

Having a state means that the circuit has amemory


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A circuit made of gates (AND, OR, XOR, etc.)without any loop is guaranteed to becombinatorial


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Block diagram-Combinational circuits

This circuit consists of logic gates whose outputs at any timeare determined from the present combinations of inputs.

A combinational circuit performs an operation that can bespecified logically by a set of Boolean functions.

Combinational circuitInputsn

Outputsm


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Combinational

circuit

Inputvariables

Logic gates

Outputvariables


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Examples:

ADDERS(BINARY, BCD)

SUBTRACTOR

MULTIPLEXER/DEMULTIPLEXER

DECODER/ENCODER

MAGNITUDE COMPARATOR

CONVERTERS(ALL SORT)

BINARY MULTIPLIERS

ANY BOOLEAN FUNCTION CAN BE IMPLEMENTED BY THEANY BOOLEAN FUNCTION CAN BE IMPLEMENTED BY THECOMBINATIONAL CIRCUITS.COMBINATIONAL CIRCUITS.


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Need for multiplexing?


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Multiplexer

A MULTIPLEXER is a combinational circuit that selects binaryinformation from one of many input lines and directs it to asingle output line.

The selection of a particular input line is controlled by a set ofselection lines.

Normally, there are 2n input lines and n- selection lines whosebit combination determines which part is selected.


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A 2-to-1 line MUX connects one of two 1-bit sources toa common destination as shown:

A MUX acts like a switch that selects one of two sources.

If S=0, Y=I0

If S=1, Y=I1


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Select the Source Register - The source register maybe selected by a Multiplexer circuit. (One multiplexerper bit).

A 4-to-1 line MUX : Each of four inputs, I0 through I3applied to one of input of AND gate. Selection lines S1and S0 are decoded to select a particular AND gate.The output of AND gate are applied to OR gate thatprovides the 1-line output.

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3


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Consider an integer m, which is

constrained by the following relation:

m = 2n,where m and n are both integers.

A m-to-1 Multiplexer has

m Inputs: I0, I1, I2, ................ I(m-1) one Output: Y n Control inputs: S0, S1, S2, ...... S(n-1) One (or more) Enable input(s)

such that Y may be equal to one of the inputs,

depending upon the control inputs.

Example of a Combinatorial Circuit:

A Multiplexer (MUX)


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Example: A 4-to-1 Multiplexer

I0

A 4-to-1 Multiplexer:

I1

I2

I3

S0 S1

Y

1 output

n control inputs

2n inputs

Enable(G)


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Characteristic Table of a Multiplexer

If the MUX is enabled,

s0 s10 0 Y=I0

0 1 Y=I1

1 0 Y=I2

1 1 Y=I3

Putting the above information in the form of a Booleanequation,

Y = S1.S0.I0 + S1.S0.I1 + S1.S0.I2 + S0.S1.I3


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A multiplexer is also called DATA SELECTOR, it selectsone of many inputs and steers the binary information tothe output lines.

8-to-1 line MUX


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16-to-1lineMUX


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Implementing Boolean Function using

Multiplexer

METHOD 1 : Using a Mux with n-select inputsn variables needto be connected to n select inputs. For a MUX with n selectinputs, the output Y is given by:


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The MUX output expression is a SUM of mintermsexpression for all minterms (mi) which have theircorresponding inputs (Di) equal to 1.

Thus, it is possible to implement any function of n-variables using a MUX with n-select inputs by properassignment of the input values (Di{0 , 1}).

Y(Sn-1 .. S1S0) = (minterms)


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Example: Implement the function

F (A, B, C) = (1, 3, 5, 6)

Since number of variables n = 3, this requires a MUX with 3select inputs, i.e. an 8x1 MUX.

The most significant variable A is connected to the mostsignificant select input S2 while the least significant variable Cis connected to the least significant select input S0 ,

Thus: S2 = A, S1 = B, and S0 = C

For the MUX output expression (sum of minterms) to includeminterm 1 we assign D1 =1

Likewise, to include minterms 3, 5, and 6 in the sum ofminterms expression while excluding minterms 0, 2, 4, and 7,the following input (Di) assignments are made.


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S2(A) S1(B) S0(C) D(output)

0 0 0 D0=0

0 0 1 D1=1

0 1 0 D2=00 1 1 D3=1

1 0 0 D4=0

1 0 1 D5=11 1 0 D6=1

1 1 1 D7=0


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D1 = D3 = D5 = D6 = 1D0 = D2 = D4 = D7 = 0


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METHOD 2 : Using a MUX with (n-1) select inputs

Any n-variable logic function can be implemented using a Muxwith only (n-1) select inputs (e.g 4-to-1 mux to implement any3 variable function)

This can be accomplished as follows: Express function in canonical sum-of-minterms form. Choose n-1 variables to be connected to the mux select

lines. Construct the truth table of the function, but grouping the

n-1 select input variables together (e.g. by making the n-1select variables as most significant inputs).

The values of Di (mux input line) will be 0, or 1, or nth variableor complement of nth variable of value of function F, as will beclarified by the following example.


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Example : Implement the functionF (A, B, C) = (1, 2, 6, 7)

This function can be implemented with a 4-to-1 line MUX.a) The first (n-1) variables of function are connected to selection

inputs of MUX.

b) The remaining single variable of the function is used for datainputs. If the single variable is denoted by C, each data input ofMUX will be C, C, 1 or 0.

a) => A and B are applied to the select line,that is A => S1

B => S0b) => C is 0 and 1

The truth table of the function and the implementation are asshown:


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DEMUX

It is a digital function that performs inverse of themultiplexing operation.

It has one input line (E) and transmits it to one of2n possible output lines (D0, D1, D2, ,D2n-1).

The selection of the specific output is controlled bythe bit combination of n select inputs.


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Example : A 1-to-2 line Demux

This circuit uses the same AND gates and the same addressingscheme as the two-input multiplexer circuit .

The basic difference is that it is the inputs that are combinedand the outputs that are separate. By making this change, we

get a circuit that is the inverse of the two-input multiplexer.


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DECODER/ENCODER What is a decoder ?

In older days, the (good) printers used be like typewriters:

To print A, a wheel turned, brought the A key up, which

then was struck on the paper. Letters are encoded as 8 bit codes inside the computer.

When the particular combination of bits that encodes A is

detected, we want to activate the output line correspondingto A (Not actually how the wheels worked)

How to do this detection : decoder General idea: given a k bit input,

Detect which of the 2^k combinations is represented

Produce 2^k outputs, only one of which is 1.


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What a decoder does ?

A n-to-2n decoder takes an n-bit input and produces 2noutputs. The n inputs represent a binary number thatdetermines which of the 2n outputs is uniquely true.

A 2-to-4 decoder operates according to the following truthtable:

The 2-bit input is called SIS0 (serial in, serial out) and thefour outputs are Q0-Q3.

If the input is the binary number i, then output Qi is

uniquely true. Follow the design procedures from last time! We have a

truth table, so we can write equations for each of the fouroutputs (Q0-Q3), based on the two inputs (S0-S1).


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Enable inputs

Many devices have an additional enable input, which is used toactivate or deactivate the device.

For a decoder, EN=1 activates the decoder, so it behaves as specified

earlier. Exactly one of the outputs will be 1.

EN=0 deactivates the decoder. By convention, that meansall of the decoders outputs are 0.

We can include this additional input in the decoders truth table:


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In this table, note that wheneverEN=0, the outputs are always 0,

regardless of inputs S1 and S0.

We can abbreviate the table by

writing Xs in the input columnsfor S1 and S0.


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Blocks and abstraction

Decoders are common enough that we want to encapsulatethem and treat them as an individual entity.

Block diagrams for 2-to-4 decoders are shown here. The namesof the inputs and outputs, not their order, is what matters.

A decoder block provides abstraction: You can use the decoder as long as you know its truth table

or equations, without knowing exactly whats inside. It makes diagrams simpler by hiding the internal circuitry. It simplifies hardware reuse. You dont have to keep

rebuilding the decoder from scratch every time you need it.


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A Decoder is a Demultiplexer with a

change in the name of the inputs :

Y0

Y1

Y2

Y4

S1 S0

ENABLE

INPUT

2 to 4Decoder

When the IC is used as a Decoder, the input I is calledan Enable input


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SEQUENTIALCIRCUITS


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Properties of Sequential Circuits

So far we have seen Combinational Logic

The output (s) depends only on the current values of theinput variables.

Here we will look at Sequential Logic circuits The output(s) can depend on present and also past values of

the input and the output variables

Sequential circuits exist in one of a defined number of states atany one time

they move "sequentially" through a defined sequence oftransitions from one state to the next

The output variables are used to describe the state of asequential circuit either directly or by deriving state variablesfrom them.


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LATCHES

FLIP-FLOPS:- S-R FLIP-FLOP

J-K FLIP-FLOP

T FLIP-FLOP

D FLIP-FLOP


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Combinational

Logic

Storage

Elements

Inputs

Outputs

StateNextState


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Inputs Outputs

Clock pulses

CombinationalCircuit

Flip-Flop

Clock pulses


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Synchronous

the timing of all state transitions is controlled by acommon clock

changes in all variables occur simultaneously

Asynchronous

state transitions occur independently of any clockand normally dependent on the timing of transitions

in the input variables changes in more than one output do notnecessarily occur simultaneously


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Clock A clock signal is a square wave of fixed frequency Often, transitions will occur on one of the edges ofclock pulses i.e. the rising edge or the falling edge


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Latches In the same way thatgates are the building blocks

ofcombinatorial circuits,

latches and flip-flops are the building blocks ofsequential circuits.

While gates had to be built directly fromtransistors, latches can be built from gates, and

flip-flops can be built from latches. This fact will make it somewhat easier to

understand latches and flip-flops!


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The difference between a latch and a flip-flop is that a latch does not have a clock signal,

whereas a flip-flop always does.

How can we make a circuit out of gates that isnot combinatorial?

The answer is feed-back, which means that wecreate loops in the circuit diagrams so that outputvalues depend, indirectly, on themselves.


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Basic (NOR) SR Latch

Cross-coupling two

NOR gatesgives S-RLatch

S (set)

R (reset)Q

Q

R S Q Q Comment

0 0 ? ? Stored state unknown

0 1 1 0 Set Q to 10 0 1 0 Now Q remembers 1

1 0 0 1 Reset Q to 0

0 0 0 1 Now Q remembers 0

1 1 0 0 Both go low

0 0 ? ? Unstable!

Time


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R S Q Q Comment


0 1 1 0 Set Q to 1

0 0 1 0 Now Q remembers 11 0 0 1 Reset Q to 0


1 1 0 0 Both go low

0 0 ? ? Unstable!

Time

Thewaveformshows theoperation ofNOR gates

based RSLatch.


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Basic (NAND) S-R Latch

Cross-Couplingtwo NAND gates

givesthe S-R Latch

S = 0, R = 0 isforbidden as

input pattern

QS (set)

R (reset) Q

R S Q Q Comment


1 0 1 0 Set Q to 1


0 1 0 1 Reset Q to 0


0 0 1 1 Both go high

1 1 ? ? Unstable!

Time


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Clocked S-R Latch

Adding two NANDgates to the basic

S-R NAND latchgives the clockedSR latch:

Has a time sequence behavior similar to the basic S-R latchexcept that the S and R inputs are only observed when theline C is high.

C means control or clock.

S

R

Q

C

Q


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Clocked (Gated) S-R Latch

The Clocked S-R Latch can be described by a table

The table describeswhat happens after the

clock [at time (t+1)]based on: current inputs (S,R) and

current state Q(t).

Q(t) Q(t+1) omme t

0 0 0 0 o c a ge0 0 1 0 lear Q

0 1 0 1 et Q

0 1 1 ??? I etermi ate

1 0 0 1 o c a ge

1 0 1 0 lear Q

1 1 0 1 et Q

1 1 1 ??? I etermi ate

S

R

Q

Q

C


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D Latch Adding an inverter

to the S-R Latch,gives the D Latch:

Note that there areno indeterminatestates!

Q D Q(t 1) Comment

0 0 0 No change

0 1 1 Set Q

1 0 0 Clear Q

1 1 1 No Change

The gra hic sym ol for a

D atch is:

C

D Q

Q

D

Q

C

Q


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It is also called Transparent Latch


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Flip-Flops Master-slave flip-flop

Edge-triggered flip-flop

Standard symbols for storageelements


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Two clockedS-R latches in serieswith the clock on thesecond latch inverted

The input is observedby the first latch with C = 1

The output is changed by the second latch with C = 0

The path from input to output is broken by thedifference in clocking values (C = 1 and C = 0).

The behavior demonstrated by the example with Ddriven by Y given previously is prevented since the clockmust change from 1 to 0 before a change in Y based onD can occur.

C

S

R

Q

Q

C

R

Q

Q

C

S

R

QS

Q

S-R Master-Slave Flip-Flop


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Edge-Triggered D Flip-Flop

The edge-triggeredD flip-flop is thesame as the master-slave D flip-flop

It can be formed by:

Replacing the first clocked S-R latch with a clocked D latch or

Adding a D input and inverter to a master-slave S-R flip-flop

The delay of the S-R master-slave flip-flop can be avoided

since the 1s-catching behavior is not present with Dreplacing S and R inputs

The change of the D flip-flop output is associated with thenegative edge at the end of the pulse

It is called a negative-edge triggered flip-flop

C

S

R

Q

QC

Q

QC

DQD

Q

i i Ed T i d D


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Positive-Edge Triggered D

Flip-Flop Formed by

adding inverterto clock input.

Q changes to the value on D applied at thepositive clock edge within timing constraints tobe specified.

Our choice as the standard flip-flop for mostsequential circuits

C

S

R

Q

Q

C

Q

QC

DQD

Q

St d d S b l f St


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Master-Slave:

Postponed outputindicators

Edge-Triggered:

Dynamicindicator

(a) Latches

S

R

SR SR

S

R

D with 0 Control

D

C

D with 1 Control

D

C

(b) Master-Slave Flip-Flops

D

C

riggered Driggered SR

S

R

C

D

C

riggered Driggered SR

S

R

C

(c) Edge- riggered Flip-Flops

riggered D

D

C

riggered D

D

C

Standard Symbols for Storage

Elements


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Other Flip-Flop Types J-K and T flip-flops

Behavior

Implementation Basic descriptors for understanding

and using different flip-flop types

Characteristic tables Characteristic equations

Excitation tables


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J-K Flip-flop Behavior

Same as S-R flip-flop with J analogous to S and Kanalogous to R

Except that J = K = 1 is allowed, and

For J = K = 1, the flip-flop changes to the oppositestate

As a master-slave, has same 1s catching behavioras S-R flip-flop

If the master changes to the wrong state, that state

will be passed to the slave E.g., if master falsely set by J = 1, K = 1 cannot

reset it during the current clock cycle


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J-K Flip-flop Implementation To avoid 1s catching

behavior, one solutionused is to use anedge-triggered D asthe core of the flip-flop

Symbol

D

CK

J

J

CK


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T (Toggle)Flip-flop Behavior

Has a single input T For T = 0, no change to state

For T = 1, changes to opposite state Same as a J-K flip-flop with J = K = T

As a master-slave, has same 1scatching behavior as J-K flip-flop

Cannot be initialized to a known stateusing the T input Reset (asynchronous or synchronous)

essential


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T Flip-flop Implementation

To avoid 1s catchingbehavior, one solutionused is to use an

edge-triggered D asthe core of the flip-flop

Symbol

C

DT

T

C


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Basic Flip-Flop Descriptors Used in analysis

Characteristic table - defines the next stateof the flip-flop in terms of flip-flop inputs

and current state Characteristic equation - defines the next

state of the flip-flop as a Boolean function ofthe flip-flop inputs and the current state

Used in design Excitation table - defines the flip-flop input

variable values as function of the currentstate and next state


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D Flip-Flop Descriptors Characteristic Table

Characteristic EquationQ(t+1) = D

Excitation Table

D

0

1

Operation

Reset

Set

0

1

Q(t 1)

Q(t 1)

0

1

0

1

D Operation

Reset

Set

D type Flip Flop


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D-type Flip-Flop

D = inputQ = output signal

Q = NOT(Q)CK = clock signal

Q takes the value of Dwhen the CK signal is

active.


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T Flip-Flop Descriptors Characteristic Table

Characteristic EquationQ(t+1) = T Q

Excitation TableQ(t 1)

Q(t)

1

0

T

No change

Com lement

Operation

t

No changeComplement

Operation

01

T Q(t 1)

Q(t)

Q(t)

+


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S-R Flip-Flop Descriptors Characteristic Table

Characteristic Equation

Q(t+1) = S + R Q, S.

R = 0 Excitation Table

Operation

No change

Set

Reset

No change

S

X

0

1

0

Q(t+1)

0

1

1

0

Q(t)

0

0

1

1

R

X

0

1

0

0

01

1

OperationS

0

10

1

R

No change

ResetSet

Undefined

01

?

Q(t+1)

Q(t)


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J-K Flip-Flop Descriptors Characteristic Table

Characteristic EquationQ(t+1) = J Q + K Q

Excitation Table

0

0

1

1

No change

Set

Reset

Complement

OperationJ

0

1

0

1

K

0

1

Q(t+1)

Q(t)

Q(t)

Q(t

+

1)

0

1

1

0

Q(t)

0

0

1

1

Operation

X

X

0

1

K

0

1

X

X

J

No change

Set

Reset

No Change


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ANALYSIS OF CLOCKED

SEQUENTIAL CIRCUITS


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State Diagrams

The sequential circuit function can berepresented in graphical form as a statediagram with the following components: A circle with the state name in it for each state A directed arc from the Present State to the Next

State for each state transition

A label on each directed arc with the Input valueswhich causes the state transition, and

A label: On each circle with the output value produced, or

On each directed arc with the output valueproduced.


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State Diagrams Label form:

On circle with output included:

state/output Moore type output depends only on state

On directed arc with the outputincluded:

input/output Mealy type output depends on state and

input


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Circuits that include flip-flops are usually classifiedby the function they perform rather than by thename of the sequential circuits.

Two such circuits are:

Registers

Counters

Sequential circuits


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Registers

A register is a group offlip-flops.

Each flip-flop is capableof storing 1 bit ofinformation.

An n-bit register

consists of n-flip-flopscapable of storing n-bitof binary information.

Counters

A counter is a register

that goes throughpredetermined sequenceof states.

A Counter is a specialtype of register.

An n-bit counter consistsof n-flip-flops and cancount in binary from 0 to2n-1.


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A flip-flop stores one bit of information

When a set of n flip-flops is used to store n - bits ofdata, we refer to these flip-flops as a Register

Common register usages include

Holding a data value output from an arithmeticcircuit.

Holding a count value in a counter circuit.

A common clock signal is typically used for eachflip-flop in a register.

REGISTERS

Serial data transfer


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One application of shift registers is converting betweenserial data and parallel data.

Computers typically work with multiple-bit quantities. ASCII text characters are 8 bits long. Integers, single-precision floating-point numbers, and screen

pixels are up to 32 bits long.

But sometimes its necessary to send or receive data serially,or one bit at a time. Some examples include:

Input devices such as keyboards and mice. Output devices like printers. Any serial port, USB device transfers data serially. Recent switch from Parallel ATA to Serial ATA in hard drives.

Receiving serial data


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Receiving serial data To receive serial data using a shift register:

The serial device is connected to the registers SI input. The shift register outputs Q3-Q0 are connected to the

computer.

The serial device transmits one bit of data per clock cycle.

These bits go into the SI input of the shift register.

After four clock cycles, the shift register will hold a four-bitword.

The computer then reads all four bits at once from the Q3-Q0outputs.

Sending data serially


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Sending data serially To send data serially with a shift register, you do the

opposite:

The CPU is connected to the registers D inputs. The shift output (Q3 in this case) is connected to the

serial device. The computer first stores a four-bit word in the register,

in one cycle. The serial device can then read the shift output.

One bit appears on Q3 on each clock cycle. After four cycles, the entire four-bit word will have been

sent.

Shift register


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Shift register

A register that provides the ability to shift its

contents by a single bit

May be to the right or left (or possibly both)

Shift right register


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Example: Basic four-bit shift register

A basic four-bit shift register can be constructedusing four D flip-flops, as shown in Figure.


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The operation of the circuit is as follows:

The register is first cleared, forcing all four outputsto zero.

The input data is then applied sequentially to the Dinput of the first flip-flop on the left (FF0). During each clock pulse, one bit is transmitted from

left to right.

Assume a data word to be 1101. The least significant bit of the data has to be shifted

through the register from FF0 to FF3.


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Example Shift right register

Assume a data word to be 1101.

Such that Q0Q1Q2Q3 = 1101

Initially Q0Q1Q2Q3 = 0000

(all FF are reset by Clear pin)

Data is entered from left side towards the right.

Data inData out


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Q0Q1Q2Q3 = 0100

Q0Q1Q2Q3 = 1000


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Q0Q1Q2Q3 = 1101

Q0Q1Q2Q3 = 1010


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Example Shift left register

Assume a data word to be 1101.

Such that Q0Q1Q2Q3 = 1101

Initially Q0Q1Q2Q3 = 0000

(all FF are reset by Clear pin)

Data is entered from right most FF and o/p is takenfrom left most FF.

Data inData out


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Q0Q1Q2Q3 = 0011

Q0Q1Q2Q3 = 0001


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Q0Q1Q2Q3 = 1101

Q0Q1Q2Q3 = 0110


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For this kind of register, data bits are enteredserially in the same manner as discussed in the last

section.

The difference is the way in which the data bitsare taken out of the register. Once the data arestored, each bit appears on its respective output

line, and all bits are available simultaneously.

A construction of a four-bit serial in - parallelout register is shown.


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For parallel in - parallel out shift registers, all data bits appearon the parallel outputs immediately following thesimultaneous entry of the data bits. The following circuit is afour-bit parallel in - parallel out shift register constructed by D

flip-flops.


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Parallel-in, parallel-out( universal shift register)

A register capable of shifting in only one direction isa Unidirectional shift register.

One that shift in both direction is called Bidirectional

shift register. If a register has both shifts and parallel load

capabilities, it is referred to as Universal shiftregister.

The purpose of the parallel-in/ parallel-out shift

register is to take in parallel data, shift it, thenoutput it as shown below. A universal shift register isa do-everything device in addition to the parallel-in/parallel-out function.


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Mode control


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s1 s0 Registeroperation

0 0 No change

0 1 Shift right

1 0 Shift left

1 1 Parallel load

The selection lines(S1S0)controls the

Operation of theregister according thefunction table


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Counters

What is counter?

Count 1,2,3100 and back to 1,2..

A counter is a sequential logic circuitcapable of counting the number of clockpulses arriving at its clock input.

The sequence can be : ascending ordescending.

A specified sequence of states appear atthe counter.


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Special purpose arithmetic circuits used for thepurpose of counting

Design circuits that can increment or decrement acount by 1

Counter circuits serves many purposes Count occurrences of certain events Generate timing intervals for controlling various tasks

in a digital system

Track elapsed time between events Often (but not always) built with T flip-flops because

the toggle feature is naturally suited for implementingthe counting operation


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A counter is set of flip-flops (FFs) whose stateschanges in response to pulses applied at input.

The pulses can be in the form of clock.

A counter that follows the binary number sequenceis called Binary Counter. An n-bit counter consists of n- FFs and can count in

binary from 0 through 2n-1. They can be of two types : a) up-counter

(ascending)b) down-counter

(descending)


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RIPPLE

(ASYNCHRONOUS)COUNTERS

SYNCHRONOUS

COUNTERS

COUNTERS


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RIPPLE COUNTER

The FF o/p transitionact as source of

triggering other FF. (that means FF is not

triggered by acommon clock ratherby the o/p transition

that occur in otherFFs).

This form of counteris slow

SYNCHRONOUS COUNTER

The Clock i/p of all the FFsreceives a common clock.

Therefore, they aresynchronized only by asingle clock.

Faster response than

asynchronous counters


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Binary count sequenceIf we examine a four-bitbinary count sequence

from 0000 to 1111, adefinite pattern will beevident in the"oscillations" of the bitsbetween 0 and 1:


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Note how the least significant bit (LSB)toggles between 0 and 1 for every step in thecount sequence, while each succeeding bit

toggles at one-half the frequency of the onebefore it.

The most significant bit (MSB) only togglesonce during the entire sixteen-step countsequence: at the transition between 7 (0111)

and 8 (1000).


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Rising-edge and falling-edge clock inputs


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Counting occurs when the clock input changes

state. Mostsynchronous counters count on the

rising-edge which is the low to hightransition of the clock signal.

Mostripple counters count on the falling-edge which is the high to low transition of theclock signal.


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2-bit Asynchronous(Ripple) counter

A two-bit asynchronous counter is shown.

The external clock is connected to the clock inputof the first flip-flop (FF0) only. So, FF0 changes

state at the falling edge of each clock pulse, but FF1changes only when triggered by the falling edge ofthe Q output of FF0.

Because of the inherent propagation delay througha flip-flop, the transition of the input clock pulse

and a transition of the Q output of FF0 can neveroccur at exactly the same time.

Therefore, the flip-flops cannot be triggeredsimultaneously, producing an asynchronousoperation.


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State diagram


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11

10

00

01

State diagram

Usually, all the CLEAR inputs are connected together,so that a single pulse can clear all the flip-flopsbefore counting starts


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before counting starts. The clock pulse fed into FF0 is rippled through the

other counters after propagation delays, like a rippleon water, hence the name Ripple Counter. The 2-bit ripple counter circuit above has four

different states, each one corresponding to a countvalue. Similarly, a counter with n flip-flops can have2 to the power n states. The number of states in acounter is known as its mod (modulo) number. Thusa 2-bit counter is a mod-4 counter.

A mod-n counter may also described as a divide-by-ncounter. This is because the most significant flip-flop(the furthest flip-flop from the original clock pulse)

produces one pulse for every n pulses at the clockinput of the least significant flip-flop (the onetriggers by the clock pulse). Thus, the above counteris an example of a divide-by-4 counter.

MOD Number MOD number indicates the number of states in


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MOD number indicates the number of states inthe counting sequence.

If 3 FFs were use, the sequence of stateswould count in binary from 000 to 111, a totalof 8 states. This would be called a MOD-8counter.

In general, if N FFs are cascaded, the counterwill have 2N different states, and so it isMOD-2N.

It would be capable of counting up to 2n 1before returning to its 0 state.

MOD number = 2N

N- the number of FFs

The following is a 3-bit asynchronous binary counterand its timing diagram for one cycle. It works exactlythe same way as a two-bit asynchronous binary counter


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the same way as a two bit asynchronous binary countermentioned above, except it has eight states due to the

third flip-flop.


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000State diagram


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111

100

110

101011

010

001

000

3-bit asynchronous binary counter is also calledMOD-8 counter and Divide- by-8 counter.

4-bit asynchronous binary


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y ycounter

Ripple counter (Mano)


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4-bit asynchronous binary counter is alsocalled MOD-16 counter and Divide- by-16


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counter.1111 0000

0011

1010

00010010

0100

0101

011001111000

1001

1100

1011

1110

State diagram


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4-bit asynchronous binary counter is alsocalled MOD-16 counter and Divide- by-16counter.

Because of the frequency of the last FF is equalto the clock frequency 16.

fD=f /16 ; fD = frequency of IVth FFf = clock frequency


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A common application is in machine motion control, wheredevices called rotary shaft encoders convert mechanicalrotation into a series of electrical pulses these pulses


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rotation into a series of electrical pulses, these pulses"clocking" a counter circuit to track total motion:


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Synchronous Counter

The problems encountered with asynchronous arecaused by :

Accumulated FF propagation delays

FFs do not all change states simultaneously insynchronism with the input pulses.

This limitations can be overcome with the use ofsynchronous or parallel counters

The function is the same to count number, but theoperation is different


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The differences between synchronous andasynchronous:

1. The CLK inputs of all of the FFs are connected

together so that the input signal is applied to eachFF simultaneously

2. Only FF A, the LSB has its J and K inputs

permanently at the HIGH level, The J,K inputs of

the others FFs are driven by some combination ofFF outputs

3. The synchronous counter requires more circuitry

than does the asynchronous counter

A synchronous counter, in contrast to anasynchronous counter, is one whose output


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bits change state simultaneously, with no

ripple.

The only way we can build such a counter

circuit from J-K flip-flops is to connect all theclock inputs together, so that each and everyflip-flop receives the exact same clock pulse atthe exact same time.

Now, the question is, what do we do with the J and Kinputs?


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We know that we still have to maintain the


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same divide-by-two frequency pattern in order

to count in a binary sequence, and that thispattern is best achieved utilizing the "toggle"mode of the flip-flop, so the fact that the J and Kinputs must both be (at times) "high" is clear.

However, if we simply connect all the J and Kinputs to the positive rail of the power supply aswe did in the asynchronous circuit, this wouldclearly not work because all the flip-flops would

toggle at the same time: with each and everyclock pulse!

This circuit will not act as a counter!


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Because all the flip-flops would toggle at thesame time: with each and every clock pulse!

Let's examine the four-bit binary countingsequence again, and see if there are any otherpatterns that predict the toggling of a bit


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patterns that predict the toggling of a bit.

Asynchronous counter circuit design isbased on the fact that each bit toggle happensat the same time that the preceding bit toggles

from a "high" to a "low" (from 1 to 0).

Since we cannot clock the toggling of a bitbased on the toggling of a previous bit in asynchronous counter circuit (to do so would

create a ripple effect) we must find some otherpattern in the counting sequence that can beused to trigger a bit toggle.


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Examining the four-bit binary countsequence, another

predictive pattern canbe seen. Notice that justbefore a bit toggles, allpreceding bits are"high:"

This pattern is also something we can


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exploit in designing a counter circuit.

If we enable each J-K flip-flop to togglebased on whether or not all preceding

flip-flop outputs (Q) are "high," we canobtain the same counting sequence asthe asynchronous circuit without theripple effect, since each flip-flop in this

circuit will be clocked at exactly the sametime:


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The result is a four-bit synchronous "up"counter. Each of the higher-order flip-flops aremade ready to toggle (both J and K inputs


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"high") if the Q outputs of all previous flip-flops

are "high." Otherwise, the J and K inputs forthat flip-flop will both be "low," placing it intothe "latch" mode where it will maintain itspresent output state at the next clock pulse.Since the first (LSB) flip-flop needs to toggle at

every clock pulse, its J and K inputs areconnected to Vcc or Vdd, where they will be"high" all the time. The next flip-flop need only"recognize" that the first flip-flop's Q output is

high to be made ready to toggle, so no AND gateis needed. However, the remaining flip-flopsshould be made ready to toggle only when alllower-order output bits are "high," thus theneed for AND gates.

To make a synchronous "down" counter, we need

to build the circuit to recognize the appropriate


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g pp p

bit patterns predicting each toggle state while

counting down. Not surprisingly, when we

examine the four-bit binary count sequence, we

see that all preceding bits are "low" prior to a

toggle (following the sequence from bottom to

top):


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Since each J-K flip-flopcomes equipped with aQ' output as well as a Q

output, we can use theQ' outputs to enablethe toggle mode oneach succeeding flip-flop, being that each Q'

will be "high" everytime that the respectiveQ is "low:"


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Documents

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