Cellular Array-based Delay-insensitive Asynchronous
Circuits Design and Test for Nanocomputing Systems
Jia Di Parag K. Lala
[email protected] [email protected]
Comp. Science & Comp. Eng. Engineering & Information Science
University of Arkansas Texas A&M University at Texarkana
Fayetteville, AR 72701 Texarkana, TX 75501
This paper presents the design, layout, and testability analysis of delay-insensitive circuits on
cellular arrays for nanocomputing system design. In delay-insensitive circuits the delay on a
signal path does not affect the correctness of circuit behavior. The combination of delay-
insensitive circuit style and cellular arrays is a useful step to implement nanocomputing systems.
In the approach proposed in this paper the circuit expressions corresponding to a design are
first converted into Reed-Muller forms and then implemented using delay-insensitive Reed-
Muller cells. The design and layout of the Reed-Muller cell using primitives has been described
in detail. The effects of stuck-at faults in both delay-insensitive primitives and gates have been
analyzed. Since circuits implemented in Reed-Muller forms constructed by the Reed-Muller cells
can be easily tested offline, the proposed approach for delay-insensitive circuit design improves
a circuits testability. Potential physical implementation of cellular arrays and its area overhead
are also discussed.
Index terms: cellular arrays, delay-insensitive circuit; Reed-Muller expression, stuck-at fault;
layout, nanoscale circuit
Complementary metal-oxide semiconductor (CMOS) has been the dominant technology for
implementing VLSI systems because it provides a good trade-off of high speed and small area.
The continuous decrease in transistor feature size has been pushing the CMOS process to its
physical limits caused by ultra-thin gate oxides, short channel effects, doping fluctuations, and
the unavailability of lithography in nanoscale range. To continue the size/speed improvement
trends according to Moores Law, nanoelectronic and molecular electronic devices are needed. A
significant amount of research has been done in nanoscale computing system design [1-5].
Although recent research have resulted in the development of basic logic elements and simple
circuits in nanoscale, there are still debates on what logic style and architecture will be the best
for nanocomputers. A family of asynchronous logic called delay-insensitive circuits has drawn
attention in recent years. The advantages of delay-insensitive circuits include flexible timing
requirement, low power, high modularity, etc. These characteristics fit the needs of nanoscale
computing. Cellular arrays have an ideal architecture for implementing delay-insensitive circuits
in nanoscale; they have highly regular structures, simple cell behavior, and flexible scalability
[6-7]. The regular structure together with delay-insensitive circuit style makes cellular arrays a
viable option for implementing nanocomputing systems.
In this paper the design and layout of delay-insensitive circuits on cellular arrays are
presented. One appealing approach to design nanoscale circuits is to express the logic functions
in the Reed-Muller form using AND and XOR gates only ; the Reed-Muller representation of
Boolean functions have been discussed in detail in section 5. The main motivation for using the
Reed-Muller form is that the testability of circuits implemented from Reed-Muller expansions is
considerably improved compared to that of their original forms. This paper presents the design
and layout of a delay-insensitive Reed-Muller cell which is composed of the three primitives
proposed in . In addition, a potential physical implementation for asynchronous circuits on
cellular arrays introduced by IBM researchers , and the effects of possible stuck-at faults on
this molecular implementation have been analyzed. Certain faults in these circuits can be
detected during normal operation without applying any external test patterns i.e. the faults can be
detected on-line . However, faults that escape on-line detection can be easily detected off-line
by applying a few external test patterns; this is possible because of the Reed-Muller expression-
based structure of the delay-insensitive circuits.
2. Delay-insensitive circuits
Currently synchronous logic is predominantly used in commercial integrated circuit chip
design. Synchronous logic uses a global clock to control logic behavior. On the other hand
asynchronous logic delay-insensitive circuits do not require a clock. Delay-insensitivity is
achieved by checking the completion of an operation in a subblock and sending a signal to
previous subblock stages to acknowledge the completion. The clock-less operation of such
circuits lead to the following benefits:
No clock skew Since delay-insensitive asynchronous circuits have no globally
distributed clock, clock skew need not be considered.
High energy efficiency Delay-insensitive circuits generally have transitions only where
and when involved in the current computation. Some implementations inherently eliminate
glitches, therefore decreasing energy consumption.
Robust external input handling Since signals do not need to be synchronized with a
clock, delay-insensitive circuits accommodate external inputs thus avoiding the metastability
problem in synchronous circuits .
Low noise and low emission In mixed-signal circuits, a digital subcircuit usually
generates noise and/or emits electromagnetic (EM) radiation which affects the whole circuit
performance. Due to the absence of a complex clocking network, delay-insensitive circuits may
have better noise and EM properties. 
Asynchronous circuits are very different from Boolean logic based synchronous circuits and
are usually more difficult to design without appropriate CAD tools. This remains a major
obstacle to the use of asynchronous logic systems. However, in recent years the clock skew
problem in synchronous circuits is becoming increasingly critical. Because of above listed
advantages delay-insensitive circuits utilizing dual-rail encoding are becoming popular. Dual-rail
encoding uses a two-rail code to represent a data bit as shown in Table 1 .
State Rail 1 Rail 0 Spacer 0 0 Data 0 0 1 Data 1 1 0 Invalid 1 1
Table 1 Dual-rail encoding truth table
As can be seen in Table 1, besides Data 0 and Data 1 there is a spacer state denoted by both
rails being logic low. For each circuit element, after a data bit has been processed, it goes to a
spacer state before it is allowed to process the next data. This is known as the return-to-spacer
protocol. This return-to-spacer procedure is actually a self-resetting step of the circuit operation.
Delay-insensitivity is achieved by checking the completion of an operation in a subblock and
sending a signal to previous subblock stages to acknowledge the completion. Dual-rail encoding
is used to design delay-insensitive circuits in this paper.
3. Asynchronous cellular arrays
Cellular arrays have been widely studied as a computational model. A cellular array is a d-
dimensional array of identical cells, which are placed next to each other. Each cell has a finite
number of states. Based on its current state and the states of its neighbor cells, the cell can
change its state by an operation known as a transition . Following certain transition rules, the
cellular arrays are able to perform logic computation as well as data storage.
In this paper, two-dimensional cellular arrays are used. Each cell has four bits, represented by
rectangles located at north, south, east, and west, respectively, as shown in Fig. 1. If one or more
rectangles in a cell are filled a signal is said to have arrived at this cell. An empty rectangle
represents a logic 0 and a filled rectangle (also known as a block) represents a logic 1, as
shown in Fig. 2. Depending on the physical implementation, signals can be generated by
different phenomena. In the molecular cascade structure which will be explained in the next
section, signals are generated by CO molecular hopping.
Fig. 1 Cell structure
Fig. 2 A 2-D cellular array
Based on the von Neumann neighborhood definition, the cells next state will be determined
by its current state and states of the four nearest bits of its nearest orthogonal cells as shown in
Fig. 3. The letters in the rectangles of each cell represent the bit-states (0 or 1) of the cell.
Fig. 3 Transition of cell
A cell changes its state based on previously mentioned transition rules as shown in Table 2
below . There is no timing restraint on such transitions, except that two neighboring cells may
not be updated simultaneously. Instead, the cells are updated in order following the signal