BJT DC Biasing 29 Aug 2014

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EE321: Analog Circuits Laboratory

Experiment 1: BJT DC Biasing

Objectives

1. To study various methods of biasing a BJT and

2. Their effect on bias stability

Introduction

Transistors used in amplifier circuits must be biased into an active state with constant (direct) levels of

collector, base and emitter current and constant terminal voltages. The levels of collector current (Ic) and

collector-emitter voltage (Vce) define the transistor dc operating point , or quiescent point Q. The circuit that

provides this state is known as a bias circuit . Ideally, the current and voltage levels in bias circuits should

remain absolutely constant. In practical circuits these quantities are affected by the variation in transistor current

gain beta (hfe) , by temperature changes, or by supply voltage variation. The best bias circuits strive to keep

Vce and Ic constant even though beta, ICBO, Vbe and Vcc changes from part to part or with time or with

temperature. See Fig (a) below which shows BJT output characteristics between CE voltage Vce and collector

current Ic. For a Common emitter BJT with emitter grounded, the load line represents the equation

VCC – IcRc – Vce =0. The slope of the curve is given by (-1/Rc) where Rc is the collector load.

It is necessary to bias transistor in middle of active region as shown in Q. If it is biased near

saturation (Qh) or cutoff region (Ql), it might happen that small variation in parameters like temperature, hfe or

supply voltage, the transistor may shift in to saturation or cutoff region. To avoid such condition proper biasingwith stability is necessary. In addition, Q point should be in middle such that the “head room” (VCC – Vce)

and the “leg room” (VCE – VCEsat) is nearly equal and output signal may swing on positive and negative side

of Q point, in equal amplitude without driving the BJT in cutoff or saturation.

How stability is improved by adding resistor in Emitter (Re)?

In CE amplifier, emitter is common terminal between input and output and is normally grounded. We

first consider circuit shown in Fig 1. The bias current Ib is decided by Vcc, R2 and R3. This base current times

beta (hfe) flows in collector as Ic. So even if manage to keep Ib constant by keeping VCC and Rb constant, any



change in beta will cause a change in Ic and therefore VCE. In our experiment we will change VCC to study the

resultant change in Vce and Ic (Q-point).

The addition of emitter resistance has an effect of negative feedback which reduces gain of the amplifier

but improves the stability. The presence of Re, tends to reduce of destabilizing effect as follows- If Ic tends to

increase due to some reason, say because of increase in temperature, the current Ie in Re increases. This will

increase the voltage drop across Re. Voltage drop across Re opposes the flow of Ib from Vcc & R2 R3 biasing

circuit. Since the opposition will increase, it will reduce Ib. This reduced Ib will cause reduced Ic to flow untilIc will tend to return to its pre-rise value. This way Re tries to reduce the change in Ic, which improves bias

stability by maintaining bias point at constant value. Suppose Ib reduces due to bias voltage Vcc reduction then

Ic will reduce, Ie will reduce and Ie * Re will decrease causing reduced opposition to Vcc R2 R3 source.

Reduced opposition will increase the base current Ib to the extent of original reduction, as much as possible.

Insertion of Re does not fully stabilize the Q point but improves the stability by atleast an order of value.

Case 1: DC fixed biasing

Figure 1 figure 2

Figure 1 &2 shows fixed DC biasing circuit for transistor. Figure 1 is without feedback (Re =0) , and figure 2 is

with feedback with Re=R4=50ohm. Applying KVL in output loop, we obtain load line equation as

VCC-Ic * (Rc+Re) -Vce=0

Or Ic = (VCC/ (Rc+Re) ) - (Vce / (Rc+Re) )

In following procedure steps 1 to 5 gives idea about biasing and steps 7 to 12 give idea about stability.

Procedure:

1.

Set up the circuit as shown in figure with Vcc = 12V. Measure the values of fixed resistors beforehand

and note down.

2. Set the potentiometer at one extreme condition such that R3 is maximum, Ib and Ic are maximum and

VCE is minimum. Note that Vce must be above 1V to ensure that BJT is not in saturation. Measure



Voltage across R2 and calculate Ib and note down. Measure Voltage across Rc and calculate Ic. Measure

VCE and note down both.

3. Now adjust potentiometer to increase VCE by 1 volt approx. and take second reading.

4. Repeat step 3 and 4 and keep recording to get Ib, Ic and Vce.

5. Plot load line based on above equation and plot your Q point readings on the same graph. The graph will

show the locus of Q point with Ib variation.

Now we will study the effect of Vcc variation on Q point.

Set the Q point approximately at the middle of the characteristics or load line by adjusting

potentiometer such that Vce = nearly Vcc/2 and Ic is between 2 to 4 mA (depending upon beta of

your BJT).

6. Now change the supply voltage from 11 V to 15 V in scale of 1V.

7. Keep recording VRC, calculate IC, VCE value.

8. Observe the change in DC biasing point.

9. Insert a Resistor Re=50ohm. As shown in figure2.

10.

Repeat step 7 to 9 and see the change in DC biasing point.

11. Plot Q point i.e. VCE Ic for both Re=0 and Re=50ohm

12. Calculate Instability ratio = [(VCE at Vcc = 15 ) - (VCE at Vcc = 11 )*100] / [ (15-11)] for both Re=0

and Re=50ohm

13. See that insertion of Re reduces the Instability Ratio or improves stability.

Case 2: Voltage divider biasing

Figure 3 Figure 4



The figure shows Voltage divider biasing scheme. Input side can be converted to its Thevenin equivalent.

Where

Vth= VCC*R3/(R2+R3) and Rth= R3||R2

Similarly for figure 4

Vth= VCC*R6(R5+R6) and Rth= R5||R6

Step 1 to 5 gives idea about biasing and step 7 to 12 will give idea about stability.

Procedure:

1. Set up the circuit as shown in figure with Vcc = 12V. Measure the values of fixed resistors beforehand

and note down.

2. Set the potentiometer at one extreme condition such that R3( or R6) is maximum, Ib and Ic are

maximum and VCE is minimum. Measure Voltage across R5 and calculate Ib and note down. Measure

Voltage across Rc and calculate Ic. Measure VCE and note it down.

3.

Now adjust potentiometer to increase VCE by 1 volt approx. and take second reading.

4. Repeat step 3 and 4 and keep recording to get Ib, Ic and Vce.

5.

Plot load line based on above equation and plot your Q point readings on the same graph.

Set the Q point approximately at the middle of the characteristics or load line by adjusting

potentiometer such that Vce = nearly Vcc/2 .

6. Now change the supply voltage from 11 V to 15 V in scale of 1V.

7. Keep recording VRC, calculate IC, VCE value.

8. Observe the change in DC biasing point.

9. Insert a Resistor Re=100ohm. As shown in figure2.

10.

Repeat step 7 to 9 and see the change in DC biasing point.11. Plot VCE->VCC for both Re=0 and Re=100ohm

12. Calculate Instability ratio = [(VCE at Vcc = 15 ) - (VCE at Vcc = 11 )*100] / [ (15-11)] for both Re=0

and Re=50ohm.

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BJT DC Biasing 29 Aug 2014