Basic of FPGA Construction

8/8/2019 Basic of FPGA Construction

1/6

By Gina R. SmithCEO, Owner Brown-Smith Research and Development Laboratory Inc.

Over the last several years, the useo FPGAs has greatly increased inmilitary and commercial prod-ucts. They can be ound in pri-mary and secondary surveillanceradar, satellite communication,automotive, manu acturing, andmany other types o products.While the FPGA developmentprocess is second nature toembedded systems designers

experienced in implementingdigital designs on an FPGA, itcan be con using and di cult orthe rest o us. Good communica-tion is important when technicalleads, supervisors, managers, orsystems engineers inter ace withFPGA designers.

The key to good communica-tion is having an understandingo the development process. Asolid understanding will helpyou comprehend and extractrelevant in ormation or statusreports, de ne schedule tasks,and allocate appropriate re-sources and time. There havebeen many times when myFPGA knowledge has allowedme to detect and correct errors,such as wrong part numbers ormisuse o terms and terminology

ound in requirements and otherdocuments.

Regardless o your inal prod-

uct, FPGA designers must ollowthe same basic process. TheFPGA development stages aredesign, simulation, synthesis,and implementation, as shownin Figure 1 . The design pro-cess involves converting therequirements into a ormat thatrepresents the desired digital

unction(s). Common designormats are schematic capture,

hardware description language(HDL), or a combination o thetwo. While each method has itsadvantages and disadvantages,HDLs generally o er the great-est design lexibility.

Schematic captureSchematic capture, the graphi-cal depiction o a digital design,shows the actual interconnec-tion between each logic gatethat produces the desired output

unction(s). Many o these logic-gate symbols involve proprietaryin ormation making them avail-able to the designer only throughthe speci c vendors componentlibrary. Schematic capture de-signs that mainly consist o pro-

prietary symbols make the designunrecognizable by competitorsFPGA development tools. Theproprietary nature o this typeo design makes it vendor de-pendent, and the entire designprocess must be repeated i adi erent vendor is used.

Examples o schematic cap-ture tools are Viewlogics View-Draw and HDLs EASE. The mainadvantage o schematic captureis that the graphical represen-

tation is easy to understand.However, its major drawback isan increase in cost and time toreproduce a design or di erentvendors due to the designs pro-prietary nature.

HDL methodHardware description languages(HDLs) use code to representdigital unctions. Firmware o tenre ers to the resulting HDL code.HDLs are a common and popular

Figure 1: The FPGA development process can be divided into our unctions: design, synthesis, simulation and imple-mentation.

EE Times-India | January 2008 |eetindia.com

The basics of constructing FPGAIC DESIGN
http://www.eetindia.co.in/http://www.eetindia.co.in/


2/6

approach to FPGA design. You cancreate the source code with anytext editor. Special HDL editorslike CodeWright and Scriptum(a ree HDL text editor by HDLWorks) o ers eatures such asHDL templates and highlightingreserved words not ound in or-

dinary text editors. HDLs can begeneric (supported by multiplesimulation and synthesis toolsets) like Verilog or VHDL (VeryHigh Speed IC HDL), or vendor-speci c like Alteras HardwareDescription Language (AHDL),which is only recognizable byAlteras design tool set.

There are two writing stylesor HDL designs, structural or

behavioral. Structural irmware

is the so tware equivalent o aschematic capture design. Likeschematic capture, structural de-signs instantiates or uses vendor-speci c components to constructthe desired digital unctions. Thistype o HLD rmware is vendor-dependent like its graphicalcounterpart and has the samedisadvantages. Like schematiccapture designs, repeating thedesign process is necessary ordi erent vendors.

Behavioral HDL irmwaredescribes digital unctions ingeneric or abstract terms thatare generally vendor indepen-dent. This provides enough fex-ibility or code reuse in di erentvendors FPGAs so little or nocode modi ication is required.Advantages o behavioral designsare its lexibility and time andcost-savings, and it o ers littleto no vendor dependence. For

designs that require vendor spe-ci c resources, such as RAM, onlythose components must change

or di erent vendors.VHDL and Verilog are the most

popular HDL languages. VHDLles consist o three main parts:

library declaration, entity decla-ration, and architecture section.While not required by VHDL, anoptional heading section shouldbe included. This section shouldcontain pertinent in ormation,such as the designers name,

ilename, a brie summary o the code, and a revision history.Listing 1 shows an example o

a VHDL les behavior. BecauseHDLs are similar to so tware,

irmware designers should ol-low some o so tware develop-ment rules.

HDL guidelines1. Use comments to provide

code clarity.2. Indicate active low signals by

n, _n, _b, * at the end o thename.

3. Signal names should be rela-tively short but descriptive.

For example: A good signal name would

be CEn or an active low chipenable.

A bad signal name would beactive_low_chip_enable.

Use underscores in namedescription or clarity.

Synchronize signals to changeon a clock edge.

Process, routes, modules, and

so orth, should per orm asingle unction. Use ormatting, such as tabs

and spaces, to provide read-ability o code.

Include a header section oreach ile or module. Sug-gestive header in ormationdesigners name, le descrip-tion, and revision or historyrecord.

VHDL syntax rulesNow or some VHDL speci cs,including data types: Std_logic can have values o

high 1, low 0, unknown X, un-

initialized U, high impedanceZ, weak unknown W, weak 0 L,weak 1 H, and dont care - torepresent a single data bit.

Std_logic_vector can havethe same values as std_logic;however it represents mul-tiple bits.

A bit can only have a value o high 1 or low 0, and it repre-sents one data bit.

Boolean represents true oralse.

Comments are denoted bydouble dash marks .

Comments continue a ter until a carriage return.

Each statement ends with asemicolon ; .

VHDL is not case sensitive. No speci ic ormat is re-

quired. Reserved words aren't valid

signal names.

Signal names must start witha letter; numbers are notacceptable.

Library declaration The library declaration is the rstsection in the source le. This iswhere you place the library andpackage call-out statements.Libraries and packages de neand store components, de nesignal types, unctions, proce-dures, and so orth. Packages andlibraries are standardized, such asthe IEEE library, and de ned bya user (designer) or vendor. TheIEEE library o ers several pack-

ages, such as standard, textio, andstd_logic_1164. Each o thesepackages de nes various types,attributes, procedures, les, andso on. Heres an abbreviated listo selected IEEE packages: standard de nes types (such

as boolean, bit, time, andinteger), subtypes (such asnatural and positive), and theattribute oreign.

textio package de nes types(such as line and text), les(such as input and output),and procedures (such as read,readline write, and writeline).

Std_logic_1164 package de-nes types (such as std_ulogic

and std_ulogic_vector) andunctions (such as nand, and,

or, nor).

The work library serves as aplace to add or delete designs.

Designs stored in the work libraryget analyzed during synthesisand simulation. Various toolshandle libraries in di erent ways. There ore, users should consultthe tools documentation or cor-rect use. To use whats in a libraryor package, the library must bemade visible by using the key-words Library and Use clause. The IEEE std_logic_1164 packagecontains the types used in Listing1. There ore, the LIBRARY IEEE;statement makes it visible andUSE IEEE.std_logic_1164.all; tellsthe tools to use all the contents inthe std_logic_1164 package.

Figure 2: Multiple source iles are created or each unction and are interconnected through a hierarchicalile structure.

eetindia.com | January 2008 | EE Times-India


3/6

When a designer has speci cconstants, ormulas, processes,and procedures that are used bymultiple modules or submoduleswithin their design, he or she cancreate a custom package. By do-ing this, the unctions in the user-de ined package can be shared

with other designers and projects.A user-de ined library/packageis an easy way to repeatedly usespeci c HDL elements in multiple

les with the luxury o only de n-ing its elements once. Assuming adesigner creates a package calledmy_package and stores this pack-age in the library called Test, the

ollowing command would makethe package visible, thereby allow-ing its contents to be used in the

source le.LIBRARY Test;USE Test.my_package.ALL;

User/designer-de ned pack-ages are similar to those suppliesby vendors, such as Xilinx, whosepackages contain elements suchas RAMs, counters, and bu ers.Xilinxs vcomponents packagecontains constants, attributes,types, and components that be-come available once the libraryand package are visible to thedesign. The package containscomponents like AND3, whichis a three-input AND gate, andNAND3, a three-input NANDgate. The vcomponent packageprovides timing in ormation, theI/O port names (used to instan-tiate components in design),and other in ormation used bysynthesis and simulation tools.

The vendors package becomesvisible in the same manner asthe standard and user-de inedlibraries. To use the elements inXilinxs vcomponent package,designers must make the libraryvisible. For example, the ollow-ing command makes the Xilinxlibrary with vcomponent packagevisible to the design:

LIBRARY Xilinx;USE Xilinx.vcomponents.ALL;

Once all the libraries andpackages are visible, this sectionis complete.

Entity declaration The entity declaration sectionimmediately ollows the librarydeclaration. Each entity has anassigned name; Monitor is the

entity name o the VHLD code inListing 1. Just as the library decla-ration section makes libraries andpackages visible to the design,the entity section makes the I/Osvisible to other source les andthe design and can represent theI/Os as physical FPGA pins. VHDLdesigns can contain one source

le or a hierarchy o multiple les.Hierarchical le structures consisto several les connected throughthe signals declared in their enti-ties. Figure 2 shows a simpli edhierarchical le structure or ahome security system.

On the other hand, i the de-sign is only one le, the top-levelentity declaration de nes all o the I/O that represents physicalFPGA pins. All I/O signals de nedin this section must have uniquenames, indicated signal direction(input or output), and number o bits reserved or the signal. From

Listing 1, reset is an input, onlyone data-bit wide and is a std_logic data type. The keyword END

ollowed by the entitys namesigni es the end o the entity. Allentities must be associated withan architecture section.

Architecture section The architecture section, whichcontains the circuit description,is the body o the VHDL sourcecode. The libraries, packages, andsignals work together to developthe desired unctions. Like the en-tity, each architecture must havean assigned name. The ormat or

declaring the architecture is thereserved word Architecture ol-lowed by its name Door_monitor,then the reserved word O , thenthe entitys name Monitor. Signals

not de ned in the entity sectionare de ned in this section. The signal assignment ormat

consists o the reserved word Sig-nal ollowed by the signal nameand then the data type (such asstd_logic and std_logic_vector),as in Listing 1. Like names de nedin the entity, each signal namemust be unique and have adata type. This section is also

or declaring constants, variables,and other data types.

Signals can be thought o aswires used to connect unctionsand store values. A ter de ning allthe designs signals, the designeris ready to develop the code thatdescribes the desired unctions. The reserved word Begin signi esthe start o the next subsection,which combines the concur-rent and sequential statements.Concurrent statements updateor change value at anytime. The

signal assignment immediatelyollowing the rst reserved wordBEGIN in Listing 1 is an exampleo a concurrent statement. Se-quential statements updateor change value when signalsin the sensitivity list (see List-ing 1) change state. Signals inprocesses are sequential state-ments. Most processes have asensitivity list, process name, andcircuit description (HDL code) be-tween reserve words BEGIN andEND PROCESS. The process nameprecedes the reserved wordProcess, and the sensitivity list isenclosed in the parenthesis.

Listing 1 contains two pro-cesses. The irst is checking_door_status, which has a sen-sitivity list that contains threesignals: reset, clock_20mhz, and

reset_start_timer. The secondprocess is set_alarm_enable,which only has two signals, resetand clock_20mhz, in its sensitivitylist. Signals in a process that up-date or change ollowing a clock edge are called synchronoussignals. Start_500ns_timer in thechecking_door_status process isan example o a synchronoussignal. The architecture sectioncloses by using the reservedword END ollowed by thearchitectures name.

Simulate or synthesizeOne or more designers maybe responsible or a design. Anumber o actors infuence thenumbers designers needed,such as design complexity andsize; the designers skill level;and the designers scheduleand availability. Regardless o the number o designers, a ter

the design is completed, thereare a couple o options. He orshe may choose to simulate orsynthesize the design. Thereisnt a hard and ast rule stat-ing you must simulate be oresynthesis. There are advantagesto each option, and designersmust determine which step ismost bene icial. In act, theremay be times when a designerdecided to simulate ollowingthe completion o the initial de-sign while another time decideto synthesize. Each option letsthe designer detect and correctdi erent types o errors.

Figure 3: The design serves as the input to the synthesis process, resulting in a netlist that is used as the input to theplace and route or implementation tool.



4/6

Simulating the design priorto synthesis allows logic errorsand design faws to be resolvedearly in the development process.Synthesizing lets the designerresolve synthesis errors prior tologic errors and design faws. Ide-ally, the designer would per orm

minimal simulation, leaving themore stringent testing to a codetester. The original code designershouldnt test his own codebecause hes less likely to detectspeci c design faws such as:1. Misinterpretation o require-

ments; i the designer misun-derstood a requirement, he orshe will test and evaluate thedesign based on that misun-derstanding.

2. Its more di cult or a personto nd his own errors. A third-party generally tests the codemore rigorously and is moreeager to nd bugs than theoriginal designer.

Regardless o who per ormsthe simulations, the process is thesame. For the sake o this article,were going to assume the testingis per ormed by a code tester, notthe original designer.

Simulation is the act o veri y-ing the HDL or graphical digitaldesigns prior to actual hard-ware validation. The circuitsinput-signal characteristics aredescribed in HDL or in graphicalterms that are then applied tothe design. This lets the codetester observe the outputs be-havior. It may be necessary tomodi y the source code duringsimulation to resolve any discrep-

ancies, bugs, or errors.Simulation inputs or stimulusare inputs that mimic realisticcircuit I/Os. Stimulus orces thecircuit to operate under variousconditions and states. The great-est bene t o stimulus is the abil-ity to apply a wide range o bothvalid and invalid input-signalcharacteristics, test circuit limits,vary signal parameters (such aspulse width and requency), andobserve output behavior withoutdamaging hardware. Stimulus canbe applied to the design in eitherHDL or graphical/wave orm or-mat. Generally, when a tester or de-

signer speaks o a testbench, hesre erring to applying stimulus to

the design in the orm o HDL.Listing 2 shows an example o aVHDL stimulus or testbench le.

The testbench looks similar tothe actual VHDL design. Hence,the same VHDL language rulesapply. Each tester has a style inwhich he or she writes a test-bench, which can be automaticor manual and can use external

les or simulation and analysis.Automatic testbenches can ana-lyze simulation data and providea nal result, output error data,or other important in ormation.Manual testbenches require thetester to manually analyze the

data. An example o an automatictestbench would be one that

reads valid data rom an externalle, compares it with simulationdata, and writes the nal pass/ ailresults to an external le. External

iles are use ul or duplicatingevents seen on actual hardware.

Data can be taken rom thehardware, stored in an external

le, then read into a testbench andused as the input stimulus. Manysimulators accept both wave ormand testbenches as input stimu-lus; consult your simulator usersmanual or acceptable ormats.Some popular simulators are Men-tor Graphics ModelSim, AldecsRiviera, and Alteras Quantus II.

There are three levels o simu-lation: register trans er level

(RTL), unctional, and gate level.Each occurs at a speci c placein the development process.RTL ollows the design stage;

unctional ollows synthesis anda ter implementation is com-pleted the gate level simulation.Generally, the stimulus devel-oped or the RTL simulation isreusable without modi cation oreach level o simulation.

Simulation The initial simulation per ormedimmediately a ter the designstage is the RTL simulation. This involves directly applying

Listing 1: The various sources o a VHDL source le are illustrated here.



5/6

the stimulus to the design. RTLsimulation only lets designersveri y that the logic is correct.No realistic timing in ormationis available to the simulator. There ore, no serious timingexists or the design. The onlytiming in ormation that canbe available to the simulator istester generated. Much like in-

put stimulus, a tester can insertsimulated or injected delaysinto the original HDL design, asin Listing 1. Most synthesis tools(discussed later) will ignorethese simulated delays.

Applying test stimulus tothe synthesized or optimizednetlist produced by a synthesistool is a unctional simulation.Optimized netlists produced bynon-vendors apply estimateddelays that produce more realis-tic simulation output results. Themain bene t rom per orming

unctional simulation is that itlets the tester veri y that the syn-

thesis process hasnt changedthe design. Many, but not all,third-party simulation tools ac-cept post-synthesis netlists.

Gate-level simulation involvesapplying stimulus to the netlistcreated by the implementationprocess. All internal timing de-lays are included in this netlist,which provides the tester with

the most accurate design out-put. Again, many, but not all,third-party simulation tools canper orm gate simulation.

Ideally, each level o simula-tion is per ormed at the ap-propriate development stage.However, i this isnt possible,its recommended that at aminimum, RTL is per ormed. Asthis simulation is per ormed, itsnormal or the original designto require modi ications dueto logic errors. Each simulationlevel o ers various bene its.RTL uncovers logic errors, the

unctional level veri es that the

pre- and post-synthesis designsare equivalent, and the gate leveluncovers timing errors.

Some bene its to spendingsu cient time generating qualitytestbenches and simulation arereduced time troubleshootinghardware (generally, cheaperto testbench troubleshoot thanhardware troubleshoot) and a de-

crease in the chance o damaginghardware resulting in a aster timeto market. Opting to omit simula-tion and testbenching will gener-ally cost the project additionaltime and money. Lab testingrequires collecting and setting uptest equipment (such as a logicanalyzer and oscilloscope) anddepending on the equipmentused, the designer may have alimited number o signals avail-able. Or, the desired signal mustbe made available on an output,which requires additional time.Simulation is valuable and as aguideline, at least 2X the number

o hours spent writing the codeshould be spent developing andtesting the code.

Design synthesisWhile some designers pre erto proceed directly to simula-tion, I pre er to synthesize the

design. Synthesis is the processthat reduces and optimizes theHDL or graphical design logic.Some third-party synthesis toolsare available as a part o theFPGA vendors complete devel-opment package. SynplicitysSynpli y and Mentor GraphicsLeonardoSpectrum, PrecisionRTL, and Precision Physical areexamples o third-party synthe-sis tools. Xilinx o ers ISE Project

Foundation, which is a com-plete development applicationthat includes a synthesis tool.Altera has Quartus II IntegratedSynthesis, QIS.

Although some FPGA ven-dors o er synthesis, they stillrecommend using a third-partyssynthesis tools. The synthesistool must be set up prior to ac-tually synthesizing the design.Synplicitys Synpli y goes througha common set-up process, as it in-volves providing the design les(completed during design stage)and in ormation about the FPGA.FPGA in ormation includes thevendors name, the speci c partor amily, the package type, andthe speed. The synthesis processtakes this in ormation and theuser-de ined constraints andproduces the output netlist. Aconstraints le speci es in orma-tion like the critical signal paths

and clock speeds. A ter complet-ing set-up, synthesis can begin.General synthesis fow or toolslike Synplicitys Synpli y involvesthree steps, creating structuralelement, optimizing, and map-ping. Figure 3 shows a synthesisfow diagram.

The rst step in the synthesisprocess is to take the HDL designand compile it into structuralelements. This means that theHDL design is technology in-dependent. Synpli y graphicallyrepresents this step as the RTLSchematic View, viewable inSynpli y. The next step involves

Listing 2: VHDL Testbench is used to provide stimulus to the VHDL source code.



6/6

optimizing the design, making itsmaller and aster by removingunnecessary logic and allowingsignals to arrive at the inputsor output aster. The goal o the optimizing process is themake the design per orm betterwithout changing the circuits

unctions. The nal step in the synthesis

process involves mapping orassociating the design to thevendor speci ic architecture. The mapping process takes thedesign and maps or connectsit using the architecture o thespeci c vendor. This means thatthe design connects to vendor-speci ic components such aslook-up tables and registers.

The optimized netlist is theoutput o the synthesis process. This netlist may be produced inone o several ormats. Edi is ageneral netlist ormat acceptedby most implementation tools,while .xn ormat is speci c toXilinx and is only recognized byXilinxs implementation.

In addition to the optimizednetlist, many synthesis tools likeSynpli y will produce a netlist orgate-level simulation and otherreport les. Stimulus applied tothis netlist instead o the originalHDL design produces the unc-tional-level simulation, whichlets the designer veri y that thesynthesis process hasnt changedthe designs unctions. At thispoint, synthesis is complete andready or the implementationprocess. Each FPGA vendor has itsown implementation tool, suchas Xilinxs Project Navigator and

Alteras Quartus IIs.

Design implementation The inal stage in the FPGAdevelopment process is thedesign implementation, alsoknown as place and route (PAR).I the FPGA vendor has a com-plete development tool, mean-ing it can per orm synthesis,

and the design is synthesizedusing this tool, little or no set-up is required or PAR. However,i a third-party synthesis tool isused, the implementation toolmust be set up, which involvesdirecting the PAR tool to thesynthesized netlist and possiblya constraint ile. The constraint

ile contains in ormation suchas maximum or minimum tim-ing delays or selected signal(s)

and I/O pin assignments.Pin assignments can be auto-matic (per ormed by the tool) ormanual (dictated by the designer).Automatic pin assignment isgenerally the best option or newdesigns, as it lets the tool more e -

ectively route the design withouthaving xed pin assignments. Itmay be necessary to manuallyassign signals to speci c pins toachieve easy board routing, toprovide the minimum signal route

or timing-critical signals, or becompatible with legacy designs.

There are numerous rea-sons why manual pin assign-ments would be necessary.But regardless o the reason,the designer must make thisin ormation available to the PARtool, which is done by creatinga user constraint ile thats usedby the PAR tool. A ter complet-ing setup, the PAR process can

begin. Each PAR tool may have

a slightly di erent approach todesign implementation, so con-sult your PAR documentation.Xilinxs Foundation or ProjectNavigator per orms designimplementation in three steps,translate, it, and generate pro-gramming ile.

Step one, called translate,involves veri ying that the syn-thesized netlist is consistent withthe selected FPGA architectureand there are no inconsistenciesin the constraint le. Inconsisten-cies would consist o assigningtwo di erent signals to the samepin, assigning a pin to a poweror ground pin, or trying to assigna non-existing design signal toa pin. I the design ails either

check, the translate step will ailand the implementation processwill be stopped.

Translate errors must be cor-rected and the translation stepmust be error ree be ore advanc-ing to step two, which is the tstage. This step involves takingthe constraints ile and netlistand distributing the design logicin the selected FPGA. I the de-sign is too large or requires moreresources or available logic thanthe selected device o ers, the

tter will ail and halt the imple-mentation process. To correct thistype o error, replace the currentFPGA with a larger one and re-synthesize, and repeat PAR or thedesign. A success ul t stage isnecessary to proceed to generatethe programming le stage.

All timing in ormation is avail-able and many PAR tools willprovide the required les neces-

sary or the simulator to per orm

a timing simulation. The nal stepis to generate the programming

le, which can be stored in fashmemory, PROMs, or directly pro-gramming into the FPGA. JTAGand third-party programmers likeData I/O are two programmingmethods used to store the pro-

gramming le in memory. The ap-propriate ormat depends on theFPGA vendor, the programmingmethod, and the device used tohold the programming.

There are various output or-mats; consult your documentation

or the correct one. In additionto the implementation processcreating the programming le,there are several output report

iles created, such as a pad ile.

The pad le contains in ormationsuch as signal pin assignment, partnumber, and part speed.

Beyond the basics This article gives some basic ex-amples o the FPGA developmentprocess, so a new embedded sys-tems designer, manager, techni-cal lead rom other disciplines, orsomeone wanting to diversi y hisor her skills can understand whatit takes to develop and imple-ment a digital design in a FPGA. The generic process providedhere will vary depending on theFPGA tools since each vendormay per orm some o these tasksin a slight di erent manner.

A good resource or urtheringyour knowledge isEssential VHDL RTL Synthesis Done Right(SundarRajan, F.E. Compton Co, 1998).

Email Send inquiry

http://www.xess.com/prod013.php3http://www.xess.com/prod013.php3http://www.eetindia.co.in/article/email_friend.php3?article_id=8800498846&type=TA&cat_id=1800001&back_url=%2Farticle%2Farticle_content.php3%3Fin_param%3D8800498846_1800001_TA_9e56fe0c%26http://www.eetindia.co.in/article/email_friend.php3?article_id=8800498846&type=TA&cat_id=1800001&back_url=%2Farticle%2Farticle_content.php3%3Fin_param%3D8800498846_1800001_TA_9e56fe0c%26http://www.eetindia.co.in/inquiry/send_inquiry.php3?article_id=8800498846&type=TA&title=The+basics+of+constructing+FPGAs&cat_id=1800001http://www.eetindia.co.in/http://www.eetindia.co.in/http://www.eetindia.co.in/inquiry/send_inquiry.php3?article_id=8800498846&type=TA&title=The+basics+of+constructing+FPGAs&cat_id=1800001http://www.eetindia.co.in/article/email_friend.php3?article_id=8800498846&type=TA&cat_id=1800001&back_url=%2Farticle%2Farticle_content.php3%3Fin_param%3D8800498846_1800001_TA_9e56fe0c%26http://www.xess.com/prod013.php3http://www.xess.com/prod013.php3

Documents

Basic of FPGA Construction