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8/9/2019 Bakir Chapter5
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Chapter 5 The MOSFET
Metal Oxide SemiconductorField Effect Transistor
5.1 MOS Structure
5.2 MOSFET Basics & Device Physics5.3 MOSFET Circuit Models
5.4 SPICE Analysis
Literature: Pierret, Chapter 16&17, page 563-637Jaeger, Blalock, Chapter 4, page 145-202
Acknowledgement Oliver Brand for slides
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MOSFET Device StructureMetal Oxide Semiconductor Field Effect Transistor
Most important devicestructure in VLSI
First MOSFET: 1960
4-terminal device: gate,
substrate, drain, source
Basic Device Principle(n-channelMOSFET)
Positive gate voltage depletesholes underneath the gate oxide
Vg> V
T(threshold voltage): large electron concentration (inversion)
underneath gate oxide: np> pp0
As a result, a conducting channelis formed between source anddrain, resulting in a current flow in case VD!0
Switching Device: ON: Vg> VT; OFF: Vg< VT
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5.1 MOS Capacitor
5.1.1 Band Diagram
5.1.2 Electrostatics
5.1.3 The Si-SiO2MOS Capacitor
Literature: Pierret, Chapter 16, page 563-599
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MOS Capacitor
Pierret, Fig. 17.1
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5.1.1 Energy Band Diagram
Assumptions:
Thick metallic gate, i.e. equipotential region
Perfect insulator, i.e. no dc current
No charges in oxide or interface
Uniformly doped semiconductor
Sufficiently thick semiconductor having field-free region close to
contact
One-dimensional structure
Flat-band condition: M= S= + (EC EF)FB
Work function : Energy difference between vacuum level E0and Fermi Energy EF
Electron affinity : Energy difference between vacuum level E0
and conduction band energy EC
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Band Structure of Individual Materials
Pierret, Fig. 16.2
N-Type
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Work Function & Electron Affinity
E0 vacuum level
!M metal work function (fundamental property of particular metal)= 4.28 eV for Al = 4.33 eV for Ti = 4.50 eV for Cr= 4.55 eV for W = 5.10 eV for Au = 5.65 eV for Pt
!S semiconductor work function (depends on material & doping)
" electron affinity = E0 EC(fundamental property of semiconductor)= 4.03 eV for Si = 4.07 eV for GaAs =4.00 eV for Ge
Pierret, Fig. 16.2
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MOS Capacitor Equilibrium Energy Band Diagram
Pierret, Fig. 16.3
No band bending
under equilibrium,
because M= S!
N-Type
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MOS CapacitorBiased Band Diagram
Bias Vgapplied to gate electrode
Fermi energy:
Note:
EFis constant inside thesemiconductorbecause there isno dc carrier flow through theinsulator
No band bending inside themetalbecause it is considered anequipotential region
Constant energy slope insideinsulatorbecause there are nocharges inside it and thus theelectric field is constant across it
Pierret, Fig. 16.5
EF(metal) "EF(semicon.) = "qVg
N-Type Semiconductor
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MOS Capacitor (N-Type)
Biasing Regions I
Accumulation
Vg> 0
Depletion
small Vg< 0
Pierret, Fig. 16.5
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MOS Capacitor (N-Type)
Biasing Regions II
Onset of Inversion
Vg= VT
Inversion
Vg< VT
Pierret, Fig. 16.5
Ei,surface
!Ei,bulk
=2 EF!E
i,bulk"#
$%
ps =
nie
(Ei,surface
!EF)/kT
= nie
(EF!E
i,bulk)/kT
= nbulk
=ND
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MOS Capacitor (P-Type) Biasing Regions
Pierret, Fig. 16.6
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5.1.2 MOS Capacitor Electrostatics
Potential !(x) inside semiconductor
Surface potential !s
Fermi potential !F
!(x) = "1
qE
i(x)"E
i,bulk#$
%&
!s =
1
q
Ei,bulk
"Ei,surface
#$
%&
!F"
1
qE
i,bulk#E
F$%
&'
> 0 for p type
< 0 for n type
()*
!F =
+
kT
qln
NA
ni
$
%+
&
',for p type
#kT
qln
ND
ni
$
%+
&
', for n type
(
)--
*
--
!s= 2 !Fat onset of inversion!s> 2 !Fin inversion0 < !s< 2 !Fin depletion
Pierret, Fig. 16.7
P-Type
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MOS Capacitor Electrostatics Depletion Region (P-Type Semiconductor)
Assumptions:
P-type semiconductor
Constant charge densityin depletion region:#= q NAfor 0 "x "W
Electric Field(boundary condition: $(W) = 0):
Electrostatic Potential(boundary condition: !(W) =0):
d!
dx=
"
Ks
!0
# $qN
A
Ks
!0
% !(x) =qN
A
Ks
!0
(W $ x)
! = "#$ % $(x) =qN
A
2Ks!0
(W " x)2
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MOS Capacitor Electrostatics Depletion Region (cont.)
Surface Potential!s= !(0):
Width of Depletion RegionW and Maximum Width at Onsetof InversionWT:
How does !sdepend on Vgin depletion mode?
!s =
qNA
2Ks"0
W2
W =2K
s!0
qNA
"s
WT =2K
s
!0
qNA
2"F =4K
s
!0
kT
q2NA
lnN
A
ni
#
$%
&
'(
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MOS Capacitor Electrostatics Gate Voltage Relationship
How does !sdepend on Vgin depletion mode?
No charges inside the oxide with thickness x0, i.e. #oxide= 0, yields
The electric field inside the oxide can be obtained from the
boundary condition stating that the dielectric displacementDat the oxide-semiconductor interface must be continuous:
Vg ="#semi
=#s
!"#
+"#oxide =#s +"#oxide
d"oxidedx
=#oxideKo"0
=0 $ "oxide =%&'oxide =const.
('oxide = "oxidedx =x0"oxide%x0
0
)
Doxide =Dsemi,x=0 " #oxide =
Ks
Ko#semi
Ks= 11.8 for SiKo= 3.9 for SiO2
EFsEFm
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MOS Capacitor Electrostatics Gate Voltage Relationship (cont.)
Resulting in a gate voltage Vgin the depletion region
with the electric field at the semiconductor surface
Vg ="s +KsKo
x0#semi(0)
Vg ="s +KsKo
x02qNAKs#0
"s
"semi(0)=
qNA
Ks"0 W=
qNA
Ks"0
2Ks"0
qNA#s
=
2qNAKs"0
#s
0 " #s " 2 #F
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MOS CapacitorGate Voltage Vgvs.
Surface Potential !s
Pierret, Fig. 16.10
Depletion InversionAccum.
Surface potential is
rather rapidly varying
with Vgin the depletion
region, but not in theaccumulation or
inversion region
In the accumulation and
inversion regions,
changes in the appliedvoltage are dropped
almost totally across the
oxide
P-Type
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5.1.3 Si-SiO2MOS-C Work Function Difference
Metal-SiO2-Si is the mostextensively studied MOScapacitor
For commonly used metalelectrodes (e.g. polysilicon andaluminum), the work function
difference is not zero:
The work function differenceresults in a band bending in theSi and SiO2even in equilibrium,
i.e. Vg= 0 In order to reach flat-band
conditions, the so called flat-band voltage VFBhas to beapplied to the gate: VFB= MS
"MS = q#MS ="M$ "S % 0
Sze, Fig. 6.8
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Si-SiO2MOS Capacitor Work Function Difference
Sze, Fig. 6.9
BeforeContact
AfterContact
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Si-SiO2MOS Capacitor Interface Traps and Oxide Charges
In addition to the work function
difference, the MOS capacitor is
affected by charges in the oxide
and traps at the Si-SiO2
interface
Types of interface traps and
oxide charges:
Interface-trapped charges Qit
Fixed oxide charges Qf Oxide-trapped charges Qot
Mobile ionic charges Qm
Pierret, Fig. 18.4
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Si-SiO2MOS Capacitor Oxide Charges and Flat-Band Voltage
Influence of charges on the flat-band voltage depends onlocation of charges within theoxide:
Minimal influence at themetal-SiO2interface
Maximal influence at the Si-SiO2interface
Often, the flat band voltage is
expressed by the effective oxidecharges
VFB ="1
Co
1
x0x #(x) dx
0
xo
$%
&
''
(
)
**
Sze, Fig. 6.12
VFB ="MS#Qf+Qm +Qot
Cowith e.g. Qm =
1
x0x $m(x) dx
0
xo
%
(a)Ideal MOS-C
(b)Parallel shift due to oxide charges
(c)Slope change due to interface-trapped charges
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5.2 MOSFET Device Characteristics
5.2.1 Qualitative Theory of Operation
5.2.2 Derivation of IV Characteristic
Long-Channel MOSFET: Square-Law Theory
5.2.3 Threshold Voltage
Workfunction Difference
Oxide Charges
5.2.4 MOSFET Types and Circuit Symbols
Literature: Pierret, Chapter 17.1-17.2, page 611-630
(for VT: Pierret, Chapter 18, page 645-681)
Jaeger, Blalock, Chapter 4.2-4.4, page 148-165
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N-Channel MOSFET Device Structure
Pierret, Fig. 17.1
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N-Channel MOSFET
Device Operation
Vg< VT: Depletion (or Accumulation)
No conductive path betweensource S and drain D
Drain current ID= 0 for all VD> 0
Vg!VT: Inversion
Conductive channel (n-type)
between source S and drain D
Drain current ID> 0 for all VD> 0
Open Question:
ID(VD) Characteristic?
Jaeger, Blalock, Fig. 4.5
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5.2.1 MOSFET
Qualitative TheoryID(VD) Characteristic
Sze, Fig. 6.17
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MOSFET Linear Regime
Linear Regime: Vg!VTand VD Vg Width of and carrier concentration in
the n-type inversion layer onlydepend on Vg(and not on VD), i.e.are constant along the length L ofthe channel
As a result, the channel resistanceRchanneldoes not depend on VD, butonly on Vg
For a given Vg, IDincreases linearly
with VD Rchanneldecreases with increasing
Vg, thus the slope of IDvs. VDincreases with increasing Vg
ID =R
channel
!1VD
Neamen, Fig. 11.40
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MOSFET Non-Linear Regime
Non-Linear RegimeVg!VTand VD< VD,sat
Width of and carrier concentration in then-type inversion layer depend on Vg
andVD, i.e. are notconstant along thelength L of the channel
As a result, the channel resistanceRchannelincreases with increasing VD;effective voltage drop between gate andchannel is reduced towards the drain
Leveling-off of ID(VD) characteristic Note: Jaeger/Blalock call the linear/
nonlinear regime the triode region
Neamen, Fig. 11.40
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MOSFET Pinch-Off Point
Pinch-Off PointVg!VTand VD= VD,sat
The voltage applied across the MOScapacitor at the edge of the drain
#V = Vg VD,satis just enough to reachthe onset of inversion
This is known as the pinch-off point
VTis the threshold voltage (the voltageto achieve the onset of inversion) forVD= 0
Neamen, Fig. 11.40
dIDdVD VD=VD,sat
= 0 with VD,sat = Vg "VT
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MOSFET Saturation Regime
Saturation RegimeVg!VTand VD!VD,sat
Pinched-off portion of the channel widens(#L in Pierret, Fig. 17.2); the pinched-off
region is depleted, i.e. it has few carriersand thus a low conductance
As a result, most of the drain voltage inexcess of VD,satis dropped across a small#L:ID= const. for VD$VD,satif #L L(long channel approximation)
At the pinch-off point, the carriers areinjected into the depletion region and areswept by the strong electric field to thedrain contact
Neamen, Fig. 11.40
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5.2.2 MOSFET IV Characteristic
Assumption: N-channel MOSFET Drift current dominating in channel
Jn
! Jny
! "qnn#
y= +q
nn d$dy
Carrier mobility in
channel %n!%n(bulk)
! = "#$
Note: %nand n depend on x and y coordinatePierret, Fig. 17.6
GND
Vg
+ VD
$%
because of
coordinate system
+Jnin y direction
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MOSFET IV Characteristic (cont.)
Current flow is restricted to surface channel
Integrate over the channel length:
ID = J
nydx dz =Z J
nydx
0
xc(y )
!!! ="Zd#
dy"q( ) n(x,y) n(x,y) dx
0
xc(y )
!
$ n(y) Q
n(y)
! "#### $####
Assumption:
!does not depend on xEffectivemobility
Charge in inversionlayer at y [C/cm2]I
D= !Z
n(y) Q
n(y)
d"
dy
IDdy
0
L
! ="Z n(y) Qn(y) d#0
VD
! ="Z n Qnd#0
VD
!
Assumption:n(y) = n
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MOSFET IV Characteristic (cont.)
Assumption: Charges added to the metal electrode after theonset of inversion (Vg$VT) result in added mirror charges in the
inversion layer only, leaving the depletion layer unchanged (seedelta-depletion theory of MOS-C): Square-Law Theory
ID =!
Z n
LQ
nd"
0
VD
#
=?
! "# $#
!Qgate
= "!Qsemi
= "Qn
!Qgate
[C/cm2 ]
!"#
#Co!V
g = C
o
$Co/ A
$
(Vg" V
T) =
Ko%
0
xo
(Vg" V
T)
Qn = !
Ko"0
xo
(Vg! V
T)
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MOSFET IV Characteristic (cont.)
Effective potential drop across the MOS-C along thechannel length L is [Vg !(y)]
Inserting in the drain current equation yields
Qn(y) = !
Ko"0
xo
(Vg!V
T! #(y))
ID =!
Zn
LQ
nd"
0
VD
# =!Z
n
L!K
o$0
xo
(Vg! V
T! ") d"
0
VD
#
ID =Z
n
Co
L (Vg! VT)VD!V
D
2
2
%
&''
(
)**
for 0 "VD"VD,satand Vg$VT
Square-Law Theory
VD,sat
=Vg! V
T
ID,sat
=Z
nC
o
2L (V
g! V
T)2
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MOSFET IV Characteristic Square-Law Theory
ID=
Z nC
o
L(V
g! V
T)V
D!VD
2
2
"
#$$
%
&''
Neamen, Fig. 11.48and Fig. 11.49
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MOSFET IV Characteristic Square-Law Theory
Linear/Non-Linear Regime (Triode Region)0 "VD"VD,sat= Vg VT
Saturation Regime (Pinch-Off Region)
VD> VD,sat= Vg VT
ID=
Z nC
o
L
(Vg! V
T)V
D!V
D
2
2
"
#
$
$
%
&
'
'
ID(Z
nC
o
L(V
g! V
T)V
D"#
%& for VD Vg VT
ID=
Z nC
o
2L(V
g! V
T)2"#
$%
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MOSFET IV Characteristic Square-Law Theory
Jaeger, Blalock, Fig. 4.10
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MOSFET IV Characteristic Linear Regime
NMOS device (n-channel MOSFET) in common-source
configuration operated in linear regime
Example: VT= V
TN= 1 V
Kn= C
O= 250A / V
2
ID !
Z nC
o
L (Vg" VT)VD#$ %&
Ron=
'ID
'VD V
D(0
#
$
))
%
&
**
"1
=Z
nC
o
L(V
g" V
T)
#
$)
%
&*
"1
=Ron(V
g)
Voltage-Controlled Resistor
Jaeger, Blalock,
Fig. 4.7
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MOSFET IV Characteristic
Limitations of Square-Law Theory 1. Depletion layer width depends on Vgand VD, i.e. W =
W(y); the square-law theory assumes that all added
charges are added to the inversion layer; in reality, some
of these charges are added to the depletion layer; thus,
IDis always overestimated in the square-law theory: useBulk-Charge Theoryinstead!
2. The drain current is assumed to be zero for Vg< VT; inreality, a channel exists even for Vg< VT, resulting in a
small sub-threshold current
3. The drain current does not self-saturatein the square-
law (and bulk-charge) theory; the saturation in the pinch-
off portion (VD> VD,sat) of the IV characteristic is
artificiallyconstructed
Use
Charg
e-Sheetor
Exact-Char
getheories
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5.2.3 Threshold Voltage No Work Function Difference
Assuming M= Sand an n-channel MOSFET, the thresholdvoltage is identical to the MOS-C gate voltage at the onset ofinversion (!s= 2 !F)
with the charge per area QB= q NAWTin the depletion regionat the onset of inversion
Similarly, the threshold voltage for a p-channel MOSFETis(QB= + q NDWT)
VT = 2!
F+
Ksxo
Ko
4qNA
Ks"0
!F = 2!
F+
xo
"0Ko
=Co#1
!
qNA
4"0Ks
qNA
!F
=WT
" #$ %$
VT = 2!
F+
qNAW
T
Co
$ 2!F#Q
B
Co
VT =2!
F"K
sxo
Ko
4qND
Ks#0
("!F) =2!
F"Q
B
Co
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Threshold Voltage Work Function Difference !MS
In reality !M!!S, i.e. a voltage!MS= q
-1(!M !S) has to be
applied to the gate to achieve
flat band condition
As a result, the thresholdvoltage is shifted by the work
function difference:
VT ="MS + 2"F #QB
Co
Pierret, Fig. 18.1
n-channel p-channel
&F > 0 < 0
&MS < 0 < 0
QB < 0 > 0
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Threshold Voltage
Work Function Difference!
MS
Pierret, Fig. 18.3
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Threshold Voltage Oxide Charges
With the types of oxide chargesand their charge density
(i) interface-trapped charges Qit,(ii) fixed oxide charges Qf,
(iii) oxide-trapped charges Qot,(iv) mobile ionic charges Qm,
the threshold voltage of theMOSFET becomes
with 0 "cm, cot"1; the charge density Qitof the interface-trappedcharges depends on the surface potential &s
VT ="MS + 2"F #QBCo
#
QfCo
#
Qit("s)
Co#
cmQmCo
#
cotQotCo
Pierret, Fig. 18.4
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Threshold Voltage Adjustment by Implantation
In modern device processing (e.g. n-channel and p-channel
MOSFETs in CMOS processes), the threshold voltage is
adjusted to the desired value by ion implantation, implanting
a controlled number of either boron or phosphorous ions into the
near-surface region of the semiconductor (in the channel region)
Under inversion bias, the additional dopant adds to the chargenear the Si-SiO2interface (with charge density QI) and, thus,
results in a VTshift of the structure:
Depending on the dopant type, both positive (for acceptor atoms,B) and negative (for donor atoms, P) VTshifts are possible
Example: QI= 5 1011cm-3boron, xo= 10 nm yields #VT= +0.23 V
"VT = #QI /Co
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5.2.4 Types of MOSFET
Sze, Fig. 6.19
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MOS TransistorCircuit Symbols
Jaeger, Blalock, Fig. 4.15
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5.3 MOSFET Circuit Models
5.3.1 MOSFET DC Model Square-Law Theory: Model Equations
MOSFET Bias Circuits
Q-Point Analysis
5.3.2 MOSFET Small Signal Model
Y-Parameter Two-Port Network
Small Signal Equivalent Circuit Small Signal Analysis
5.3.3 Comparison MOSFET BJT
5.3.4 Common-Source Amplifier
Literature: Jaeger, Blalock, Chapter 4.6-4.9, page 167-187
Jaeger, Blalock, Chapter 13.8-13.10, page 815-838
Jaeger, Blalock, Chapter 15.4, page 1016-1024
Jaeger, Blalock, Chapter 16.2, page 1049-1063
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5.3.1 DC Models NMOS & Square-Law Theory
Long Channel
Approximation
Short Channel
Approximation
Saturation Region
VGS > VT; VDS > VDsat
Triode Region
VGS > VT; VDS "VDsat
Cut-Off Region
VGS < VT
ID =
Kn
2
(VGS
!VT)2
ID =K
n (V
GS!V
T)V
DS!V
DS
2
2
"
#$$
%
&''
ID = 0
ID =
Kn
2
(VGS
!VT)2(1+ "V
DS)
ID =K
n (V
GS!V
T)V
DS!V
DS
2
2
#
$%%
&
'((
ID = 0
In addition, we assume IG= 0 and IB= 0 (substrate current)
Kn =!
nC
ox(W /L)
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How to Perform Q-Point Analysis?
1. Educated guess: Assume the region ofoperation (most often the saturation region)
2. Use circuit analysis (might require Thvenin
equivalent circuit) to find VGS
3.
Use VGSto calculate ID, and IDto determineVDS(using MOSFET model and KVL)
4. Check the validity of the operation regionassumptions
5.
Change assumptions and analyze again ifnecessary
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Constant Gate-Source Voltage Bias
Voltage dividerbiases gate
terminal
With IG= 0,we find
VGS
= 3 V
R1+ R2is large
to minimize power
supplied by VGG
Assuming biasing in the saturation region, we find
Because VDS= 5 V > VGSVT= 2 V, the MOSFET is in saturation
VT= 1 VKn= 25 "A/V2
Saturation Model : ID =
Kn
2 (VGS!
VT)
2
= 50A
KVL : VDD
= ID
RD+V
DS " V
DS= 5 V
Jaeger, Blalock, Fig. 4.24
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Constant Gate-Source Voltage Bias (cont.)
Q-point is (ID, VDS) = (50 %A, 5 V) at VGS= 3 V
Note: If we know the mode of operation (in this case saturation),we can calculate VGSfrom IDand VDS;
thus, the Q-point is defined by IDand VDSonly
Why is the constant gate-source voltage bias typically NOT
used in practical applications? Obtained Q-point is very sensitive to variations of the
transistor parameters (Kn, VT): IDincreases linearly with Kn
and quadratically on VT
Betterbias circuits: two or four-resistorbias, bias with
current mirror
How would you obtain the above Q-point if '= 0.02 V-1!0?
How would you perform a load-line analysis of the circuit?
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MOSFET Four-Resistor Bias Most general and
important bias method
Advantages:
Feedback circuit
helps stabilize the
Q-point upon variation
of transistorparameters and
temperature
Only single voltage
supply needed
Lets analyze this
circuit&..
Jaeger, Blalock, Fig. 4.27
VT= 1 VKn= 25 "A/V
2
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MOSFET Four-Resistor Bias
Analysis 1.
Assume a region of operation: Saturation
2. Perform circuit analysis to find VGS(a) Find Thevenin equivalent circuit
for gate bias network
(see previous page):
(b) Use KVL and MOSFET model to extract VGSJaeger, Blalock, Fig. 4.28
VEQ
=
R1
R1+R
2
VDD
=4 V
REQ
=
VEQ
VDD
R2
=
R1R
2
R1+R
2
=600 k!
VEQ
= IGR
EQ
=0,because IG =0
!
+ VGS
+ (ID+ I
G)
=ID
,because IG =0
"#$
RS ! V
EQ =V
GS+ I
DR
S
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MOSFET Four-Resistor Bias
Analysis (cont.)
Solve quadratic equation to obtain VGS
yielding VGS= 2.71 V (which would mean cut-off mode) andVGS= 2.66 V
3. Use VGSto calculate ID, and IDto determine VDS
4. Check the validity of the operation region assumptions
ID =
Kn
2(V
GS!V
T)2 = 34.4!A
VDD
= IDR
D+V
DS+ (I
D+ I
G)
=ID,because I
G=0
!"#
RS " V
DS =V
DD ! I
D(R
D+R
S) =6.08V
ID =
Kn
2(V
GS! V
T)2
VEQ
= VGS
+ IDR
S
"
#$
%$VEQ
= VGS
+
KnR
S
2(V
GS! V
T)2
VGS!V
T =1.66V < V
DS = 6.08V " Saturation
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MOSFET Four-Resistor Bias
Analysis (cont.) Resulting Q-point: (ID, VDS) = (34.4 %A, 6.08 V)
Why is the bias point morestabilized compared toconstant VGSbias?
Bias circuit uses negative feedbackto stabilize bias point
If IDrises (because of parameter or temperature variations),VGSmust decrease because VEQis fixed; but a decrease inVGSwill tend to restore (decrease) ID, thus stabilizing theoperating point of the n-channel MOSFET
In the previous circuits it was assumed that the bulk contact isconnected to the grounded source contact(three-terminaldevice); if this is not the case, the analysis become moreinvolved (body effect)
ID =K
n
2(VGS
!VT)2 and VEQ = VGS + IDRS
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And what about PMOS FETs?
PMOS bias techniques
mirror those of NMOS biasexamples
Source of PMOS transistoris drawn on top of devicebecause it is normallyconnected to a potential
higher than the drain For PMOS transistors
the drain current IDisPOSITIVE whencoming OUT of thedrain terminal and
the values for VGSandVDSwill be NEGATIVE
Try to analyze the shownPMOSFET bias circuit
Jaeger, Blalock, Fig. 4.30
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Current Sources
Current sources are widelyused to establish transistor
working points in integrated
circuits
Ideal current source delivers
constant current independentof voltage across the source
How can we use MOSFETs
as effective current sources?
MOS transistors operated in
saturation region (pinched-off
region) deliver constantcurrent for VDS> VDsat
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MOSFET Current Source
How can we achieve output characteristic shown on previous page? Use NMOS transistor operated with constant gate-source voltage
VGS= 3 V (with VGS> VT)
As long as VDC$VDsat, the MOSFET is biased in the pinched-off
region and the
drain current IDremains constant
Assuming VT= 1 V
and Kn
= 25 %A/V2,
we find IDC= ID=
50 %A
ID =
Kn
2(V
GS! V
T)2
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MOSFET Current Mirror
Fundamental building block inelectronic circuit design defining
currents and current ratios (froma single reference current)
Current mirror relies on matched
transistor parameters VT, Kn, 'and W/L(rather than absolute
parameter values) to deliver
IO= IREF
Note: in a CMOS process,
absolute device parameters might
have 20-30% spread, butneighboring transistor parameters
are typically matched to within1-2%; as a result circuit designersrely on ratios rather than absolute
values
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NMOS Current Mirror
Assumption: Transistors M1and M2have matchedparameters VT, Kn, 'and W/L
Gate currents IGof bothtransistors are zero, i.e. thereference current must flow
into drain of M1: IREF= ID1 With VDS1= VGS(> VGS VT),
the transistor M1is insaturation and
Similarly, the current throughM2becomes
IREF
= ID1
=
Kn
2(V
GS! V
T)2(1+ "V
DS1)
IO = I
D2 =
Kn
2(V
GS!V
T)2(1+ "V
DS2) = I
REF
(1+ "VDS2
)
(1+ "VDS1)# I
REF
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NMOS Current Mirror (cont.)
For equal values of VDS, theoutput current mirrors the
reference current
Note: In most applicationsVDS1!VDS2, resulting in a
slight mismatch of the
currents
By designing the transistors
M1and M2with different W/L
ratio, current ratios can be
defined!
IO = I
REF
(W / L)2(1+ !V
DS2)
(W / L)1(1+ !V
DS1)
Jaeger, Blalock, Fig. 16.3
Note: Current mirror is operated between
ground and negative supply; compared to
slide 14 the supply voltage is just shifted
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Multiple Current Mirrors Current mirrors are used to
generate multiple currents from asingle reference current, asneeded in more complex circuits
The displayed circuit generatesthree currents ID2, ID3and ID5fromthe reference current IREF
The resistance R defines the
reference current with
Large resistors R are typicallyrealized with a transistor inintegrated circuit design
R =(V
DD! V
SS)+V
GSP! V
GSN
IREF
ID1
=
Kn
2(V
GSN!V
Tn)2
ID4 =
ID1=
IREF =
Kp
2 (VGSP!
VTp)
2
274 k#
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5.3.2 Small Signal Analysis
Small signal model for FET toanalyze (small signal) ACbehavior of e.g. common-source amplifier
DC voltages/currents (allcapital letters) superimposed
by AC currents/voltage (allsmall letters)
Small signal model based ony-parameter two-port network(expressing currents as afunction of the voltages)
vGS
=VGS
+ vgs v
DS =V
DS+ v
ds
iG = I
G+ i
g i
D = I
D+ i
d
ig =y
11vgs+ y
12vds
id =y
21vgs+ y
22vds
ig
id
!
"##
$
%&& =
y11
y12
y21
y22
!
"##
$
%&&v
gs
vds
!
"##
$
%&&
Jaeger, Blalock, Fig. 13.21
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Y-Parameter Definition (cont)
Y-parameters depend on the DC working point (Q-point) of theMOSFET and have units of ['-1]
Y-parameters are defined as partial derivatives of complete portvariables
Derivatives are evaluated from the large-signal model
equations, e.g. in the saturation region(vDS$vGS VTand iG= 0)
y11
=
!iG
!vGSQ"point
#!I
G
!VGSQ"point
y12
=
!iG
!vDSQ"point
#!I
G
!VDSQ"point
y21
=
!iD
!vGSQ"point
#!I
D
!VGSQ"point
y22
=
!iD
!vDSQ"point
#!I
D
!VDSQ"point
ID =
Kn
2(V
GS! V
T)2 with K
n =!
nC
ox(W / L)
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Y-Parameter Definition (cont.) Saturation Mode
Long- Channel (!= 0) Short - Channel (! !0)y11
= 0 = 0
y12
= 0 = 0
y21= g
m =K
n(V
GS"V
T) =K
n(V
GS" V
T)(1+ !V
DS) =
2 ID
VGS
" VT
y22 =
1
ro
= 0 =! Kn2(V
GS"V
T)2 = ! ID
1+ !VDS
Jaeger, Blalock, Fig. 13.21
iG= 0
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Y-Parameter Definition (cont.) Saturation Mode
Because the gate terminal is insulated from thechannel by the gate oxide, the input resistance1/y11
of the FET is infinite
Transconductance gm
and output resistance ro
:
gm =y
21=
ID
VGS!V
T
2
=Kn(V
GS!V
T)(1+ "V
DS) = 2K
nID(1+ "V
DS)
ro =
1
y22
=
1
"+V
DS
ID
# 1
" ID
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Limits of Small-Signal Model
What are the limits of the linear operation of the MOSFET, i.e.what are the limits for the input voltage amplitude vgsto enable
use of small-signal model?
Assume n-channel MOSFET in saturation region with vGS= VGS+ vgsand iD= ID+id:
By comparison we find
For a linear relation between idand vgs, we must request
iD =
Kn
2(v
GS!V
T)2
iD = I
D+ i
d =
Kn
2(V
GS+ v
gs! V
T)2 =
Kn
2(V
GS! V
T)2 + 2(V
GS! V
T)v
gs+ v
gs
2"#
$%
id =
Kn
22(V
GS!V
T)v
gs+ v
gs
2"#
$%
vgs
2! 2(V
GS! V
T)v
gs or v
gs! 2(V
GS! V
T)
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Small-Signal Model for PMOS
Transistors
Small signal model for
PMOS transistor is identical
to that of the NMOS device
NMOS PMOS
Jaeger, Blalock, Fig. 13.24
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5.3.3 Comparison Small-Signal Model
for BJT and MOSFET
Parameter BJT Relation MOSFET
Transconductance gm
IC
(kT/q)!
2ID
VGS! V
T
" 2KnID
Input Resistance r#
$o
gm
=
$o(kT/q)
IC
" %
Output Resistance ro
VA+ V
CE
IC
"V
A
IC
& '!1 + V
DS
ID
" 1
' ID
AmplificationFactor gmro
VA+ V
CE
(kT/q)"
VA
(kT/q)!
2('!1 + VDS
)
VGS! V
T
Small-SignalRequirement vbe " (kT/q) " vgs " 2(VGS! VT)
IC = I
S e
qVBE/kT
!1( ) 1+VCE
VA
"
#$
%
&' I
D =
Kn
2VGS
! VT( )
2
1+ (VDS( )
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Comparison Small-Signal Model
for BJT and MOSFET Small signal parameters of BJT and MOSFET are directly controlled by
the design of the Q-point
For a given operating current, the MOSFET has a much smallertransconductance than the BJT
The MOSFET transconductance increases with the square root of thedrain current, the BJT transconductance is directly proportional to thecollector current
Transconductance of MOSFET depends on geometry W/L,transconductance of BJT is geometry independent
Output resistance of BJT and MOSFET are similar for given operatingpoint (ID, VDS) = (IC, VCE), because 1/'is similar to VA
Amplification factor of BJT is larger than amplification factor ofMOSFET
Amplification factor of MOSFET decreases with increasing operatingcurrent, whereas amplification factor of BJT is independent of operatingpoint
MOSFET small signal model can handle larger values of vgsthan thevbeof the corresponding BJT
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5.3.4 Common-Source Amplifier FET version of common-emitter amplifier (see Chapter 4.3)
Goal: Calculate amplifier voltage gain (see Jaeger, Blalock, Chapter 13.10)
DC Analysis:
Find equivalent circuit byreplacing all capacitors withopen circuits and inductors
with short circuits Find the Q-point from the DCequivalent circuit usingappropriate large-signal modelfor the transistor
AC Analysis:
Find AC equivalent circuit by replacing all capacitors by short circuits and
all inductors by open circuits, replacing DC voltage sources by groundconnections and replacing DC current sources by open circuits
Replace FET by its small-signal model
Simplify the resulting AC circuit as much as possible
GND
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Common-Source Amplifier DC Analysis
Parameters: R1= 430 k', R2= 560 k',RD= 4.3 k', RS= 1.3 k', VDD= 12 V,
Kn= 0.5 mA/V2, VT= 1 V, '= 0.0133 V
-1
Thvenin equivalent of gate bias circuit:
Extract VGS, VDS, ID:
VEQ
=
R1
R1+R
2
VDD
= 5.21V
REQ
=
R1R
2
R1+R
2
=243.2 k!
ID =
Kn
2(V
GS! V
T)2(1+ "V
DS)
VEQ = VGS + IDRS
VDD
= (RD+R
S)ID+V
DS
ID= 1.44 mA, VGS= 3.34 V, VDS= 3.93 V
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Common-Source Amplifier AC Analysis
Additional Parameters:
Ri= 1 k', R3= 100 k' RG= R1|| R2= 243.2 k'
Small signal parameters:
RL= ro|| RD|| R3= 3835 '
Calculate vgs, voand vo/vi:
gm =y
21=
2 ID
VGS! V
T
=1.23mS
ro = 1y22
=
"!1+V
DS
ID
= 54.9 k#
vgs =
RG
Ri
+RG
vi = 0.996 v
i
vo = !R
Lg
mv
gs = !4.72 v
gs
Av =v
o/ v
i = !R
Lg
m
RG
Ri+R
G
= !4.7
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Common-Source Amplifier AC Analysis
If RG Ri, then vgs(viand thevoltage gain of the common-source amplifier becomes
i.e. the product of the transistortransconductance gmand theeffective load resistor RL
The sign indicates that inputand output waveform are 180out of phase
The effective load resistance RL
consists of output resistance roin parallel with drain-biasresistor RDand external loadresistor R3
Av
! "gmR
L
Simplified equivalent circuit
for RG Ri:
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Common-Source Amplifier Input/Output Resistance
Input Resistance= totalresistance looking into amplifierat coupling capacitance C1
Attach test signal vxto input sideand measure ix:
Output Resistance= totalresistance looking into amplifierat coupling capacitance C2
Attach test signal vxto outputside and measure ix(keep in
mind that vgs= 0 in this case):
Rin =
vx
ix
=RG
=243 k!
Rout
=
vx
ix
= ro!R
D !
ro"R
D
RD =4.3 k"
Input Resistance
Output Resistance
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5.4 SPICE Analysis
5.4.1 SPICE Model for MOSFET
5.4.2 Implemented Non-Idealities
Channel Length Modulation
Substrate Bias (Body Effect)
Capacitances
Series Resistances
5.4.3 Sample Problem: Putting It All Together
Jaeger, Chapter 4.5-4.7, page 165-172Jaeger, Chapter 4.2.7-4.2.9, page 157-161
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5.4.1 SPICE Model Equations Level-1 Model for NMOS Transistor
Triode Region
Saturation Region
Threshold Voltage
Junction Capacitances
iD =KP
W
LvGS
!VT!vDS
2
"
#$
%
&'v
DS1+LAMBDA v
DS( )
Jaeger, Blalock, Fig. 4.18
CJ =
CJO
1+v
R
PB
!
"#
$
%&
MJ and C
JSW =
CJSWO
1+v
R
PB
!
"#
$
%&
MJSW
iD =
KP
2
W
L
vGS
!VT
( )
2
1+LAMBDA vDS
( )
VT = VTO+GAMMA v
SB+PHI! PHI( )
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With again many Parameters$
Parameter Name Default Comment
Transconductance KP 20 "A/V2
Zero-Bias Threshold Voltage VTO 1 V
Threshold Voltage VT calculated
Surface Potential 2 &F PHI 0.6 V
Body Effect GAMMA 0Channel Length Modulation LAMBDA 0 typ. 0.02 V-1
Mobility UO 600 cm2/Vs
G-D Capacitance per unit width CGDO 0
G-S Capacitance per unit width CGSO 0
G-B Capacitance per unit width CGBO 0Junction Bottom Cap. per unit area CJ 0
Grading Coefficient MJ 0.5 V0.5
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Parameter Name Default Comment
Sidewall Capacitance CJSW 0
Sidewall Grading Coefficient MJSW 0.5 V0.5
Oxide Thickness TOX 100 nm
Junction Saturation Current IS 10 fA
Built-In Potential PB 0.8 V
Ohmic Drain Resistance RD 0
Ohmic Source Resistance RS 0
SPICE Parameters (cont.)
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And for a simple MOSFET$.
Parameter Name Default
Transconductance KP 20 "A/V2
Zero-Bias Threshold Voltage VTO 1 V
Channel Length Modulation LAMBDA 0
What are some of the non-idealities described in the SPICE model?
iD =KP
W
LvGS
! VT!vDS
2
"
#$
%
&'v
DS1+LAMBDA v
DS( )
C
J =C
JSW = 0
iD =
KP
2
W
LvGS
!VT( )
2
1+LAMBDA vDS( )
VT = VTO
C
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5.4.2a Channel Length Modulation
ID-VDSoutput characteristic of realMOSFET has small positive slope
in saturation region due tochannel-length modulation
Similar to base width modulation(Early effect) of BJT
As VDSincreases, the pinched-offlength #L of the channel increasesand L decreases; I
D
is proportionalto L-1, i.e. IDincreases withincreasing VDS
Model for saturation regimeincluding channel lengthmodulation
with 10-3"'"10-1V-1
Jaeger, Blalock, Fig. 4.11
ID =
Kn
2 VGS ! VT( )
2
1+ " VDS( )
5 4 2b B d Eff t
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5.4.2b Body Effect
So far it has been assumed thatthe source-body voltage VSBis
zero With VSB= 0, the MOSFET acts
as a three-terminal device VT = V
T0+ ! V
SB+2"
F# 2"
F( )
VSB!0 changes the thresholdvoltage of the MOSFET; for n-
channel MOSFET
The parameter (is the bodyeffect parameterwith units V0.5
Jaeger, Blalock,
Fig. 4.13&14
4 2 C i
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5.4.2c Capacitances Internal capacitances limit high-frequency performance of
electronic devices (including MOSFET) In logic applications, capacitances limit switching speed
In amplifiers, capacitances limit frequency at which useful
amplification can be achieved
Capacitances of NMOS transistor operated in triode region:
Jaeger, Blalock, Fig. 4.16
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Capacitances of NMOS Transistor
Capacitances of NMOS transistor operated in triode region:
Gate Channel Capacitance:
Gate-Source Capacitance:
Gate-Drain Capacitance:
CGSOand CGDOare overlap capacitancesoriginating from
overlap of gate with source/drain; they are specified ascapacitance per unit width with units [F/m]
In addition, source-bulk and drain-bulk capacitancesCSBandCDBexist between source/drain and bulk substrate (body); thesecapacitances are associated with junction capacitances of reversebiased pn-junctions between source/drain and substrate; each
capacitance consists of a component (CJin [F/m2]) proportional tothe bottom area of source/drain and a sidewall component(CJSWin [F/m]) proportional to the perimeter length
Saturation and cut-off region: see Jaeger, Blalock, page 206-207
CGC = !!CoxW L
CGS
=
CGC
2+C
GSOW = !!C
ox
WL
2+C
GSOW
CGD
=
CGC
2+C
GDOW = !!C
ox
WL
2+C
GDOW
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5.4.3 Sample Problem MOSFET Common Source Amplifier
Our oldProblem:
see Chapter 5.3:
Parameters: VDD= 12 V,Kn= 0.5 mA/V
2, VT= 1 V,
'= 0.0133 V-1
By hand calculationwe found
ID= 1.44 mA, VGS= 3.34 V, VDS= 3.93 V
SPICE M d l
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SPICE Model Q-Point of Common-Source Amplifier
SPICE results: VGS= 3.340 V
VDS= 3.935 V
ID= 1.440 mA
SPICE A l i
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SPICE Analysis AC Sweep: Frequency Transfer
AC sweep analysis provides frequency transfer plot as output
Analysis of choice to investigate frequency dependencies
SPICE A l i
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SPICE Analysis AC Sweep: Frequency Transfer
Gain: |A| %4.70
Vin= 1 mVp
Why do we
see a low
frequency
but no highfrequency
cut-off?
SPICE Analysis
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SPICE Analysis Transient Analysis
Transient signal analysis provides waveform (at a given signalfrequency) as output signal
Analysis of choice to investigate phase relations and signal distortions
SPICE A l i
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SPICE Analysis Transient Analysis: Small Amplitude
Gain: |A| %4.70
Vin= 0.1 Vp
Av= 4.64
SPICE A l i
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SPICE Analysis Transient Analysis: Large
Amplitude
Gain: |A| %4.70
Vin= 1 Vp
What is the
origin of the
distortion?