ARTWORK ANALYSIS TOOLS FOR VLSI CIRCUITS. (U ... Artwork Analysis Tools for VLSI Circuits by Clark Marshall

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  • AOAO87 040 MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTE--ETC F/B 9/5 ARTWORK ANALYSIS TOOLS FOR VLSI CIRCUITS. (U)

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    LABORATORY FOR N 1 A A C I i I I 'TTf: Of-IWI 1*1'(7 - COMPUTER SCIENCF iNol (XY

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    ARTWORK ANALYSIS TOOLS FOR VLSI CIRCUITS

    Clark Marshall Baker

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    A-~wokAn.al-ysis ,Thols for visI ir c M.S. & E.E. Theses-may 1080 S. PERFORMING ORG. REPORT NUMBER

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    M IT/Laboratory for Qmpiter Science fj&" UINMBR 545 Technology Square Caiibridge, MA 02139 _____________

    IS. CONTROLLING OFFICE NAME AND ADDRESS

    ARPAI/Departumnt of Defense JT o 1400 Wilson Boulevard 6 2t. NUMBEfR OF PAGES Arlinigton, VA 22209 7______________

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    1S. SUPPLEMENTARY NOTES

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    artwo~rk -analysis circuit extraction r(1LLLAA design rule checking

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    Current usthods of desiM(1SI)chips c~ not insure that the chips will perform correctly wm mn~uufactured. Becaue the turnaround

    * tine on chip fabr icto varies frcm a few weeks to a few um~ths, a sde other than * ,yit and ame if it work s 1 rmd . Checking of chips by hand sizrulation and visual inspection of dueckplots will no~t catch all of the errors. in addition, the nmbrker of transistors per A chip is li~wly to increase fzuu tn tkKiawd to ayer a million in h -

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    ,.xt few years. This increase in cxmplexity precludes any manual verifi- 7cation meuthods; awie better methoxd is needed.>

    4Aseries of Program that use the actual mask descriptions for put are descried. 'lese programs perform various levels of checks on the masks, yielding files suitable for simulation. Same of the checks are the usual 'Odesign ruleo checks of looking for minimua line widths and adequate spacing betwen wires. However, there are many more constraints in VLSI circuits than are expressed by the usual design rules. The programs check these constraints using the mask descriptions as inut. All of the errors mentioned so far can be classified as syntactic errors; in addition, certain errors are detected. The detection of semantic errors requires various levels of sinalation.-The- 4nput-to the simulators is derived frcm the art-

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  • Artwork Analysis Tools for VLSI Circuits

    by

    Clark Marshall Baker

    Copyright (c) KMOcLlSCzts Institute ofC lchnokogy 1980

    Massachusetts Institute of Technology

    Laboratory for Computer Science

    Cambridge Massachusetts 02139

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    Artwork Analysis Tools for VLSI Circuits

    by

    Clark Marshall Baker

    Submitted to the Department of Electrical Engineering and Computer Science

    on May 18, 1980 in partial fulfillment of the requirements for

    the Degrees of Master of Sciencc and Electrical Engineer

    Abstract

    Current methods of designing VI-SI chips do not insure that the chips will perform correctly when manufactured. Because the turnaround time on chip fabrication varies from a few weeks to a few months, a scheme other than "try it and see if it works" is needed. Checking of chips by hand simulation and visual inspection of checkplots will not catch all of the errors. In addition, the number of transistors per chip is likely to increase from ten thousand to over a million in the next few years. 'Ibis increase in complexity precludes any manual verification methods; some better method is needed.

    A series of programs that use the actual mask descriptions for input are described. ihese programs perform various levels of checks on the masks, yielding files suitable for simulation. Some of the checks are the usual "design rule" checks of looking for minimum line widths and adequate

    - [spacing between wires. However, there are many more constraints in VISI circuits than are expressed by the usual design rules. The programs check these constraints using the mask descriptions as input. All of the errors mentioned so far can be classified as syntactic errors; in addition, certain semantic errors are detected. 1"he detection of semantic errors requires various levels of simulation. 'The input to the simulators is derived from the artwork.

    I

    Name and "litle of'l'hesis Supervisor:

    Stephen A. Ward, Associate Professor of E'lectrical Engineering and Computer Science

    Key Words and Phrases:

    VI.SI, artwork analysis, circuit extraction, design rule checking

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    ACKNOWLEDGMENTS

    The original inspiration for this thesis came from the Schemc79 chip designed by Jack Holloway, Guy Steele, Gerry Sussman, and Alan Bell in the summer of 1979. Except for examination of the checkplot for errors and a small amount of hand simulation, there was no way of making sure that it was going to work. For the fall term offering of the VI SI I)esign course, Randy Bryant had created a switch-levcl simulator for students to test out their designs before implementing them. It occurred to me that it might be possible to extract the logic circuit of the Scheme chip from the actLal mask description. Ibis could then be simulated, with the hope of discovering any remaining bugs. While I went to work on the node extractor, Chris Terman implemented a simulator that could handle such a large circuit, In the end, bugs were found in the Scheme chip and fixed, and after the chip was manufactured, it was found to work.

    Many gotd ideas were generated by Chris "'erman, Jon Sieber, and Dave Goddeau. In addition, sone of the speed improvements came from discussions with Steve Ward and Bert Haistead.

    Ibis thesis would not be as readable as it is without the hard work of I)ebbie Cohn who turned my draft into granmatically correct, smoothly flowing E'nglish. Miriam Alexander and Ronni Rosenberg also provided helpful suggestions about grammer and style.

    ihe comments and corrections made by Chris 'l'erman, Carl Hewitt, Steve Ward, and Iarry Seiler have improved the content and presentation of this thesis.

    No acknowledgments would be complete without a mention of the great working environment provided by the Real Time Systems group of the Laboratory for Computer Science. Both in terms of people and computers, the RTS group provides a place where one can work on interesting problems, from small "hacks" to large programs, with a minimum amount of trouble.

    Many designers have provided me with circuit descriptions to be debugged. Without them, I would not have been able to test out my ideas and generate a useful series of programs. It is hard to know if an idea is any good without actually trying it out.

    This research was supported by the Advanced Research Projects Agency of the I)cpartment of Defense and was monitored by the Office of Naval Research under contract number N00014-75-C-0661.

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  • CONTENTS

    1. Introduction ............................................................................ 7

    2. Why VLSIlCircuits Might Not Work ............................................. 10

    2.1 Design rules........................................................................... 10 2.2 Pullup ratios............................................................................ 13 2.3 Two threshold drops................................................................... 15 2.4 Races ............. ......................*****'*********'****"**'**...***.......***is 2.5 1-1 igh level design errors ............................................................... 16 2.6 Editing errors ........................................................................... 16

    3. What Artwork Anaylsis Can Do For Us ......................................... 18

    3.1 Design rule chcker..................................................................is 3.2 Node extractor....