Gujarat Technological University Subject: VLSI Technology & Design Code:2161101 Topic_2_Fabrication of MOSFET

Compiled By: Prof G B RathodBVM Engineering CollegeET DepartmentV V Nagar-Gujarat-India-388120Email: ghansyam.rathod@bvmengineering.ac.in

Gujarat Technological UniversitySubject: VLSI Technology & DesignCode:2161101Topic_9_Chips Input and Output Circuits

OutlinesIntroductionOn-chip Clock Generation and DistributionLatch-Up and Its PreventionOutcomesReferences

09-May-16BVM ET2

Introduction09-May-16BVM ET3The input/output (VO) circuits, clock generation, and distribution circuits are essential to VLSI chip design.Any external hazards such as electrostatic discharge (ESD) and noises should be filtered out before propagating to the internal circuits for their protection.Also, some chips have to communicate with Transistor- Transistor Logic (TTL) or Emitter-Coupled Logic (ECL) bipolar chips, and in such cases, the input or output circuit must provide proper level shifting so that the transmitted signal contents can be correctly received or sent by the CMOS chip.

On Chip Clock Generation and Distribution09-May-16BVM ET4Clock signals are the heartbeats of digital systems. Hence, the stability of clock signals is highly important.Ideally, clock signals should have minimum rise and fall times, specified duty cycles, and zero skew.A simple technique for on-chip generation of a primary clock signal would be to use a ring oscillator as shown in Fig.13.19.Such a clock circuit has been used in low-end microprocessor chips.

On Chip Clock Generation and Distribution09-May-16BVM ET5

On Chip Clock Generation and Distribution09-May-16BVM ET6However, the generated clock signal can be quite process-dependent and unstable. As a result, separate clock chips which use crystal oscillators have been used for high performance VLSI chip families.Figure 13.20 shows the circuit schematic of a Pierce crystal oscillator with good frequency stability.This circuit is a near series-resonant circuit in which the crystal sees a low load impedance across its terminals

On Chip Clock Generation and Distribution09-May-16BVM ET7

On Chip Clock Generation and Distribution09-May-16BVM ET8Usually a VLSI chip receives one or more primary clock signals from an external clock chip and, in turn, generates necessary derivatives for its internal use. It is often necessary to use two non-overlapping clock signals.The logical product of such two clock signals should be zero at all times. Figure 13.21 shows a simple circuit that generates CK- 1 and CK-2 from the original clock signal CK. Figure 13.22 shows a clock decoder circuit that takes in the primary clock signals and generates four phase signals.

On Chip Clock Generation and Distribution09-May-16BVM ET9

On Chip Clock Generation and Distribution09-May-16BVM ET10

On Chip Clock Generation and Distribution09-May-16BVM ET11Since clock signals are required almost uniformly over the chip area, it is desirable that all clock signals are distributed with a uniform delay. An ideal distribution network would be the H-tree structure shown in Fig. 13.23In such a structure, the distances from the center to all branch points are the same and hence, the signal delays would be the same.However, this structure is difficult to implement in practice due to routing constraints and different fanout requirements.

On Chip Clock Generation and Distribution09-May-16BVM ET12

On Chip Clock Generation and Distribution09-May-16BVM ET13The reduction of clock skews, which are caused by the differences in clock arrival times and changes in clock waveforms due to variations in load conditions, is a major concern in high-speed VLSI design. In addition to uniform clock distribution (H-tree) networks and local skew balancing, a number of new computer-aided design techniques have been developed to automatically generate the layout of an optimum clock distribution network with zero skew.

Latch Up and Its Prevention09-May-16BVM ET14Latch-up is defined as the generation of a low-impedance path in CMOS chips between the power supply rail and the ground rail due to interaction of parasitic pnp and npn bipolar transistors.These BJTs form a silicon-controlled rectifier (SCR) with positive feedback and virtually short circuit the power rail to-ground, thus causing excessive current flows and even permanent device damage.Figure 13.27 shows a cross-sectional view of a CMOS inverter circuit with identification of parasitic npn and pnp bipolar transistors.

Latch Up and Its Prevention09-May-16BVM ET15

Latch Up and Its Prevention09-May-16BVM ET16Some of the causes for latch-up are:Slewing of VDD during initial start-up can cause enough displacement currents due to the well junction capacitance in the substrate and the well. If the slew rate is large enough, latch-up can be induced. But, the SCR can have a dynamic recovery before latch-up when the slew rate is not very high.Large currents in the parasitic SCR in CMOS chips can occur when the input or output signal swings either far beyond the VDD level or far below the Vss (ground) level, thus injecting a triggering current. Such disturbance can happen due to impedance mismatches in transmission lines of high-speed circuits.

Latch Up and Its Prevention09-May-16BVM ET17ESD stress can also cause latch-up by the injection of minority carriers from the clamping device in the protection circuit into either the substrate or the well.Sudden transients in power or ground buses due to simultaneous switching of many drivers may turn on a BJT in SCR.Leakage currents in well junctions can cause large enough lateral currents.Radiation due to X-rays, cosmic rays, or alpha particles may generate enough electron-hole pairs in both the substrate and well regions and thus trigger the SCR.

Latch Up and Its Prevention09-May-16BVM ET18Guidelines for Avoiding Latch-UpReduce the gains of BJTs by lowering the minority carrier lifetime through gold doping of the substrate (but without causing excessive leakage currents) or reducing the minority carrier injection efficiency of BJT emitters by using Schottky source/ drain contacts.Use p+ guard band rings connected to ground around nMOS transistors and n+ guard rings connected to VDD around pMOS transistors to reduce Rw and Rsub and to capture injected minority carriers before they reach the base of the parasitic BJTs.

Latch Up and Its Prevention09-May-16BVM ET19Place substrate and well contacts as close as possible to the source connections of MOS transistors to reduce the values of Rw and RsubUse minimum area p-wells (in case of twin-tub technology or n-type substrate) so that the p-well photocurrent can be minimized during transient pulses.Source diffusion regions of pMOS transistors should be placed so that they lie along equipotential lines when currents flow between VDD and p-wells. In some nwell I/O circuits, wells are eliminated by using only nMOS transistors.

Outcomes09-May-16BVM ET20From this unit we can understand the requirement of clock signal in the various Input output chips. We also learn the different types of Clock generation circuits and problems associated with those circuits. The Latch up problem and its prevention concept is also understood by this unit.

References09-May-16BVM ET21Book: CMOS Digital Integrated Circuit Design - Analysis and Design by S.M. Kang and Y. Leblebici.