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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware
Reference
Revision 0.5, February 2018
Part Number82-100132-01
Analog Devices, Inc.One Technology WayNorwood, MA 02062-9106
Notices
Copyright Information
2018 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any formwithout prior, express written consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Ana-log Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for itsuse; nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, Blackfin, Blackfin+, CrossCore, EngineerZone, EZ-Board, EZ-KIT Lite, EZ-KIT Mini,
EZ-Extender, SHARC, SHARC+, A2B, and VisualDSP++ are registered trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of their respective owners.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
ii
Contents
Introduction
ADuCM4050 MCU Features ........................................................................................................................ 11
ADuCM4050 Functional Description ........................................................................................................... 12
ADuCM4050 Block Diagram..................................................................................................................... 12
Memory Architecture.................................................................................................................................. 13
SRAM Region ............................................................................................................................................ 13
System Region ............................................................................................................................................ 14
Flash Controller.......................................................................................................................................... 15
Cache Controller ........................................................................................................................................ 15
ARM Cortex-M4F Memory Subsystem ...................................................................................................... 15
Booting ...................................................................................................................................................... 15
Security Features......................................................................................................................................... 16
Safety Features ............................................................................................................................................ 16
Multi Parity Bit Protected SRAM............................................................................................................... 16
Programmable GPIOs ................................................................................................................................ 16
Timers ........................................................................................................................................................ 16
Power Management .................................................................................................................................... 17
Clocking ..................................................................................................................................................... 17
Real-Time Clock (RTC) ............................................................................................................................. 18
System Debug ............................................................................................................................................ 19
Beeper Driver ........................................................................................................................................... 110
Cryptographic Accelerator (Crypto) ......................................................................................................... 110
CRC Accelerator....................................................................................................................................... 110
True Random Number Generator (TRNG).............................................................................................. 111
Serial Ports (SPORTs) .............................................................................................................................. 111
Serial Peripheral Interface (SPI) Ports....................................................................................................... 111
UART Ports.............................................................................................................................................. 112
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
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Inter-Integrated Circuit (I2C)................................................................................................................... 112
Analog-to-Digital Converter (ADC) Subsystem........................................................................................ 112
Reference Designs..................................................................................................................................... 112
Development Tools................................................................................................................................... 112
ADuCM4050 Peripheral Memory Map ....................................................................................................... 113
Debug (DBG) and Trace Interfaces
Debug and Trace Features .............................................................................................................................. 21
DBG Functional Description......................................................................................................................... 21
Serial Wire Interface ................................................................................................................................... 21
DBG Operating Modes ................................................................................................................................. 22
Serial Wire Protocol.................................................................................................................................... 22
Debug Access Port (DAP).............................................................................................................................. 24
Debug Port .................................................................................................................................................... 25
ADuCM4050 SYS Register Descriptions ...................................................................................................... 25
ADI Identification ..................................................................................................................................... 26
Chip Identifier ........................................................................................................................................... 27
Serial Wire Debug Enable .......................................................................................................................... 28
Events (Interrupts and Exceptions)
Events Features .............................................................................................................................................. 31
Events Interrupts and Exceptions................................................................................................................... 31
Cortex Exceptions....................................................................................................................................... 31
Nested Vectored Interrupt Controller ......................................................................................................... 32
Handling Interrupt Registers...................................................................................................................... 34
External Interrupt Configuration................................................................................................................ 35
ADuCM4050 XINT Register Descriptions .................................................................................................. 35
External Interrupt Configuration ............................................................................................................... 37
External Interrupt Clear .......................................................................................................................... 310
External Wakeup Interrupt Status ............................................................................................................ 311
Non-maskable Interrupt Clear ................................................................................................................. 313
iv ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
Power Management (PMG)
Power Management Features ......................................................................................................................... 41
Power Management Functional Description .................................................................................................. 41
Power-up Sequence..................................................................................................................................... 41
Operating Modes ........................................................................................................................................... 42
Active Mode ............................................................................................................................................... 42
Flexi Mode.................................................................................................................................................. 43
Hibernate Mode ......................................................................................................................................... 44
Shutdown Mode ......................................................................................................................................... 45
Programming Sequence ................................................................................................................................. 46
Configuring Hibernate Mode ..................................................................................................................... 46
Configuring Shutdown Mode..................................................................................................................... 47
Wake-up Sequence ......................................................................................................................................... 48
Fast Wake-up from Shutdown Mode.............................................................................................................. 48
Monitor Voltage Control ............................................................................................................................... 48
ADuCM4050 PMG Register Descriptions ................................................................................................. 410
HPBUCK Control ................................................................................................................................... 412
Power Supply Monitor Interrupt Enable .................................................................................................. 413
Trimming Bits ......................................................................................................................................... 415
Power Supply Monitor Status .................................................................................................................. 416
Key Protection for PMG_PWRMOD and PMG_SRAMRET ................................................................ 419
Power Mode Register ............................................................................................................................... 420
Reset Status ............................................................................................................................................. 421
Shutdown Status Register ........................................................................................................................ 423
Control for Retention SRAM in Hibernate Mode ................................................................................... 424
ADuCM4050 PMG_TST Register Descriptions ........................................................................................ 424
Clear GPIO After Shutdown Mode ......................................................................................................... 426
Fast Shutdown Wake-up Enable .............................................................................................................. 427
Scratch Pad Saved in Battery Domain ...................................................................................................... 428
Scratch Pad Image ................................................................................................................................... 429
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
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Control for SRAM Parity and Instruction SRAM .................................................................................... 430
Initialization Status Register .................................................................................................................... 432
General-Purpose I/O (GPIO)
GPIO Features............................................................................................................................................... 51
GPIO Functional Description........................................................................................................................ 51
GPIO Block Diagram................................................................................................................................. 51
ADuCM4050 GPIO Multiplexing ............................................................................................................. 53
GPIO Operating Modes ................................................................................................................................ 55
IO Pull-Up or Pull-Down Enable ............................................................................................................... 55
IO Data In ................................................................................................................................................. 55
IO Data Out............................................................................................................................................... 55
Bit Set......................................................................................................................................................... 55
Bit Clear ..................................................................................................................................................... 55
Bit Toggle ................................................................................................................................................... 55
IO Data Output Enable.............................................................................................................................. 55
Interrupts ................................................................................................................................................... 55
Interrupt Polarity........................................................................................................................................ 56
Interrupt A Enable...................................................................................................................................... 56
Interrupt B Enable...................................................................................................................................... 56
Interrupt Status .......................................................................................................................................... 56
GPIO Programming Model ........................................................................................................................... 57
ADuCM4050 GPIO Register Descriptions .................................................................................................. 57
Port Configuration .................................................................................................................................... 58
Port Data Out Clear ................................................................................................................................ 510
Port Drive Strength Select ....................................................................................................................... 511
Port Input Path Enable ............................................................................................................................ 514
Port Interrupt A Enable ........................................................................................................................... 515
Port Interrupt B Enable ........................................................................................................................... 516
Port Registered Data Input ...................................................................................................................... 517
vi ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
Port Interrupt Status ................................................................................................................................ 518
Port Output Enable ................................................................................................................................. 519
Port Data Output .................................................................................................................................... 520
Port Output Pull-up/Pull-down Enable ................................................................................................... 521
Port Interrupt Polarity ............................................................................................................................. 522
Port Data Out Set .................................................................................................................................... 523
Port Pin Toggle ........................................................................................................................................ 524
System Clocks
System Clock Features ................................................................................................................................... 61
System Clock Functional Description ............................................................................................................ 62
System Clock Block Diagram ..................................................................................................................... 62
Clock Muxes ........................................................................................................................................... 63
Clock Dividers ........................................................................................................................................ 64
Clock Gating........................................................................................................................................... 64
PLL Settings .................................................................................................................................................. 65
PLL Interrupts............................................................................................................................................ 66
PLL Programming Sequence ...................................................................................................................... 66
Crystal Programming..................................................................................................................................... 67
Oscillator Programming ................................................................................................................................ 68
Switching System Clock to Greater than 26 MHz ......................................................................................... 68
Oscillators...................................................................................................................................................... 69
System Clock Interrupts and Exceptions...................................................................................................... 612
Setting the System Clocks............................................................................................................................ 613
Set System Clock to PLL Input Source ..................................................................................................... 613
Set System Clock to XTAL ....................................................................................................................... 615
Changing System Clock Source ................................................................................................................ 617
ADuCM4050 CLKG_OSC Register Descriptions ...................................................................................... 618
Oscillator Control ................................................................................................................................... 619
Key Protection for OSCCTRL ................................................................................................................ 624
ADuCM4050 CLKG_CLK Register Descriptions ...................................................................................... 624
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
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Misc Clock Settings ................................................................................................................................. 625
Clock Dividers ......................................................................................................................................... 628
HF Oscillator Divided Clock Select ......................................................................................................... 630
System PLL ............................................................................................................................................. 632
User Clock Gating Control ...................................................................................................................... 634
Clocking Status ....................................................................................................................................... 637
Reset (RST)
ADuCM4050 Reset Register Description ...................................................................................................... 72
Reset Status ............................................................................................................................................... 73
Flash Controller (FLASH)
Flash Features ................................................................................................................................................ 81
Supported Commands................................................................................................................................ 81
Protection and Integrity Features................................................................................................................ 82
Flash Functional Description ......................................................................................................................... 82
Organization .............................................................................................................................................. 82
Flash Access ................................................................................................................................................ 85
Reading Flash .......................................................................................................................................... 87
Erasing Flash ........................................................................................................................................... 87
Writing Flash........................................................................................................................................... 88
Protection and Integrity............................................................................................................................ 812
Integrity of Info Space........................................................................................................................... 812
User Space Protection............................................................................................................................ 812
Runtime Configuration......................................................................................................................... 813
Meta Data Configuration ...................................................................................................................... 814
Signatures.............................................................................................................................................. 815
Key Register .......................................................................................................................................... 816
ECC ...................................................................................................................................................... 816
Clock and Timings................................................................................................................................ 817
Flash Operating Modes................................................................................................................................ 818
Clock Gating ............................................................................................................................................... 819
viii ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
Flash Interrupts and Exceptions................................................................................................................... 819
Flash Programming Model........................................................................................................................... 819
Programming Guidelines.......................................................................................................................... 819
ADuCM4050 FLCC Register Descriptions ................................................................................................ 819
IRQ Abort Enable (Upper Bits) ............................................................................................................... 821
IRQ Abort Enable (Lower Bits) ............................................................................................................... 822
Flash Security .......................................................................................................................................... 823
Volatile Flash Configuration .................................................................................................................... 824
Command ............................................................................................................................................... 825
ECC Status (Address) .............................................................................................................................. 829
Interrupt Enable ...................................................................................................................................... 830
Key .......................................................................................................................................................... 832
Write Address .......................................................................................................................................... 833
Write Lower Data .................................................................................................................................... 834
Write Upper Data .................................................................................................................................... 835
Lower Page Address ................................................................................................................................. 836
Upper Page Address ................................................................................................................................. 837
Signature ................................................................................................................................................. 838
Status ....................................................................................................................................................... 839
Time Parameter 0 .................................................................................................................................... 845
Time Parameter 1 .................................................................................................................................... 848
User Configuration .................................................................................................................................. 850
Write Protection ...................................................................................................................................... 852
Write Abort Address ................................................................................................................................ 854
Static Random Access Memory (SRAM)
SRAM Features .............................................................................................................................................. 91
SRAM Configuration .................................................................................................................................... 91
Instruction SRAM vs Data SRAM.............................................................................................................. 91
SRAM Retention in Hibernate Mode ......................................................................................................... 92
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
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SRAM Programming Model .......................................................................................................................... 92
SRAM Parity ................................................................................................................................................. 92
SRAM Initialization....................................................................................................................................... 93
Initialization in Cache ................................................................................................................................ 94
Kernel Code: SRAM Bank 0 Initialization Before User Code Execution..................................................... 94
ADuCM4050 SRAM Register Description.................................................................................................... 94
Initialization Status Register ...................................................................................................................... 95
Control for SRAM Parity and Instruction SRAM ...................................................................................... 97
Control for Retention SRAM in Hibernate Mode ..................................................................................... 99
Cache
Cache Programming Model ......................................................................................................................... 101
Programming Guidelines.......................................................................................................................... 101
ADuCM4050 FLCC_CACHE Register Descriptions ................................................................................. 101
Cache Key Register .................................................................................................................................. 102
Cache Setup Register ............................................................................................................................... 103
Cache Status Register .............................................................................................................................. 104
Direct Memory Access (DMA)
DMA Features ............................................................................................................................................. 111
DMA Functional Description ...................................................................................................................... 112
DMA Architectural Concepts ................................................................................................................... 113
DMA Operating Modes............................................................................................................................... 113
Channel Control Data Structure............................................................................................................... 113
Source Data End Pointer .......................................................................................................................... 115
Destination Data End Pointer .................................................................................................................. 115
Control Data Configuration ..................................................................................................................... 115
DMA Priority ........................................................................................................................................... 118
DMA Transfer Types ................................................................................................................................ 119
Invalid ................................................................................................................................................... 119
Basic...................................................................................................................................................... 119
x ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
Auto-Request....................................................................................................................................... 1110
Ping-Pong ........................................................................................................................................... 1110
Memory Scatter-Gather....................................................................................................................... 1112
Peripheral Scatter-Gather .................................................................................................................... 1114
DMA Interrupts and Exceptions............................................................................................................. 1116
Error Management .............................................................................................................................. 1116
Address Calculation............................................................................................................................. 1116
Address Decrement.............................................................................................................................. 1117
Endian Operation................................................................................................................................... 1118
DMA Channel Enable/Disable ............................................................................................................... 1119
DMA Master Enable .............................................................................................................................. 1120
Power-down Considerations ................................................................................................................... 1120
DMA Programming Model........................................................................................................................ 1120
Programming Guidelines........................................................................................................................ 1120
ADuCM4050 DMA Register Descriptions ............................................................................................... 1121
DMA Channel Alternate Control Database Pointer .............................................................................. 1122
DMA Channel Primary Alternate Clear ................................................................................................ 1123
DMA Channel Primary Alternate Set .................................................................................................... 1124
DMA Channel Bytes Swap Enable Clear ............................................................................................... 1125
DMA Channel Bytes Swap Enable Set ................................................................................................... 1126
DMA Configuration .............................................................................................................................. 1127
DMA Channel Destination Address Decrement Enable Clear ............................................................... 1128
DMA Channel Destination Address Decrement Enable Set ................................................................... 1129
DMA Channel Enable Clear .................................................................................................................. 1130
DMA Channel Enable Set ..................................................................................................................... 1131
DMA per Channel Error Clear .............................................................................................................. 1132
DMA Bus Error Clear ........................................................................................................................... 1133
DMA per Channel Invalid Descriptor Clear .......................................................................................... 1134
DMA Channel Primary Control Database Pointer ................................................................................ 1135
DMA Channel Priority Clear ................................................................................................................ 1136
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
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DMA Channel Priority Set .................................................................................................................... 1137
DMA Controller Revision ID ................................................................................................................ 1138
DMA Channel Request Mask Clear ...................................................................................................... 1139
DMA Channel Request Mask Set .......................................................................................................... 1140
DMA Channel Source Address Decrement Enable Clear ....................................................................... 1141
DMA Channel Source Address Decrement Enable Set ........................................................................... 1142
DMA Status .......................................................................................................................................... 1143
DMA Channel Software Request ........................................................................................................... 1144
Cryptography (CRYPTO)
Crypto Features ........................................................................................................................................... 122
Crypto Functional Description .................................................................................................................... 122
Crypto Block Diagram ............................................................................................................................. 123
Crypto Operating Modes............................................................................................................................. 123
Crypto Data Transfer................................................................................................................................... 124
Crypto Data Rate ..................................................................................................................................... 124
Data Pipeline............................................................................................................................................ 125
DMA Capability....................................................................................................................................... 125
Core Transfer............................................................................................................................................ 125
Data Formatting .......................................................................................................................................... 125
Interrupts..................................................................................................................................................... 127
Crypto Error Conditions ............................................................................................................................. 128
Crypto Status Bits........................................................................................................................................ 128
Crypto Keys............................................................................................................................................... 1210
Key Length ............................................................................................................................................. 1210
Key Programming .................................................................................................................................. 1210
Key Wrap-Unwrap Register .................................................................................................................... 1211
Key Register Attributes........................................................................................................................... 1211
Crypto Power Saver Mode ......................................................................................................................... 1211
Registers with Mode Specific Roles............................................................................................................ 1211
xii ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
Protected Key Storage (PrKStor)................................................................................................................ 1213
Operation ............................................................................................................................................... 1214
Protected Key Storage Configuration...................................................................................................... 1215
Command Fail Status ............................................................................................................................. 1218
HMAC ...................................................................................................................................................... 1219
HMAC Algorithm .................................................................................................................................. 1219
Programming Model .............................................................................................................................. 1220
CCM/CCM* Mode ................................................................................................................................... 1221
Programming Flow for Block Modes of operation ..................................................................................... 1223
Payload and Authenticated Data Formatting .......................................................................................... 1225
Programming Flow for SHA-Only Operation............................................................................................ 1225
Retention in Hibernate Mode.................................................................................................................... 1226
ADuCM4050 CRYPT Register Descriptions ............................................................................................ 1226
AES Key Bits [31:0] ............................................................................................................................... 1229
AES Key Bits [63:32] ............................................................................................................................. 1230
AES Key Bits [95:64] ............................................................................................................................. 1231
AES Key Bits [127:96] ........................................................................................................................... 1232
AES Key Bits [159:128] ......................................................................................................................... 1233
AES Key Bits [191:160] ......................................................................................................................... 1234
AES Key Bits [223:192] ......................................................................................................................... 1235
AES Key Bits [255:224] ......................................................................................................................... 1236
NUM_VALID_BYTES ......................................................................................................................... 1237
Configuration Register .......................................................................................................................... 1238
Counter Initialization Vector ................................................................................................................. 1241
Payload Data Length ............................................................................................................................. 1242
Input Buffer .......................................................................................................................................... 1243
Interrupt Enable Register ...................................................................................................................... 1244
Key Wrap Unwrap Register 0 ................................................................................................................ 1245
Key Wrap Unwrap Register 1 ................................................................................................................ 1246
Key Wrap Unwrap Register 10 .............................................................................................................. 1247
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
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Key Wrap Unwrap Register 11 .............................................................................................................. 1248
Key Wrap Unwrap Register 12 .............................................................................................................. 1249
Key Wrap Unwrap Register 13 .............................................................................................................. 1250
Key Wrap Unwrap Register 14 .............................................................................................................. 1251
Key Wrap Unwrap Register 15 .............................................................................................................. 1252
Key Wrap Unwrap Register 2 ................................................................................................................ 1253
Key Wrap Unwrap Register 3 ................................................................................................................ 1254
Key Wrap Unwrap Register 4 ................................................................................................................ 1255
Key Wrap Unwrap Register 5 ................................................................................................................ 1256
Key Wrap Unwrap Register 6 ................................................................................................................ 1257
Key Wrap Unwrap Register 7 ................................................................................................................ 1258
Key Wrap Unwrap Register 8 ................................................................................................................ 1259
Key Wrap Unwrap Register 9 ................................................................................................................ 1260
Key Wrap Unwrap Validation String [63:32] ......................................................................................... 1261
Key Wrap Unwrap Validation String [31:0] ........................................................................................... 1262
Nonce Bits [31:0] .................................................................................................................................. 1263
Nonce Bits [63:32] ................................................................................................................................ 1264
Nonce Bits [95:64] ................................................................................................................................ 1265
Nonce Bits [127:96] .............................................................................................................................. 1266
Output Buffer ........................................................................................................................................ 1267
Authentication Data Length .................................................................................................................. 1268
PRKSTOR Configuration ..................................................................................................................... 1269
SHA Bits [31:0] ..................................................................................................................................... 1270
SHA Bits [63:32] ................................................................................................................................... 1271
SHA Bits [95:64] ................................................................................................................................... 1272
SHA Bits [127:96] ................................................................................................................................. 1273
SHA Bits [159:128] ............................................................................................................................... 1274
SHA Bits [191:160] ............................................................................................................................... 1275
SHA Bits [223:192] ............................................................................................................................... 1276
SHA Bits [255:224] ............................................................................................................................... 1277
xiv ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
SHA Last Word and Valid Bits Information ........................................................................................... 1278
Status Register ....................................................................................................................................... 1279
True Random Number Generator (TRNG)
TRNG Features ........................................................................................................................................... 131
TRNG Functional Description .................................................................................................................... 131
TRNG Block Diagram ............................................................................................................................. 131
TRNG Oscillator Counter ....................................................................................................................... 132
TRNG Entropy and Surprisal................................................................................................................... 134
Oscillator Count Difference ..................................................................................................................... 135
ADuCM4050 RNG Register Descriptions .................................................................................................. 135
RNG Control Register ............................................................................................................................. 137
RNG Data Register ................................................................................................................................. 138
RNG Sample Length Register .................................................................................................................. 139
Oscillator Count .................................................................................................................................... 1310
Oscillator Difference .............................................................................................................................. 1311
RNG Status Register ............................................................................................................................. 1312
Cyclic Redundancy Check (CRC)
CRC Features............................................................................................................................................... 141
CRC Functional Description ....................................................................................................................... 141
CRC Block Diagram................................................................................................................................. 141
CRC Operating Modes ................................................................................................................................ 142
Polynomial ............................................................................................................................................... 143
Reset and Hibernate Modes...................................................................................................................... 145
Input Data Length....................................................................................................................................... 145
CRC Data Transfer ...................................................................................................................................... 146
CRC Interrupts and Exceptions ................................................................................................................... 146
CRC Programming Model........................................................................................................................... 146
Mirroring Options.................................................................................................................................... 148
ADuCM4050 CRC Register Descriptions .................................................................................................. 149
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
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CRC Control ......................................................................................................................................... 1410
Input Data Bits ...................................................................................................................................... 1412
Input Data Byte ..................................................................................................................................... 1413
Input Data Word ................................................................................................................................... 1414
Programmable CRC Polynomial ............................................................................................................ 1415
CRC Result ........................................................................................................................................... 1416
Serial Peripheral Interface (SPI)
SPI Features ................................................................................................................................................. 151
SPI Functional Description.......................................................................................................................... 152
SPI Block Diagram................................................................................................................................... 152
MISO (Master In, Slave Out) Pin............................................................................................................. 153
MOSI (Master Out, Slave In) Pin............................................................................................................. 153
SCLK (Serial Clock I/O) Pin .................................................................................................................... 153
Chip Select (CS I/O) Pin.......................................................................................................................... 153
SPI Operating Modes .................................................................................................................................. 154
Wired-OR Mode (WOM) ........................................................................................................................ 154
General Instructions.............................................................................................................................. 154
Power-down Mode ................................................................................................................................... 154
SPI2 vs SPI0/SPI1.................................................................................................................................... 155
Interfacing with SPI Slaves ....................................................................................................................... 155
Flow Control ............................................................................................................................................ 156
Three-Pin Mode ....................................................................................................................................... 158
SPI Data Transfer ........................................................................................................................................ 158
Transmit Initiated Transfer....................................................................................................................... 159
Receive Initiated Transfer ......................................................................................................................... 159
Transfers in Slave Mode.......................................................................................................................... 1510
SPI Data Underflow and Overflow......................................................................................................... 1511
SPI Interrupts and Exceptions ................................................................................................................... 1511
Transmit Interrupt.................................................................................................................................. 1512
xvi ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
Receive Interrupt .................................................................................................................................... 1512
Underflow/Overflow Interrupts.............................................................................................................. 1513
SPI Programming Model ........................................................................................................................... 1513
SPI DMA ............................................................................................................................................... 1513
ADuCM4050 SPI Register Descriptions ................................................................................................... 1515
Transfer Byte Count .............................................................................................................................. 1517
Chip Select Control for Multi-slave Connections .................................................................................. 1518
Chip Select Override ............................................................................................................................. 1519
SPI Configuration ................................................................................................................................. 1520
SPI Baud Rate Selection ........................................................................................................................ 1523
SPI DMA Enable ................................................................................................................................... 1524
FIFO Status ........................................................................................................................................... 1525
Flow Control ......................................................................................................................................... 1526
SPI Interrupts Enable ............................................................................................................................ 1528
Read Control ......................................................................................................................................... 1531
Receive .................................................................................................................................................. 1533
Status ..................................................................................................................................................... 1534
Transmit ................................................................................................................................................ 1537
Wait Timer for Flow Control ................................................................................................................. 1538
Serial Port (SPORT)
SPORT Features .......................................................................................................................................... 161
Signal Description ....................................................................................................................................... 162
SPORT Functional Description................................................................................................................... 163
SPORT Block Diagram ............................................................................................................................ 163
SPORT Transfer....................................................................................................................................... 164
Multiplexer Logic ..................................................................................................................................... 165
Serial Clock .............................................................................................................................................. 167
Frame Sync ............................................................................................................................................... 168
Frame Sync Options .............................................................................................................................. 169
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
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Sampling Edge........................................................................................................................................ 1611
Premature Frame Sync Error Detection .................................................................................................. 1612
Serial Word Length................................................................................................................................. 1613
Number of Transfers............................................................................................................................... 1613
SPORT Power Management................................................................................................................... 1614
SPORT Operating Modes ......................................................................................................................... 1614
Mode Selection....................................................................................................................................... 1614
SPORT Data Transfer ............................................................................................................................... 1616
Single Word (Core) Transfers.................................................................................................................. 1616
DMA Transfers....................................................................................................................................... 1616
SPORT Data Buffers ................................................................................................................................. 1617
Data Buffer Status .................................................................................................................................. 1617
Data Buffer Packing ............................................................................................................................... 1617
SPORT Interrupts and Exceptions............................................................................................................. 1618
Error Detection ...................................................................................................................................... 1618
System Transfer Interrupts ..................................................................................................................... 1619
Transfer Finish Interrupt (TFI)............................................................................................................... 1619
SPORT Programming Model .................................................................................................................... 1619
ADuCM4050 SPORT Register Descriptions ............................................................................................ 1620
Half SPORT 'A' Control Register ......................................................................................................... 1621
Half SPORT 'B' Control Register ......................................................................................................... 1626
Half SPORT 'A' Divisor Register .......................................................................................................... 1630
Half SPORT 'B' Divisor Register .......................................................................................................... 1631
Half SPORT A's Interrupt Enable register ............................................................................................ 1632
Half SPORT B's Interrupt Enable register ............................................................................................ 1634
Half SPORT A Number of transfers register ......................................................................................... 1636
Half SPORT B Number of transfers register ......................................................................................... 1637
Half SPORT 'A' Rx Buffer Register ....................................................................................................... 1638
Half SPORT 'B' Rx Buffer Register ....................................................................................................... 1639
Half SPORT 'A' Status register ............................................................................................................. 1640
xviii ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
Half SPORT 'B' Status register ............................................................................................................. 1642
Half SPORT 'A' CNV width ................................................................................................................. 1644
Half SPORT 'B' CNV width register .................................................................................................... 1645
Half SPORT 'A' Tx Buffer Register ...................................................................................................... 1646
Half SPORT 'B' Tx Buffer Register ...................................................................................................... 1647
Universal Asynchronous Receiver/Transmitter (UART)
UART Features ............................................................................................................................................ 171
UART Functional Description ..................................................................................................................... 172
UART Block Diagram .............................................................................................................................. 172
UART Operations........................................................................................................................................ 172
Serial Communications ............................................................................................................................ 172
UART Operating Modes.............................................................................................................................. 175
IO Mode .................................................................................................................................................. 175
DMA Mode.............................................................................................................................................. 175
UART Interrupts ......................................................................................................................................... 175
FIFO Mode (16550) .................................................................................................................................... 176
Auto Baud Rate Detection (ABD)................................................................................................................ 176
RS485 Half-Duplex Mode ........................................................................................................................... 178
Receive Line Inversion ................................................................................................................................. 178
Clock Gating ............................................................................................................................................... 179
UART and Power-Down Modes .................................................................................................................. 179
ADuCM4050 UART Register Descriptions .............................................................................................. 1710
Auto Baud Control ................................................................................................................................ 1711
Auto Baud Status (High) ....................................................................................................................... 1713
Auto Baud Status (Low) ......................................................................................................................... 1714
UART Control Register ......................................................................................................................... 1715
Baud Rate Divider ................................................................................................................................. 1716
Fractional Baud Rate ............................................................................................................................. 1717
FIFO Control ........................................................................................................................................ 1718
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
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Interrupt Enable .................................................................................................................................... 1720
Interrupt ID .......................................................................................................................................... 1721
Line Control .......................................................................................................................................... 1722
Second Line Control .............................................................................................................................. 1724
Line Status ............................................................................................................................................. 1725
Modem Control ..................................................................................................................................... 1727
Modem Status ....................................................................................................................................... 1728
RX FIFO Byte Count ............................................................................................................................ 1730
RS485 Half-duplex Control ................................................................................................................... 1731
Receive Buffer Register .......................................................................................................................... 1732
Scratch Buffer ........................................................................................................................................ 1733
TX FIFO Byte Count ............................................................................................................................ 1734
Transmit Holding Register .................................................................................................................... 1735
Inter-Integrated Circuit (I2C) Interface
I2C Features ................................................................................................................................................ 181
I2C Functional Description ......................................................................................................................... 181
I2C Block Diagram .................................................................................................................................. 181
I2C Operating Modes.................................................................................................................................. 182
Master Transfer Initiation......................................................................................................................... 182
Slave Transfer Initiation............................................................................................................................ 182
Rx/Tx Data FIFOs ................................................................................................................................... 183
No Acknowledge from Master .................................................................................................................. 184
No Acknowledge from Slave ..................................................................................................................... 185
General Call ............................................................................................................................................. 185
Generation of Repeated Starts by Master.................................................................................................. 185
DMA Requests ......................................................................................................................................... 186
I2C Reset Mode ....................................................................................................................................... 186
I2C Test Modes ........................................................................................................................................ 186
I2C Low-Power Mode .............................................................................................................................. 186
xx ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
I2C Bus Clear Operation.......................................................................................................................... 186
Power-down Considerations ..................................................................................................................... 187
I2C Data Transfer........................................................................................................................................ 187
I2C Interrupts and Exceptions..................................................................................................................... 188
ADuCM4050 I2C Register Descriptions .................................................................................................... 188
Master Address Byte 1 ............................................................................................................................. 189
Master Address Byte 2 ........................................................................................................................... 1810
Hardware General Call ID ..................................................................................................................... 1811
Automatic Stretch SCL .......................................................................................................................... 1812
Start Byte ............................................................................................................................................... 1814
Serial Clock Period Divisor .................................................................................................................... 1815
First Slave Address Device ID ................................................................................................................ 1816
Second Slave Address Device ID ............................................................................................................ 1817
Third Slave Address Device ID .............................................................................................................. 1818
Fourth Slave Address Device ID ............................................................................................................ 1819
Master Control ...................................................................................................................................... 1820
Master Current Receive Data Count ...................................................................................................... 1822
Master Receive Data .............................................................................................................................. 1823
Master Receive Data Count ................................................................................................................... 1824
Master Status ......................................................................................................................................... 1825
Master Transmit Data ............................................................................................................................ 1828
Slave Control ......................................................................................................................................... 1829
Shared Control ...................................................................................................................................... 1831
Slave Receive .......................................................................................................................................... 1832
Slave I2C Status/Error/IRQ ................................................................................................................... 1833
Master and Slave FIFO Status ................................................................................................................ 1836
Slave Transmit ....................................................................................................................................... 1838
Timing Control Register ....................................................................................................................... 1839
Beeper Driver (BEEP)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hard-ware Reference
xxi
Beeper Features............................................................................................................................................ 191
Beeper Functional Description..................................................................................................................... 191
Beeper Block Diagram.............................................................................................................................. 191
Beeper Operating Modes ............................................................................................................................. 192
Pulse Mode............................................................................................................................................... 193
Sequence Mode......................................................................................................................................... 193
Tones........................................................................................................................................................ 194
Clocking and Power.................................................................................................................................. 194
Power-down Considerations ..................................................................................................................... 195
Beeper Interrupts and Events ....................................................................................................................... 195
Beeper Programming Model ..............................