Dr. Rehan Hafiz <rehan.hafiz@seecs.edu.pk> Lecture # 02

Course Website for ADSD Fall 2011

http://lms.nust.edu.pk/

Key: EE803

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Lectures: Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm

Contact: By appointment/Email Office: VISpro Lab above SEECS Library

Acknowledgement: Material from the following sources has been consulted/used in these

slides:

1. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan

Material/Slides from these slides CAN be used with following citing reference: Dr. Rehan Hafiz: Advanced Digital System Design 2010

Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.

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1 Introduction Outline & Introduction, Initial Assessment of students, Digital design

methodology & design flow

2 Verilog+

Combinational Logic

Combinational Logic Review + Verilog Introduction, Combinational Building

Blocks in Verilog

3 Verilog + Sequential Logic Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS),

Sequential Logic in Verilog

4 Synthesis in Verilog Synthesis of Blocking/Non-Blocking Statements

5 Micro-Architecture Design Partitioning + RISC Microprocessor + Micro architecture Document

6 Optimizing Speed Architecting Speed in Digital System Design: [Throughput, Latency, Timing]

7 Optimizing Area Architecting Area in Digital System Design: [Area Optimization]

8 FIR Implementation FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs

10 CDC Issues Cross-Clock Domain Issues & RESET circuits

11 Fixed-Point Arithmetic Arithmetic Operations: Review Fixed Point Representation

12 Adders Adders & Fast Adders Multi-Operand Addition

13 Multipliers Multiplication , Multiplication by Constants + BOOTH Multipliers

13 CORDIC CORDIC (sine, cosine, magnitude, division, etc), CORDIC in HW

14 Algorithmic

Transformations for

System Design

DFG representation of DSP Algorithms, Iteration Bound

& Retiming

15 Algorithmic

Transformations for

System Design

Unfolding

Look ahead transformations

16 Project Course Review & Project Presentations

17 Project Project Presentations

Verilog Basics 4

Verilog 5

HW or SW ?

Verilog --- Programming language ?

Verilog --- Sequential language ?

Verilog

HW Description

Creates your Datapath

Creates your circuit

Its simulation isEvent Based

Verilog (Samir Palnitkar – Chapter 1-5)

Data Types

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Nets Connection between hardware elements

Default value Z High Impedance [not driven by circuit]

Declared as Wire

Registers A variable that holds a value … (need to be careful)?

Synthesizable to register or latch

Declared as reg

Vectors Wire [7:0] bus; 8 bit bus, with bit-7 as the most significant

Memories reg mem1bit [0:1023]; // 1K 1 bit words

reg [7:0] membyte [0: 1023]; // 1K 8 bit words

Others Integer, Real, Time, Arrays, Strings, Parameters

Verilog 2001 allows Multi-Dimentional Arrays

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Xilinx allows supports upto 3D arrays

Declaring 3D array

//////////////// 3 D Array

reg [7:0] d [0:3][0:1][0:1];

Accessing 3D Array

d[i1][i2][i3] <= data;

e <= d[3][1][0][3:0];

http://www.sutherland-hdl.com/papers/2000-HDLCon-paper_Verilog-2000.pdf

Verilog (Samir Palnitkar – Chapter 1-5)

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Comments // Number Specification

2’b11 // 2 bit binary number 12’hCDF // 12 bit hex number Without base format decimal numbers Without size simulator/machine specific

Identifiers & Keywords wire Write_enable; // wire is a keyword & Write_enable is an

identifier

Logic Values: 0,1 & Unknown Value: X, e.g. Un-initialized value, A net driven by

two primitives High Impedance: Z, e.g. Tristate Buffer, Bi-directional I/O

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reg or net

net

net

net Input InOut

Output reg or net

net

Declaration of wires, regs Instantiation of lower

modules

Dataflow Statements (assign)

wire out; assign out = in1 & in2 wire out = in1 & in2

Procedural blocks Always/initial blocks

(Behavioural statements)

module Sample_Name (a,b,c_o,sum) output reg c_o, sum ; input a,b

endmodule

Rule: Input in a module is always a wire

Port Declaration (Verilog-2001 Style)

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Verilog Operators

Arithmetic operators: +, -, *, /, % Logical operators: &&, ||, ! Bitwise operators: &, |, ~, ^, ^~ Equality operators: ==, !=, Relational operators: >, <, >=, <= Reduction operators: &, ~&, |, ~|, ^ Shift operators: >>, << Concatenation {} Conditional: cond_expr ? true_expr : false_expr

Examples 12

~4'b0001 = 1110

4'b0001 & 4'b1001 = 0001

4'b0001 | 4'b1001 = 1001

& 4'b1001 = 0 // And across all the bits, Can be used to raise flags such as waiting for a 1 from multiple inputs

| 4'b1001 = 1

4'b1001 << 1 = 0010

4'b1001 >> 1 = 0100

{4'b1001,4'b10x1} = 100110x1 // Can be used to concatenate wires/buses

Synthesizing Combinational Logic using Verilog

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Combinational Logic

Output is Boolean function of its input variables on instantaneous basis

“Forgets” its results when the inputs are no longer available

CIL

NAND Structures 15

Any Boolean function can be realized

Transformation of Sum of Products (SoP) to NAND

Put inverter before OR gate & after AND gates

Replace inverted input NOR by NAND

NOR Structures 16

Any Boolean function can be realized

Product of Sum (PoS) Put inverter before AND gate & after OR gates

Replace inverted input AND by NOR

Verilog Design Levels

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Verilog -- Design Levels 18

Gate-Level modelling Verilog gate Primitives

Dataflow Modelling Continuous Assignment using assign statement

Expressions, Operators, Operands

Behavioural Modelling Structured Procedures: Initial & always blocks

Blocking & Non-blocking statements

HLL Higher language constructs (if, switch, case, loops)

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reg or net

net

net

net Input InOut

Output reg or net

net

Declaration of wires, regs

Instantiation of lower modules

Dataflow Statements (assign)

wire out; assign out = in1 & in2 wire out = in1 & in2

Behavioural statements Procedural Assignments

Always/initial blocks Blocking/Non Blocking

Statements

module Sample_Name (a,b,c_o,sum) output reg c_o, sum ; input a,b

endmodule

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reg or net

net

net

net Input InOut

Output reg or net

net

Behavioural statements (always blocks)

LHS must be reg

module Sample_Name (a,b,c_o,sum) output reg c_o, sum ; input a,b

endmodule

reg

reg or net

Dataflow Statements (assign)

LHS must be wire

net

reg or net

Two kind of Assignments Continuous & Procedural

Two kind of Assignments Continuous & Procedural

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Assignment

Continuous (net)

Using assign

Procedural (reg, integer, real, time)

Value placed on a variable will be retained unless modified by another procedural assignment

In always/initial block

Blocking Non-Blocking

Behavioural procedural blocks Initial & always block

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Initial Block Non synthesizable

Used only in stimulus

Multiple blocks execute concurrently

Simulation Starts execution at time t=0

Execute until they come to a #delay operator; delay & than resume

Always block More like HW/ Synthesizable

Can instantiate multiple initial & always blocks

Simulation executes continuously at t = 0 and

repeatedly thereafter

initial begin . . #5 . . end

always begin . . . . . end

Two bit Comparator <CIL> Eg. 4.4, Sec-5.8

A>B A=B A<B A1 B1 A0 B0

0 1 0 0 0 0 0

0 0 1 0 0 0 1

1 0 0 0 0 1 0

0 1 0 0 0 1 1

0 0 1 0 1 0 0

0 0 1 0 1 0 1

0 0 1 0 1 1 0

0 0 1 0 1 1 1

1 0 0 1 0 0 0

1 0 0 1 0 0 1

1 0 0 1 0 1 0

1 0 0 1 0 1 1

0 1 0 1 1 0 0

0 0 1 1 1 0 1

1 0 0 1 1 1 0

0 1 0 1 1 1 1

Design: Compare two bit numbers A & B

Structural Verilog Description Gate Level Model

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Data Flow Model (Continuous Assignment Using relational operators)

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Chapter 6 <Verilog - Samir> operator types

Arithmetic, Logical, Relational, Equality, Bitwise,Shift, etc

Behavioural Model – always block

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Behavioural Model – Even higher abstraction

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Parameterized Coding is Good Parameterized Model

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Xilinx DEMO for a FULL ADDER

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How it goes on FPGA ?

Basic elements:

Configurable Logic blocks (CLB)

I/O blocks

Interconnection wires and switches

Other elements

Memories

Clock Managers

Multipliers, FPU

Processor Cores

Logic Block

I/O Block

Interconnection Switches

CLB CLB

CLB CLB

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Configurable logic block (CLB)

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Xilinx CLB

Programmable Interconnects

16-bit SR

flip-flop

clock

mux

y

qe

a

b

c

d

16x1 RAM

4-input

LUT

clock enable

set/reset

The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Simplified view of a Xilinx Logic Cell

Representation of Combinational Logic : Half Adder

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Boolean (Sum of Products)

sum = a’b + ab’

c_out = a.b

Verilog - Half Adder – Gate level Design

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Verilog - Half Adder – Dataflow Design

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module Add_half ( sum, c_out, a, b );

input a, b;

output sum, c_out;

assign { c_out, sum } = a + b; // Continuous assignment endmodule

a

b

Add_half sum

c_out

Concatenation

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…..DEMO

Hierarchical Design Full Adder

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Verilog - Half Adder – Testing your design

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module test_halfadder;

reg a,b;

wire sum, c_out;

Add_half uut ( // Instantiate the Unit Under Test (UUT)

.sum(sum),

.c_out(c_out),

.a(a),

.b(b)

);

initial begin

// Initialize Inputs

a = 0;

b = 0;

// Wait 100 ns for global reset to finish

#100;

a = 1;

b = 0;

end

endmodule

Reading Assignment 39

Suggested Reading

<Samir> Verilog: Chapter 1-5

Reading Assignment

<CIL> 8.14-8.17

Combinational Logic Building Blocks & their Verilog Coding

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Multiplexers 41

n input datapath; single output datapath

MUX/DEMUX establish dynamic connectivity b/w datapaths

Data Routing

Selecting data from different sources

Example: Selecting data from Functional units in a CPU, TDM

Multiplexer [4to1]

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Symbol

Behavioural Model 4 channel 32 bit mux

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Behavioural Model 4 channel 32 bit mux – using IF

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Priority Structure inferred !!

De-multiplexers 45

Reverse of Multiplexer

Single input datapath; n output datapaths; m nit address

Example: Data to Functional Units in a CPU from Register file

n = 2^m

Encoders 46

Transforms an input word to a different word ….

n-inputs, m-outputs n = 2^m

Usually Reduces the datapath

Can generate a unique pattern for each input line

Examples

Knowing which client is requesting services

Knowing interrupts

Priority ?

0000 00

0001 01

0010 10

0100 11

Assuming only 4 valid/usable combinations

Encoder Verilog

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Decoders 48

Used to understand a decoded information

Examples Comprehending opcode in an instruction and

directing a Functional Unit to act

Locating a word in a memory using row, column address decoding

Decoder 49

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Can u build a CPU out of these Combinational Building Blocks ??

Reading Assignment 52

Suggested Reading

<CIL> Section 2.6,

<Samir> Verilog: Chapter 2-7

Reading Assignment

<CIL> 8.14-8.17

Good Guidelines

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Good References !!!

Good Coding HDL Coding Guidelines for Student Projects, Nestor,

J.A.; , IEEE Conference on Microelectronic Systems Education (MSE), 2011

http://www.inno-logic.com/resourcesTips.html

Interesting Article on Coding Multiplexer in Verilog HDL J. Stephenson and P. Metzgen, "Logic Optimization

Techniques for Multiplexers," Altera Literature, 2004

Good Guidelines 55

Avoid Glue Logic

This may happen after correcting an interface mismatch or adding some missing functionality while debugging the design.

Any such logic should be made part of the combinational logic of one of the constituent modules.

Prevents the synthesis tool from generating a fully optimized logic.

Good Guidelines 56

Design Modules with Common Design Objectives

Avoiding Latches in Combinational Circuit

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module Decoder( input [1:0] opcode, output reg [1:0] decoder_op ); always @ (opcode) begin case(opcode) 2'b01 : decoder_op = 2'b01; 2'b00 : decoder_op = 2'b01; 2'b11 : decoder_op = 2'b10; 2'b10 : decoder_op = 2'b01; endcase end endmodule

Good Straight Coding

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module Decoder( input [1:0] opcode, output reg [1:0] decoder_op ); always @ (opcode) begin case(opcode) 2'b01 : decoder_op = 2'b01; 2'b00 : decoder_op = 2'b01; 2'b11 : decoder_op = 2'b10; 2'b10 : decoder_op[0] = 1'b1; endcase end endmodule

Missed Assignment to one signal

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module Decoder( input [1:0] opcode, output reg [1:0] decoder_op ); always @ (opcode) begin case(opcode) 2'b01 : decoder_op = 2'b01; 2'b00 : decoder_op = 2'b01; 2'b11 : decoder_op = 2'b10; endcase end endmodule

Missed Case

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module Decoder( input [1:0] opcode, output reg [1:0] decoder_op ); always @ (opcode) begin decoder_op = 2'b01; case(opcode) 2'b01 : decoder_op = 2'b01; 2'b00 : decoder_op = 2'b01; 2'b11 : decoder_op = 2'b10; endcase end endmodule

Initialize This is not S/W initialization

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module Decoder( input [1:0] opcode, output reg [1:0] decoder_op ); always @ (opcode) begin decoder_op = 2'b01; case(opcode) 2'b01 : decoder_op = 2'b01; 2'b00 : decoder_op = 2'b01; 2'b11 : decoder_op = 2'b10; default : decoder_op = 2'b10; endcase end endmodule

Best Coding Practice

In summary.. 63

Initialize before the conditional construct in the always block This avoids latches for the situation where we are not assigning

values to a particular reg/signal for a particular condition

Always put DEFAULT (for cases) & ELSE (for if else) This avoids latches that shall/may be inferred by synthesizer when

we miss/forget specifying a particular condition

This may not be required for some synthesizers; but is a good practice.

Though Synthesizers are getting intelligent Still better to follow best practices E.g. Some synthesizers; although they are able to extract Priority

Encoders they may not synthesize it Synthesis reports are good resource

RTL Coding Guideline: Avoid Combinational Feedback

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Avoid Combinational Feedback

The designer must avoid any combinational feedback in RTL coding

LECTURE ENDS…

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