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8/3/2019 ADSD Fall2011 10 Adders
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Dr. Rehan Hafiz Lecture # 10
ADSD Fall 2011
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Course Website for ADSD Fall 2011
http://lms.nust.edu.pk/
2
Lectures: Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm
Contact: By appointment/EmailOffice: VISpro Lab above SEECS Library
Acknowledgement: Material from the following sources has been consulted/used in theseslides:1. [CIL] Advanced Digital Design with the Verilog HDL, M D. Ciletti2. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan3. [STV] Advanced FPGA Design, Steve Kilts4. Ercegovacs Book: Digital Arithmetic 20045. Dr. Shoab A Khans CASE Lectures on Advanced Digital System Design
Material/Slides from these slides CAN be used with following citing reference:
Dr. Rehan Hafiz: Advanced Digital System Design 2010
Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.
http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/8/3/2019 ADSD Fall2011 10 Adders
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Lecture Overview3
Last Lecture Signed/Unsigned Number Representation
Sign Extension, Truncation, Fixed Point Addition
This Lecture
Adders Ripple Carry Adder (RCA)
Pipelined Adder Bit Serial Adder
Fast Adders Carry Select Adders (CSA) Group CLAs Conditional Sum Adders
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RCA Characteristics6
Implements the conventional way of adding twonumbers
Slowestparallel Adder / Takes minimum area
N-bit full adders are required to add two N-bitoperands
Speed is linear with word length O(N)
4 Carry Delays for a 4 bit RCA
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Optimization..7
So how can we optimize for
Throughput
Area
Timing/ Latency
b i h h h
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Remember -- High Throughput
Pipelining using the Delay Transfer Theorem
8
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Remember Area Effcient/Reusing Resources
Bit Serial Adder9
Carry
FA
Sum
Shift reg A
Shift reg B
FF
Shift reg C
Reg C
N
N
Load regA
Load regB
1
1
1
1
1
clk
clk
clk
clk
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Bit Serial Adder (Two adders)10
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Fast Adders11
Pipelined adder is great BUT
Increases the latency
Way to Low Latency Adders
Do we really need to wait for Carries
Pre-compute Carries
OR we can at least start processing the data
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Some observations - RCA12
The ripple-carry adder introduces too muchdelay into a system.
The longest path through the adder is from the
inputs of the least significant full adder to theoutputs of the most significant full adder.
However
the process of summing the inputs at each bitposition is relatively fast (a small two-level
circuit suffices)
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Carry Look Ahead Adder (CLA)13
Generate all incomingcarries in advance
Idea:
A carry is either
generated or
propagated
Carry at ith location
depends on the carry
& inputs at (i-1)th
location & not on the
previous sum
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Carry Look Ahead Adder (CLA)14
Sum and Cout can be re-expressed interms of generate/propagate:
Ci+1 = Gi + Pi CiSi = Ci ^ Pi(^ =xor)
Pi = ai ^ bi
Gi = ai bi
f
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Parallel Look Ahead Generation ofall carries
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CLA look ahead eqs. Ci+1 = Gi + Pi Ci
Si = Ci ^ Pi
Look ahead Carries C1 = G0 + P0C0
C2 = G1 + P1C1
= G1 + P1(G0 + P0C0)
= G1 + P1G0 + P0P1C0
C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 +
P3P2P1P0C0
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16
1-Gate -DelayPi = ai ^ bi
Gi = ai bi
2-Gate -Delayc0 = 0
c1 = G0
c2 = G1 + P1c1c3 = G2 + P2G1 + P2P1c1c4 = G3 + P3G2 + P3P2G1 + P3P2P1c1
2-Gate Delay for aFull Adder
$ Plz. Correct gate notations* Gate delays assuming 1 gate delay for xor gate
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Final Result17
Each of the carry equations can be implementedwith two-level logic
All inputs are now directly derived from data
inputs and not from intermediate carries thisallows computation of all sum outputs toproceed in parallel
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Carry Lookahead Adder
Maximum gate delay for
the carry generation is
only 3. The full adders
introduce two more
gate delays. Worst
case path is 5 gate
delays (To final sum
bit to be generated !)
In general, the maximumfan-in/out of any gate in ann-bit CLA is n. Thus, the
maximum fan-in of any gate
in a 16-bitCLA is 16.
F d t l f di it l l i ith V il
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Fan IN/OUT Effects
19
Fundamentals of digital logic with Verilog
design
By Stephen D Brown
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CLA20
As n increases Fan IN/OUT becomes an issue
Options
Ripple the carry across
blocks(groups) of CLAadders of limited size
Or we may againpre-compute in parallel
Group Carry of each block
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Group Carry Look-ahead Adder
A16-bit GCLA is composed of four 4-bit CLAs, with additional logic that
generates the carries between the four-bit groups.
GG0 = G3 + P3G2 + P3P2G1 + P3P2P1G0
GP0= P3P2P1P0
c4 = GG0 + GP0c0
c8 = GG1 + GP1c4= GG1 + GP1GG0 + GP1GP0c0
c12 = GG2 + GP2c8= GG2 + GP2GG1 + GP2GP1GG0 +
GP2GP1GP0c0
c16 = GG3 + GP3c12= GG3 + GP3GG2 + GP3GP2GG1 +
GP3
GP2
GP1
GG0
+ GP3
GP2
GP1
GP0
c0
No carries are required to generateGroup G & Group P
We just needsingle-xor-gate-delay G & P signals !
Total Delay = 3 Gate Delays for GG/GP
To generate carries just use Group G & Group Pwith 2 Gate Delays
Red part will constitute Ripple based Group CLABlack Part will result into CLA based GCLA
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16-Bit Group Carry Lookahead Adder
Each CLA has a
longest path of
5 gate delays
In the GCLL section, GG and GP signals are generated in 3 gate delays; carry signals
are generated in 2 more gate delays, resulting in 5 gate delays to generate the carry
out of each GCLA group and 10 gates delays on the worst case path (which is s15
not c16).
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Carry Select Adder24
Partition the adder into K groups
Two values of sum with cin (1 and 0) areprecomputed for each adder group
Actual sum is selected using a 2-to-1 MUX by thecarry of the previous group
Allows computation of possible results in
parallel Requires internal carry for blocks, e.g. ripple
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Carry SelectAdder25
Three partitions have been made of 4 bits each
Outputs of each 4 bit adder block would be readysimultaneously including the Cout of the first adder
Cin = 04 - bit Adder
Cin = 14 - bit Adder
Cin = 14 - bit Adder
Cin = 14 - bit Adder
Cin = 04 - bit AdderCin = 04 - bit Adder
4-bit 2-to- 1 Mux2-to-1Mux
4-bit 2-to- 1 Mux 4-bit 2-to- 1 Mux2-to-1Mux
2-to-1Mux
C C C0 0 0
CC C1 1 1
S S S
S S S1
0
1 1
0 0
Carry in
Cout[3]Cout[7]Cout[11]
SUM [11-8] SUM [7-4] SUM [3-0]
N U if G C S l t
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Non Uniform Group Carry SelectAdder
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Delay: Approx. 5RCA Delay + 2-to-1 Mux Delay
1 1 1 1 1 0 1 1 1 1 0 0 (a)
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CSA: Example27
( )
1 1 1 1 1 1 0 1 0 0 1 1 (b)
1 1 1 1 0 0 0 0 1 1 1 1 (cin=0)
1 1 1 1 1 0 0 1 0 0 0 0 (cin=1)
100
0110
1
0
1
1
1
10111
1010
11111
11111
0
1
1
111000111111
1 1 1000000100101111011111
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If we keep on reducing the number of bits peradder we reach Conditional sum adder
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Conditional sum adder
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References & Further Reading30
Ercegovacs Book: Digital Arithmetic 2004
Another Useful Link
http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algori
thm.html