POLITECNICO DI MILANO

A SystemC-based methodology for the simulation of dynamically

reconfigurable embedded systems

DDynamic ynamic RReconfigurability econfigurability inin EEmbeddedmbedded SSystemsystems DDesignesign

Chiara Sandionigi: chiara.sandionigi@dresd.org

Relatore: Prof. Donatella Sciuto

Correlatore: Ing. Marco Domenico Santambrogio

22

Basic concepts and Basic concepts and MotivationsMotivations

Basic conceptsDynamically reconfigurable computing: the ability

of altering a microarchitecture, once it has been deployed and during the execution of the system, to meet at the best the execution mode of object codeTarget device: FPGA

MotivationsModeling and verification of dynamically

reconfigurable embedded systemsDefinition of a validation phase representing a

bridge between high level specification phase and low level implementation phase

33

GoalsGoals

Innovative contributionsDefinition and implementation of a methodology

for the simulation of dynamically reconfigurable embedded systems

System modelingArchitecture validationApplication verificationDesign space exploration

Definition of the validation phase inside a complete design flow for dynamically reconfigurable embedded systemsSystem management during simulation execution

.:: No support in the state of the art ::.

44

OutlineOutline

SyCERSModeling of reconfigurationArchitectureIntegration in EarendilIntegration in ReSP

Experimental resultsSetup and main resultsDESMD5Canny

Conclusions and future work

55

SyCERS: Modeling of SyCERS: Modeling of reconfigurationreconfiguration

SyCERS: SystemC-based simulator for dynamically reconfigurable embedded systemsModeling of reconfiguration exploiting SystemC module’s structure

sc_method/sc_thread/ sc_cthread

sc_module

66

SyCERS: ArchitectureSyCERS: Architecture

Dynamic loading of applicationsApplications running on processor of FPGA

77

SyCERS: Integration in SyCERS: Integration in EarendilEarendil

Definition of a phase for the validation of dynamically reconfigurable embedded systemsDefinition of a complete design flow

88

SyCERS: Integration in ReSPSyCERS: Integration in ReSP

Simulation platform built using Python, SystemC and C++ programming languagesAim: create mechanisms to connect and analyze SystemC components and to manage simulationExploitation of ReSP reflective capabilities for system management during simulation execution

introspection inside the componentsmonitoring of the status of the componentsmodification of the status of the componentsrun-time composition of the architecture

99

Experimental results: Setup and main Experimental results: Setup and main resultsresults

System setupIntel Core Duo 2 GHz processor, 1 GB memory and

Mac OS X 10.5.5 operating systemApple GCC version 4.0.1SystemC version 2.2

Case studiesDES: parallelism exploitation for the exploration of

solution spaceMD5: algorithm structure exploitation for the

evaluation of reconfiguration timeCanny: algorithm structure exploitation for the

evaluation of dynamic reconfiguration

1010

Experimental results: DESExperimental results: DES

Input parameters for DES applied to 1,28 kb fileMemory size: 500 kBMemory reading time: 30 nsMemory writing time: 30 nsReconfiguration time: 3 ms

RFU Ops Activity

T (ns)

A 2 0,381 4020

B 8 1 10560

C 8 1 10560

D 7 0,898 9480

RFU Ops Activity

T (ns)

A 2 0,163 4020

B 21 1 24600

RFU Ops Activity

T (ns)

A 2 0,291 4020

B 11 1 13800

C 11 1 13800

1111

Experimental results: MD5Experimental results: MD5

Input parameters for MD5 applied to 512-bit blockReconfiguration

time: 2,932 ms

Operation Time (ms)

Reconfiguration A 2,932

Elaboration A 0,274

Reconfiguration B 2,932

Elaboration B 0,144

Reconfiguration C 2,932

Elaboration C 0,144

Reconfiguration D 2,932

Elaboration D 0,168

Reconfiguration E 2,932

Elaboration E 0,144

Total 15,534

Reconfiguration T 14,66

Elaboration T 0,874

1212

Experimental results: CannyExperimental results: Canny

Input parameters for Canny applied to 16 kb fileMemory size: 500 kBMemory reading time: 30 nsMemory writing time: 30 nsReconfiguration time: 3 ms

RFU Ops Activity T (ns)

A 8 1 26700

RFU Ops Activity

T (ns)

A 4 1 13350

B 4 1 13350RFU Ops Activit

yT (ns)

A 4 1 11880

B 2 0,624 7410

C 2 0,624 7410

1313

Conclusions and future workConclusions and future work

Definition and implementation of a methodology for the simulation of dynamically reconfigurable embedded systemsDefinition of the validation phase inside a complete design flow for dynamically reconfigurable embedded systemsSystem management during simulation execution

Future workAdd flexibility in terms of scheduling policies choiceTake into account the problem of modules placement for dynamically reconfigurable systems based on FPGA

1414

QuestionsQuestions