A Study on Process and Device Structure for Schottky and Heterojunction Tunnel FETs 

using Silicide‐Silicon interface

Tokyo Institute of Technology

Supervisor: Akira NishiyamaSub‐supervisor: Hiroshi Iwai

Yan Wu

2014/2/6 Final defense presentation

1

PON+POFF=(Ion+Ioff)VDD

Introduction

SS値低減によるIOFFの減少

Vdd

LogId

ION

VG

IOFF

印加電圧の低減

T. Sakurai, IEICE Trans. Electron., Vol.E87‐C, April 2004, pp. 429‐436.

Increase in subthreshold leakagecurrent is a major issue at scaled devices.

2

Scaling in conventional FETG.Bidal et.al., Silicon Nanoelectronics Workshop (SNW), 2009.

3

Mobility enhancement planar: 3D: 

G. Tsutsui, et al., IEDM., pp. 729‐732 (2005) 

Gate

Gate G

ate

SiSi

EC

Less interface roughness scattering in 3D 

Si nanowire  

1E-6

1E-5

1E-4

1E-3

1E-2

1E-1

1E+0

0E+0 5E+2 1E+3 2E+3 2E+3

Normalized ION (A/m)N

orm

aliz

ed I O

FF (n

A/

m)

0 500 1000 1500 2000

1000

100

10

1

0.1

0.01

0.001Lg=500~65 nm

hNW=12 nm

wNW: 19 nm

39 nm28 nm

better electrostaticcontrollability

Higher ION/IOFF ratio

S. sato, et al.,  Solid‐State Electron. 2010;54(9):925‐928.

Potential 1D ballistic transportation   

K. Natori, IEEE Trans. Elec. Dev.,vol 55,  no. 11 (2008) 

Injection velocity is the dominant limiting factor for drain currentat scaled devices.

Scaling today 

Jesus del Alamo, Nature, 2011

Supply voltage scaling can be expected by using III‐V compound semiconductors(higher electron injection velocity) atn‐MOSFET channels.

Cost and process are main issues.

4

Nanowire, multi‐gate MOSFET・reduce the short channel effect・improve gate field effect

S value reaches the limit value of 60eV/dec.

Ion/Ioff <107 , S~62–75 mV/dec and low DIBL (20mV/V)

Ioff savings compared to bulk CMOS Current per NW: ~1µA ‐>need arrays

W. W. Fang et al, IEEE Electron Device Letts.,Vol. 28, March 2007.

Scaling Today

Motivation for this Research 

It is important to increase ON/OFF ratio to reduce device power consumption use new injection mechanism

Subthreshold factor has a lower bound of 60mV/decade in conventional MOSFETs

decademVC

CCq

kTId

dVS

ox

dox

d

G

/603.2

ln)10ln(

Source Channel Drain

Gate voltage

Drain votage

Conventional MOSFET

5

Low subthreshold voltage is desirable for the ease of switching the transistor off.

FETs with new mechanism and principle 

IMOS 

Crystallization of ferroelectric material, causes ,Strain on bottom dielectric layer and increase Leakage current. 

Feedback FET

K.Gopalakrishnan, P.B. Griffin, and J.D. Plummer, IEEE Trans. Electron Dev., 52(2005), 69

A.Padilla, C.Yeung, C. Shin, C. Hu, and T.-J. King Liu, Tech Dig. IEDM,2008,171.

Reliability issues due to using avalanche effect at dielectric vicinity

Negative capacitanceG. A. Salvatore, et al., IEDM.2008.4796642

6

Advantages of Tunnel FET for steep S‐factor

TunnelFETP‐source N‐channel

Tunneling injection

Main Challenge of TFETp+in+ Si‐TFET has high tunnel resistivity  ON current is degraded due to high resistance

T. Schulz, MOS‐AK/GSA Workshop, Apl. 2013

BTBT

7

Carrier injection occurs only when sourceand channel have equal potential Steep ON/OFF ratio is possible

Recent examples of Tunnel FET

Tejas Krishnamohan, et al.,IEDM2008, p.947.

The highest experimental ON current value of10‐4A/m is achievedby using III‐V compound semiconductor. (complicated process)

D.K.Mohata, S.Datta, et al., IEDM Tech. digest, 11‐781(2011)33.51

S‐factor below the 60mV/dec.was achieved however, ON current is small

8

Schottky, Heterojunction S/D

Conventional doping S/D

Hardmask

Gate

Source Drain

Source Drain

Lphy

Dop

antC

onc.

y position

Gate

Gate

(a)Hardmask

Gate

Source Drain

Source Drain

Lphy

Dop

antC

onc.

y position

Gate

Gate

(a)

Gate

Metal Metal

Metal Metal Met

al C

onc.

y position

Gate

Lphy = Leff

Gate

(b) Gate

Metal Metal

Metal Metal Met

al C

onc.

y position

Gate

Lphy = Leff

Gate

(b)

Issue of Short channel effect

MOSFET scaling

Advantage of Silicide S/D

Silicide S/D

J. M. Larson et al., T-ED, 53, 1048 (2006).

NiSi (metal), Mg2Si (semiconductor)W. Mizubayashi et al., VLSI symp., 88 (2011).N. Mise et al., T-ED, 55, 1244 (2008).

Controllability of impurity distribution in S/D region

9

- abrupt and shallow junction- robust against short-channel effect- low resistance- low temperature process

Silicide Schottky S/D is a candidate for scaled FETs

Silicide Schottky source/drain (S/D) FETs

Vg

ITH

ITNBE

z

Thermionic tunneling Band to band tunneling

Concept of Schottky junction device

・abrupt + low defect junction ・lower tunnel resistivity＋contact optimization

ITN

By using silicide material for MOSFET source region

10

1. Introduction 

2. Detail of Simulation and device process

7.conculusion

4. Schottky contact and barrier height alignment 

5. Band Discontinuities at Source‐Channel Contact in Tunnel FET 

Performance6. Heterojunction Tunnel‐FET using Semiconducting silicide‐Silicon 

contact and its scalability 

3. Evaluation of Schottky contact MOSFET with considering 

structure parameter  

X. Semiconducting silicide/ Si hetero junction Schottky contact tunnel FET

Heterojunction tunnel FET

11

Purpose of this Research

Propose source contact guidelines and process for Tunnel FETs using low defect Schottky contact technology.

Investigating structure parameters of band‐to‐band Tunnel FET with discontinuous junction.

12

p‐SOI

BOX

conductor

Schottky contact

100nm 100nmGate Length(nm)

Ohmic contact

Gate oxide 0.3nm

6nm

1000nm

Vg

ITH

ITNB

２D Simulation Design

Thermionic emission and tunneling emission were used to calculateinjection current at the Schottky junction.

13

Device structure was based on FDSOI platform to minimize short channel effects. 

K. Matsuzawa, et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 1, 2000

Lombardi CVT Model: Matthiessen’s rule

Lombardi et al, “A Physically Based Mobility Model for Numerical Simulation of Non‐Planar Devices”, IEEE Trans. on CAD (Nov.  1988): 1164.

AC scattering with acoustic phonons

sr The second component, µsr, is the surface roughness 

b scattering  with  optical intervalley phonons

SRH Concentration‐Dependent Lifetime Model Shockley‐Read‐Hall (SRH) Recombination 

Trap Assisted Auger Recombination

semiconductor bandgap  narrowing 

Includes  the  effects  of  Fermi  statistice  into  the  calculation  of  the intrinsic concentration in expressions for SRH recombination.

Martsuzawa model

Schottky barrier Tunneling FET – Calculation model

14

(b)

Injection incrementlarge 

small Injection increment

5x1018cm‐3

2x1019cm‐3

0.61eV

0.61eV

Potential (V)90

80

70

60

50

40

30

20

104

10‐1

10‐6

10‐11

10‐16

10‐21

‐0.2       0.2      0.6       1.0       1.3

5x10188x10181x10192x1019

Na(cm‐3)

Subthreshold slop (mV/dec.)Drain current den

sity (A

/m)

Gate Voltage (V)

2D simulation （Channel concentration）Gate oxide

SOI

Metal so

urce

Vg=0.45V

VD= 1.0V L=100nm

15

Higher channel doping concentration leads to Steep potential barrier increase tunneling probability

Tunneling rate (/cm‐3s)

logarithm

Injection increment

large 

small 

Injection increment

0.81eV

0.41eV

VG=0.45 (V)    0.55 (V)

90

80

70

60

50

40

30

20

104

10‐1

10‐6

10‐11

10‐16

10‐21‐0.2       0.2      0.6       1.0       1.4

0.410.610.81

B (eV)

Gate Voltage (V)

Subthreshold slop (mV/dec.)Drain current den

sity (A

/m)

Lower , leads to higher volume Injection lower S-factor can be achieved

VD= 0.3V L=100nm

16

2D simulation （ B ）

5 10 15 20 25

SS (m

V/de

c.)

V th(V) 

5       10      15     20     25

150

120

90

60

300

‐0.2

‐0.4

Conv. FETSBTFET

VTH=Vg(ID=10‐7A/m)

Gate length (nm)

VG=F.B.

VD=0.3V

VD=0.3V

Gate potential loweringby short channel effect

Long channel Short channel 

SBTFET

Conv. FET

2D Simulation（conventional vs SHBT-FET）

Degradation of S‐factor and Vth roll‐off can be suppressed at smaller channel lengths for SBHT‐FET compared to conventional FET. 

101

10‐1

10‐3

10‐5

10‐7

10‐90        0.4      0.8       1.2      1.6

102050

Lgate(nm)

Subthreshold slop (mV/dec.)Drain current den

sity (A

/m)

100

80

60

40

20

0

Gate Voltage (V)

Conv. FETSBTFET

B: 0.6eV, Na: 2x1019

VD= 0.3V

17

Channel potential lowering by SCE

101

10‐1

10‐3

10‐5

10‐7

10‐9

0.4      0.6      0.8       1.0      1.2

Subthreshold slop (mV/dec.)D

rain current den

sity (A

/m)

Gate Voltage (V)

0.210.410.610.81

B (eV)

140

120

100

80

60

40

20

101

10‐1

10‐3

10‐5

10‐7

10‐9

0.4      0.6      0.8       1.0      1.2

Subthreshold slop (mV/dec.)D

rain current den

sity (A

/m)

Gate Voltage (V)

140

120

100

80

60

40

20

5x10188x10181x10192x1019

Na(cm‐3)

2D Simulation (short channel)

Higher B results in improved S-factor for short channel

VD= 0.3V L=10nm

VD= 0.3V L=10nm

18

Increasing channel doping concentration leads to smallerS-factor (same as long channel trend)

Gate length (nm)

SS (m

V/de

c.)

I on/I of

fRa

tio 

5       10      15     20     25

120

100

80

60104

103

102

0.210.410.610.81

B (eV)

VG‐VTH=0.5VConv. SOIFET

At Lg～15nm B and S-factor relation is reversed.

2D Simulation (short channel summary)

19It is important to modulate B according to channel length.

Conclusion – Chapter 3

Higher channel doping concentration results in shallow Schottky depletion layer. This leads to higher tunneling probability and improved S‐factor.

Barrier heights need low Long Channelhigh Short Channel（10nm）

20

For short channel devices, SBHT‐FET can suppress electric field penetration and prevent S‐factor degradation.

S‐factor and Ion/Ioff ratio optimization 

21

Morphology problemdue to agglomerationtNi

(nm)

4nm

Annealing temperature (oC)500400300 800

NiSi2

NiSi

NiSi2

Ni-richphase

NiSi+NiSi2

BOX

Issues in silicide reaction ~ chapter 4

M. Koyama et al., ESSDERC, 231 (2011).

Pattern dependentinterface reaction

Control of silicide phase and interface reaction with wide process window is required for silicide Schottky S/D FETs.

Thickness dependentsilicide phase change

K. Tsutsui et al., Microele. Eng., 85, 315 (2008).

L. Knoll et al., EDL, 31, 350, (2010).

22

・・・

n-Si(100)B

Si/Nix

8 layers ・・・

n-Si(100)Ni3P

Si/Nix

7 layers

(Ni:0.5nm/Si:1.9nm) x 8

(Ni:0.5nm/Si:1.9nm) x 7 + (Ni3P:0.68nm/Si:1.9nm)

(Ni:0.5nm/Si:1.9nm) x 8 + B:0.13nm

・・・

n-Si(100)

Si(1.9nm)/Ni(0.5nm)

x 8 layers

Schottky diode fabrication process

SPM and HF cleaning

Deposition by RF sputtering

RTA: 1min in N2 (silicidation)

n-Si(100) Sub with 400 nm SiO2 (3x1015 cm-3)

Diode patterning

Backside Al contact

BHF etching of SiO2

Impurity incorporating

Ni/Si stacked structure

23

stack case

NiSi2Si Fin

No encroachmentBOX

SiNiSi2

Ni Ni silicide

BOX

Si Fin

Ni silicideencroachment

Ni

Interface reaction of stacked silicidation process

- atomically flat interface and smooth surface

- no thickness change before and after annealing

- interface position can be well-defined

Cross sectional TEM Silicidation with narrow Fins

Ni case

Stacked silicidation process is candidate for silicide Schottky S/D.

24

Schottky barrier height (Bn) modulation

Dopant segregation with silicidation

Control of dopants and junction position are the key.

A. Kinoshita et al., IWJT, 34 (2009).

Dopant segregationby activation anneal

W. Mizubayashi et al., VLSI symp. (2011).

25

Bn

(eV)

1.00

0.70

1.10

n-fa

ctor

1.20

400 600Annealing temperature (oC)

800200

0.50

RTA : 500oC, 1min in N2

P: Ohmic

ControlB

Control

B

104

102

10-2

10-4

-1 -0.8 -0.6 -0.4 -0.2 0 0.2

Cur

rent

den

sity

(A/c

m2 )

Applied voltage (V)

100

Control: 0.63 eV

P: Ohmic

B: 0.68 eV

RTA : 500oC, 1min in N2

10-6 n-Si(100)B

NiSi2

n-Si(100)P

NiSi2

n-Si(100)

NiSi2

Bn modulation by P or B incorporation

Stable property withwide process window

Bn modulation is confirmed.

Bn modulation is achieved by impurity incorporation at interface with stacked silicidation process.

Diode characteristics Dependence ofannealing temperature

26

BOXSOI

stackedsilicide

metaloxide

-3 -2 -1 0 1 2 3Gate voltage (V)

10-5

10-7

10-11

10-13

Dra

in c

urre

nt (A

)

10-9Vd = 3 V

Vd = 3 V

Vd = 0.1 V

W/L=6.0/1.5mTSi=30nmTox=76nm

Vd = 0.1 V

PB

n-Si(100)B

NiSi2

n-Si(100)P

NiSi2

Ambipolar characteristics is suppressed by P incorporating.

SOI-silicide Schottky S/D FETFabrication process

Bn modulation was also confirmed with FET operation.

Id-Vg characteristicsSOI patterningGate oxide (1000 oC)Stacked silicide for S/D

TEOS (200 oC)Gate metal depo./etch.ContactFG anneal (500 oC)

(with B or P)

The process temperature was set below 500 oC except for gate oxide formation.

27

Conclusions chapter 4

- atomically flat silicide/Si interface

- junction position is well-defined

- stable property up to 850 oC annealing

- Bn modulation is achieved by P or B incorporation at interface (ohmic ~ 0.68 eV)

- suppression of ambipolar characteristics with silicide Schottky S/D FET

Schottky barrier height (Bn) modulation

Ni/Si stacked silicidation process

Conclusion – Chapter 3、4

Schottky barrier built in potential can suppress electric field penetration. This prevents degradation of S‐factor and ON/OFF ratio at short channel 

device. Stack layer spattering could form atomic flat silicide with barrier height 

moderate

The majority injection of SBHT‐FET is due to thermionic emission, Therefore the S‐factor has a lower limit of 60mV/dec.

To achieve lower S‐factor with high ON/OFF ratio, the majority injectionMust be due to tunneling emission.

28

Moderate the barrier height process and the SHBT‐FET device design had proposed 

1. Introduction 

2. Detail of Simulation and device process

7.conculusion

4. Schottky contact and barrier height alignment 

5. Band Discontinuities at Source‐Channel Contact in Tunnel FET 

Performance6. Heterojunction Tunnel‐FET using Semiconducting silicide‐Silicon 

contact and its scalability 

3. Evaluation of Schottky contact MOSFET with considering 

structure parameter  

X. Semiconducting silicide/ Si hetero junction Schottky contact tunnel FET

Heterojunction tunnel FET

29

Drive current imaging in Tunnel FET 

Energy barrier (E)： material of source and channelTunnel width(z)： electric field apply and 

E

z

・Lower E improve ON current・Interface need more abruptness

30

Applying Band Discontinuity Concept in a FET

ChannelSource

Gate

Gate length

: Conductor

BOX

p+ poli‐Si n‐Si10nm

Gate oxide 0.3nm

Tunnel height is determined by material, Tunnel width is determined by band discontinuity 

Band offset effect is investigated by same band gapmaterial.

Source‐ Channel p+‐n junction

31

Nonlocal band to band tunneling:

J(E)

Lombardi CVT Model: Matthiessen’s rule

Lombardi et al, “A Physically Based Mobility Model for Numerical Simulation of Non‐Planar Devices”, IEEE Trans. on CAD (Nov.  1988): 1164.

AC scattering with acoustic phonons

sr The second component, µsr, is the surface roughness 

b scattering  with  optical intervalley phonons

SRH Concentration‐Dependent Lifetime Model

Shockley‐Read‐Hall (SRH) Recombination 

Trap Assisted Auger Recombination

semiconductor bandgap  narrowing 

Includes  the  effects  of  Fermi  statistice  into  the  calculation  of  the intrinsic concentration in expressions for SRH recombination.

Band to band Tunneling FET – Calculation model

32

Subthresho

ldsw

ing(mV/de

c.)

Gate voltage (V)

0

20

40

60

80

100

0.4 0.5 0.6 0.7

Ev= 0 ‐> 0.6 (eV)1.E‐17

1.E‐15

1.E‐13

1.E‐11

1.E‐09

1.E‐07

1.E‐05

1.E‐03

0.4 0.6 0.8 1.0 1.2Gate voltage (V)

Drain curren

t (A/m

)

EV= EC=0 ‐> 0.6eV

Effect of Band Discontinuity 

Increased band discontinuity can improve S‐factor and ON current.

VD=1.0V Lg=100nm 

Nd= 1x1017cm‐3

Tunnel width dependence on band discontinuityIs a key factor for improving TFET performance. 

33

Band Discontinuity using Silicide/Si 

Silicide semiconductor has small band gap (EG) and large ΔEV is used for source region.

Choosing appropriate EG, is necessary for improving ON current in TFET

Semiconductor ‐ Basic Data 2nd Edition , O.Madelung, Springer, , T. Suemasu, et al., JJAP 45 (2006) L519, M. Baleva et al., ECSTransaction 8 ,1 (2007) p.151

Improving ON current by using III‐V hetero‐junction is possibleD.K.Mohata, S.Datta, et al., IEDM Tech. digest, 11‐781(2011)33.51

Surface

p+

n

E g Ev Surface

Ec

n

p+

34

EC

EV

p+‐SiEG

EG

p+‐Mg2Si

n‐Si

n‐SiChannelSource

Gate

Gate length

: Conductor

BOX

p+‐Mg2Si n‐Si

・source concentration 1×1020cm‐3

・channel concentration  1015~1018cm‐3

・oxide thickness : tox 0.3 nm・SOI thickness    40nm・gate length : Lg 20,100nm

10nm

Gate oxide 0.3nm

As semiconductor with similar characteristics to Mg2Si（EG, dielectric constant、electron density）、was used in a FSOI structure to evaluate TFET electrical properties.

Silicide/Si Tunnel FET Design

35

Gate voltage(V)Subthresho

ldSlop

e, SS (m

V/de

c.)

Gate voltage(V)

10‐2

10‐5

10‐8

10‐11

10‐14

10‐170 0.2 0.4 0.6 0.8 0.30 0.1 0.2

80

70

60

50

40

30

20

10

0

Drain current (A

/m) p+‐Mg2Si/n‐Si

VD=1.0V Lg=100nm 

Nd= 1x1017cm‐3p+‐Mg2Si/n‐Si

p+‐Si/n‐Si

p+‐Si/n‐SiVth=Vg|Id=1x10‐8(A/mm)

Vth=0.1V, 0.5VSS(mV/dec.)=6.5,23.6

p+‐Ge/n‐Si

p+‐Ge/n‐Si

Vg (V)=0.10‐0.16

Vg (V)=0.18‐0.24

Silicide/Si Tunnel FET Design

Lowest S‐factor and highest ON current can be achieved by Mg2Si/Si Tunnel FET

36

Gate voltage(V)

Tunn

eling width (n

m)

p+‐Mg2Si/n‐Si

p+‐Si/n‐Si

0.250.200.150.10 0.30

25

20

15

10

5

0

A sharp decrease in tunneling width is observed for MgSi2/Si junction

S‐factor and ON current are simultaneously improved.

Silicide/Si Tunnel FET Design

37

Gate voltage(V)

Drain current (A

/m)

Lg=20nmLg=100nm

1×10181×10171×10161×1015

Channel conc.(cm‐3)

10‐2

10‐5

10‐8

10‐11

10‐14

10‐170 0.2 0.4 0.6 0.8

6

8

10

12

Tunn

eling width (n

m)

Gate voltage(V)

1x1015

1x1016

1x10181x1017

Lg=20nm,Vd=1.0V

0.250.200.150.10 0.30

Channel conc.(cm‐3)

VD=1.0V

Silicide/Si Tunnel FET Design

38

S‐factor is degraded for short channel devices due to electric fieldpenetration 

S=40 (mV/dec.)

Tunneling width change due to gate voltage is smaller for channels with high doping concentration.

Drain curren

t (A/m

)

Gate voltage(V)0 0.2 0.4 0.6 0.8

Lg=100nm  Nd= 1x1017cm‐3

Lg=20nm  Nd= 1x1017cm‐3

Vd (V)= 0.1‐1.0

Vd (V)= 0.1‐1.0

10‐2

10‐5

10‐8

10‐11

10‐14

10‐17

Drain curren

t (A/m

)Gate voltage(V)

0 0.2 0.4 0.6 0.8

10‐2

10‐5

10‐8

10‐11

10‐14

10‐17

Silicide/Si Tunnel FET Design

39

Drain electric field penetration to channel is reduced for lowerdrain voltages.Same drain current can be achieved regardless of channel length.

Silicide/semiconductor Tunnel‐FET Design

40It can optimize the apply voltage at 0.3 V

Degradation of On current and S‐factor has limited in 1 degrade and  10 % 

41

Delay time Compare to TFET and Conv.

TFET’s delay time is lower than conventional below Vg=0.8V, due to TFET has high ON/OFF ratio

42

TFET Compare of Simulation and Experiment 

The simulation belong in the Two popular published experiment device

Experiment

Experiment

simulation

43

Germanium Silicon

Tunnel injection concept of probing analysis

IV‐semiconductor and III‐V compound semiconductor has deferent wave vector and band gap 

The tunnel injection need consider with phonon scattering and various energy potential 

Nest step:

44

Mg2Si formation and oxidation 

Mg2Si 380nm, Annealing with Ar gas, 5hMBE, sputtering  deposition has been reported, MgO has formed in Mg2Si/Si interface.

Y. Wang, et al., JOURNAL OF APPLIED PHYSICS 102, 126102  2007  Xiao Qingquan et al., J. Semicond. 2011, 32(8)

MgO had formed in MgSi substrate above 400oC

Mg2Si p‐type formation

Mg65.2Si33.3Na1.5 (p)

Mg66.7Si32.8Ag0.5 (p)

丹 羽 陽 亮 他 日本金属学会誌 第 72 巻 第 9 号(2008)693‐697M. Akasaka , et al., JOURNAL OF APPLIED PHYSICS 104, 013703 2008

P‐type can be achieved by doping Na, Ag during Mg2Si deposition

45

III‐V Poor S factor, High ON current

Si, Ge Steep Subthreshold response, poor ON current 

ON current is increased to due low electron effective mass in III‐V material

It is necessary to achieve high ON current with steep S‐factor, for Tunnel FET in Si  (large effective density of states)

46

Chapter 6, 7・Comparison to Literature

First demonstration of Si‐based Hetero‐junctionTunnel FET feasibility 

Lattice mismatch occurs for III‐V basedHetero‐Junctions

47

Chapter 6, 7 Conclusions

Tunneling FET with band discontinuity and lower bandgap  

Large Band discontinuity lead shorter tunneling width, that improve high ON current, lower S‐factor

Semiconducting silicide has lower bandgap,Mg2Si/Si achieved higher ON current and lower S‐factor than Ge/Si, Due to larger band offsets.

At short channel, TFET has degradation of  S‐factor due to drain electric field penetration.   optimization at Vd=0.3 V, Lg=20 nm

48

Summary‐Conclusion

Thermionic tunneling

Band to band tunneling

L.  Michielis et al,. IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 6, JUNE 2013

E

z

Vg

ITH

ITNB

Proposed a model for achieving low power consumption Tunnel FET. 

49

SummaryLgate

Ion (V/m) Ion/Ioff SS

pnconventinal

Long（100nm）

short（10nm）

Thermionic FE(Cha. 3,4)

Schottky tunnel

Long（100nm）

short（10nm）

Zenner(Cha. 5,6)

B to B tunneling

Long（100nm）

short（20nm）

Short（20nm VD=1.0）

（hypothetical10nm）

1.8x102

5.5x103

150

60

60

120

10

15

43

3.0x109

5.0x106

300

300

300

680

567

50

Target and benchmarking Ohta et al., AIST Japan GNC symposium 2013 

ON current and minimum S‐factor are Key factor of benchmarking

Trendy line is lower S‐factor has smaller ON current

51

1000

100

1

10

0 20 40 60

[2] [3]

[4]

[4]

SOI‐Conv.[5]

Mg2Si/Si 

Ge/Si

Si/Si

Minimum SS (mV/dec.)

ON current (

A/m

)

GaSb/InAs hetero‐junc.

AlGaSb/InAs hetero‐junc. 

This work

This work

This work

This work

InAs/InAs homo‐junc.

1.E‐13 1.E‐11 1.E‐09 1.E‐07

1000

100

1

10

[2] [3]

[4]

[4]

SOI‐Conv.[5]

Mg2Si/Si 

Ge/Si

Si/SiON current (

A/m

)

GaSb/InAs hetero‐junc.

AlGaSb/InAs hetero‐junc. 

This work

This work

This work

This work

InAs/InAs homo‐junc.

OFF current (A/m)

VON=Vth+0.3VVOFF=Vth‐0.3VVON=Vth+0.3V

Vd=0.3V, Lg=20nm TFET

The performance is considered to be comparable of highly‐scaled III‐V hetero‐junction TFETs

Benchmarking

Yan. Wu et al.,“Influence of Structural Parameters on Electrical Characteristics of SchottkyTunneling Field-Effect Transistor and Its Scalability”Japanese Journal of Applied Physics, Volume 52, Number 4, 04CC28

Yan. Wu et al.,“A novel hetero-junction Tunnel-FET using Semiconducting silicide-Silicon contactand its scalability”Submitted to Microelectronics reliability

52

Journals

Paper publish list of this thesis

53

“Influence of Structural Parameters on Electrical Characteristics of Schottky Tunneling Field-Effect Transistor and Its Scalability”International Conference on Solid State Devices and Materials (SSDM 2012)

“Influence of Band Discontinuities at Source‐Channel Contact in Tunnel FET Performance”2013 International Workshop on DIELECTRIC THIN FILMS FOR FUTURE ELECTRON DEVICES (IWDTF2013)

International Conference (peer review)

54

“Observation of tunneling FET operation in MOSFET with NiSi/Si Schottky source/channel interface”218th Electrochemical Society (ECS) Meeting

“Observation of NiSi/Si Schottky source/channel interface electrical characteristic”Taiwan-Japan Workshop "Nano Devices"

“An analytical model of a tunnel FET with Schottky junction”G-COE PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano Devices (IS-AHND)

“The tunnel FET with schottky contact simulation”Tsukuba Nanotechnology Symposium 2011

“Size dependent resistivity change of Ni-silicides in nano-region”Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology

“A Study on Fabrication and Analytic Modeling of novel Schottky contact tunneling Transistors”IEEE EDS MQ WIMNACT 32

“Influence of Structural Parameters on Schottky Tunneling Field-Effect Transistor”Tsukuba Nanotechnology Symposium 2012

“Electrical Analyses of Nickel Silicide Formed on Si Nanowires with 10-nm-width”International Symposium on Next-Generation Electronics (ISNE 2013)

“A study of Band offset in Source-Channel Contact improve Tunnel FET Performance”Tsukuba Nanotechnology Symposium 2013

Other conference

55

Thank you very much