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Fabrication and Characterisation of Platinum Silicide (PtSi-Si) Schottky Diodes with a reverse breakdown voltage of

-60 to -50 Volts.

Sandip Jassar

Abstract

This paper details the fabrication and characterisation of Platinum Silicide Schottky Diodes that

I developed at the University of York in October 2004. Platinum was deposited on top of a wafer and annealed into the Silicon such that the Metal-Silicon interface would lie beneath the surface of the wafer where an intermediate layer of impurities and oxide is unavoidable. As

such the Metal-Silicon interface of these Platinum Silicide Schottky diodes was perfectly clean, and for the vast majority of diodes on the wafer yielded reverse breakdown voltages between

-60 and -50 Volts, where the slope of the forward-bias asymptote was between 5 and 7 mA/V.

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Contents

Section 1: Role of surface cleanliness

Section 2: Silicides, properties and formation

Section 3: The Fabrication process

3.1: Physical Vapour Deposition (evaporation) 3.2: Annealing 3.3: Photolithography 3.4: Depositing the Platinum 3.5: Photoresist lift off

3.6: Forming the Platinum Silicide 3.7: Use of Aluminium to contact the Silicide

Section 4: I-V Characteristics

References

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Section 1: Role of surface cleanliness

Silicon is a covalently bonded crystal. Since the surface atoms of a Silicon wafer (in its original form) don’t have neighbour atoms on the vacuum side to bond with, each surface atom thus has one broken covalent bond called a ‘dangling bond’. These dangling bonds give rise to ‘surface states’, which are energy states that lie between the Valence and Conduction bands (called the ‘Forbidden energy gap’). The effect of surface states is to pin the Fermi level at the surface, thus influencing the barrier height when a Schottky contact is formed. Even though

the Silicon wafer is chemically cleaned before metal is deposited on its surface, a 5 to 20 Å

thick insulating layer of oxide developing on its surface is unavoidable, as this grows very quickly on Silicon whenever it’s exposed to atmospheric conditions. Research has shown that the

Schottky barrier potential ФB is given by:

ФB = C1(ФM – χ) + (1 – C1)(Eg/q – Фo) (eq 1)

C1 = εi / (εi + q²δDS)

Where δ is the thickness of the oxide layer, εi is its permittivity, DS is the density of surface

states per eV per unit area within the band gap, χ is the electron affinity potential, ФM is the

barrier potential of the Schottky metal, Eg is the energy band gap of Silicon, Фo is said to be the

neutral level of the surface states (all surface states below that potential are occupied and all surface states above it are unoccupied). It can be seen from [equation 1] above that if the

density of surface states DS = 0 then C1 = 1, and thus ФB = (ФM – χ) which is theoretical

equation provided by Schottky-Mott theory. Although if DS is very large, then C1 tends to zero,

and ФB is said to approximate to (Eg - qФo)/(q). As can be seen above, C1 is not unique for a

particular metal-semiconductor combination, but it is dependent on the surface cleanliness of

the Silicon (which is very much related to δ).

As mentioned above, the surface states in the Silicon wafer act to pin its Fermi level at the surface. However, when the metal-silicon contact is formed, electrons from the metal can tunnel into the forbidden gap of the Silicon, due to the wave property of electrons. These electrons have an exponential decay type wave function, and leave tail energy states in the

Silicon that can penetrate up to a depth of 10 Å. These tail states can significantly alter the

intrinsic surface states of the Silicon, and thus the collective ‘interface states’ play a significant role in determining the Schottky barrier height. Although before the metal is evaporated onto the Silicon, it’s more than likely that the surface of the Silicon wafer will have a layer of native oxide. This creates interface states of a nature and density solely on the oxide-semiconductor combination. This oxide layer acts to suppress electrons from the metal tunnelling into the forbidden gap of the Silicon, and if the density of interface states at the oxide-semiconductor interface is sufficiently large, then this can render the Schottky barrier height independent of and insensitive to the work function of the metal. Therefore it is imperative that the Silicon wafer’s surface is as clean (has as little oxide on it) as possible when the metal is deposited onto it. However, with Silicide based Schottky contacts (introduced below in section 2), the Silicide-Silicon interface is located inside the Silicon. Therefore the barrier height does not

depend on the surface condition, and this problem is removed. Studies have shown that ФB of

Silicide based Schottky diodes decreases approximately linearly with the eutectic (alloying) temperature of the Metal with Silicon.

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Section 2: Silicides, properties and formation

Standard Schottky diodes use Aluminium as the metal to produce the Schottky contact. This was especially true for the Schottky barriers used in conjunction with the early families of Bipolar transistors, where the Schottky diode would be connected (or fabricated) across the base and collector, so as to reduce the amount of charge build-up, and hence yield a faster switching time for the device. However, with Aluminium-Silicon Schottky systems the atoms which lie at the metallurgical interface of the Aluminium and Silicon (referred to as interface-

atoms) are susceptible to interdiffusion at temperatures below 400 ºC. As the defects and

traps created by modern day fabrication techniques such as electron-beam evaporation (for deposition) and reactive ion etching (for etching) can only be repaired by annealing at

temperatures above 550 ºC. Another major reason why Aluminium is not the best metal to

form a Schottky contact on Silicon with is the high solubility of Silicon in Aluminium at relatively low temperatures. This leads to a defect known as Spiking. As current is applied, the Aluminium heats up, causing parts of the Silicon to dissolve into the Aluminium, thus creating voids below the interface which are often filled by Aluminium atoms. Spiking is obviously a major concern, as it can cause a short-circuit between the Schottky and Ohmic contacts, as well as the two ends of any junction-device, depending on the junction depth, and one of the main defects seen is a large leakage current. Therefore an alternative contact material to Aluminium is desired, preferably with a low resistivity (like Aluminium), as well as high-temperature stability. The criteria for a contact material to have high-temperature stability on Silicon is for the system of the two materials two have a high ‘Binary eutectic temperature’, which is the temperature at which the two materials start mixing together and forming an alloy. The Binary eutectic temperature for an Aluminium-

Silicon system is only 577 ºC, and as mentioned above interdiffusion for that system happens at

below 400 ºC.

The best contact materials, in terms of providing a low resistivity and high-temperature stability are ‘Metal Silicides’, which are metal-silicon compounds. The Silicides of most interest in the industry are those formed using metals in the ‘Refractory metal family’ and the ‘Near-Noble metal family’. Refractory metals are known to have extremely high evaporation temperatures, and so are not well suited at all to Chemical Vapour Deposition, which was the reason none of these metals were chosen to form the Silicide for the Schottky contact. Platinum (a Near-

Noble metal) was chosen instead, as its evaporation temperature (1700 ºC) is just about

achievable using CVD techniques. Silicide Schottky contacts are typically formed by evaporating the metal onto the Silicon wafer, and then maintaining the wafer at the reaction temperature of the metal so that the alloy can form. The formation of the Silicide consumes some of the Silicon, and thus the Silicide-Silicon interface will lie within the bulk of the ‘original’ Silicon. Hence any contaminations or impurities, such as surface oxide (which grows very quickly on the surface of Silicon when it is not under vacuum conditions) are left behind, and so do not deteriorate the interface properties as is the case with standard non-Silicide Schottky contacts.

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Section 3: The Fabrication process

The wafer used was a 3-inch (75 mm) wafer, and it was first cleaned in a mixture of sulphuric

acid and hydrogen peroxide (1:1) for 10 minutes and then rinsed off using deionised water. The

wafer was then put through the same process a mixture of hydrofluoric acid and deionised

water (1:6) for a short instant, and then blow-dried using a nitrogen air gun. The final step to

make the wafer suitable for use was to bake it at 150 ºC for a period of 1 hour. The material used to make the Ohmic contact on the back of the wafer was Gold/Antimony

1% (Au/Sb). This was done via the method of Physical Vapour Deposition (PVD), using the

evaporation technique (as apposed to sputtering).

3.1: Physical Vapour Deposition (evaporation)

The primary apparatus used for the PVD process was the ‘Evaporation Chamber’ shown below in (fig 1 & 2).

Baffle Valve

Air Admittance Valve

Backing Valve

Roughing Valve

Shutter Slider

Penning Gauge

Pirani

Rate Meter

Bell Jar

Variac Voltage Control

Variac Source Selector

Variac Current Indicator

Figure 1 : The Evaporation Chamber (shown with the Bell Jar on) used for Physical Vapour Deposition

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Shutter

Common Electrode

Source Electrodes

Crystal

Sample Support Frame

Figure 2 : The Evaporation Chamber (shown without the Bell Jar on) used for Physical Vapour Deposition

The first step was to load an Aluminium boat (shown in fig 3) with 0.1g of Au/Sb, and clamp the

two ends of the boat to one of the source electrodes (chosen arbitrarily) and the common

electrode. The weight 0.1g of Au/Sb was designed to yield a thickness of the deposited layer of

40 nm.

Tungsten wire coil

Aluminium boat

Figure 3 : The Aluminium boat and Tungsten coil used in Physical Vapour Deposition

The wafer was then placed on the Sample Support Frame, (with the back of the wafer face-down). The Shutter was then swivelled across so as to cover the boat and the (Bell Jar and Safety cover) were put on as shown in figure 1. The Vacuum Chamber (Evaporation Chamber)

was then pumped down from atmospheric pressure to below 0.2 Torr (20 Pa), taking the

reading from the Pirani. This was done using the Roughing Valve, which was kept open whilst the Air Admittance, Backing and Baffle Valves were kept closed. This was followed by high

vacuum pumping down to a pressure of 4 x 10^-7 Torr (4 x 10^-5 Pa), this time taking the

reading from the Penning Gauge and using the Backing and Baffle Valves which were kept open whilst the Air Admittance and Roughing Valves were kept closed. The power to the Variac was then switched on, and the correct source electrode was selected. The Variac voltage was then slowly increased, so as not to heat up the Aluminium boat too quickly and its

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resistance. When the boat was hot enough the Au/Sb could be seen through the Bell Jar to

be glowing, which showed it to be melting. The Variac voltage was further increased so that

the glow was brighter and evaporation of the Au/Sb occurred. At this point the Shutter was

swivelled away from the wafer to allow the Au/Sb vapour to reach the back of the wafer,

condense and (bond) with the Silicon (Si). The amount of Au/Sb being deposited on the wafer

was measured in nm by the Rate Meter via its crystal (as seen in figure 2). The Rate meter

had previously been calibrated by entering into it the Acoustic impedance and density of Au/Sb.

Once a thickness of about 40 nm had been achieved, the Shutter was swivelled back across to

cover the boat and prevent further deposition. The Variac voltage was zeroed, the Baffle valve was closed and then Air Admittance valve opened to slowly bring the Vacuum Chamber back up to atmospheric pressure, after which the wafer was removed.

3.2: Annealing

The next step was to diffuse (anneal) the Au/Sb into the Silicon so as to make an n+ layer in

the Silicon using the Furnace shown below in figure 4. The effect of annealing is to alloy the two materials together (if it is done at or above their eutectic temperature). This is a standard technique used to improve the Ohmic contact of a Schottky diode. It is the Antimony that acts

as the dopant, although on its own it can not withstand a temperature as high as 400 ºC, at

which the annealing procedure was done for a period of 3 mins in nitrogen (which is an inert

gas and so is non-reactive).

FurnaceQuartz tube

Quartz wafer rack

Temperature readingTemperature settings

Figure 4 : The Furnace used for the Annealing process

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3.3: Photolithography

The first step was to coat the polished side of the wafer with S1813 Photoresist (which is a ‘positive’ Photoresist) using a pipette. Photoresist (also referred to as Photoemulsion) is an organic liquid which is sensitive to Ultraviolet light. The wafer was held down to a metal plate

by a vacuum seal and then span at 3000 rpm for 40 sec, to yield a uniform coating across the

polished surface of the wafer (of thickness ~ 0.5 µm at that rpm and for that time). The wafer

was then soft-baked on a hot-plate (polished side face-up) for 1 min at a temperature of 115 ºC,

to harden the Photoresist in order to maintain the uniform coating (whilst handling the wafer,

etc). The wafer was then soaked in a beaker of Chlorobenzene for 1 min, which would aid lift-off

of the Photoresist when the time came. Photolithography involves the use of a mask (also referred to as a reticle), which is a quartz plate, which has on its surface the pattern that is to be transferred onto the wafer. Opaque regions of the mask pattern must be transparent to ultraviolet light, whilst dark regions must not be. The mask used was the ‘large area Schottky mask’, and its pattern was transferred to the wafer using the Photolithography stage shown in figure 5.

Mercury lamp

Mask aligner

Mask aligner x-y controls

Microscope

Mask

Wafer pad

Primitives user interface

display

Figure 5 : The Photolithography stage used for the Photolithography process

The light in the room was switched to yellow (monotone), which is done to protect the photoresist, as normal light contains some UV. The first step was to blow-dry the wafer using a nitrogen gun (nitrogen is an inert gas and thus is not reactive), and then place it on the wafer pad (photoresist-coated side up) shown above in figure 5. The Photolithography stage was then used to slide the wafer underneath the mask and auto-align the two. The contact force

and exposure time were set to 300 g and 7 sec respectively using the keypad. The Mercury

lamp was switched on for 7 sec thus exposing the wafer through the mask to Ultraviolet light.

The regions of the photoresist that were exposed to the Ultraviolet light became acidified. The

wafer was subsequently developed in MF319 developer for a time of 45 sec, causing the

exposed resist to etch away. Thus the mask pattern had been transferred onto the wafer, as is the effect when using positive photoresist as apposed to negative which transfers the inverse pattern to that on the mask.

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3.4: Depositing the Platinum

The Platinum was then evaporated onto the side of the wafer that had the ‘large area Schottky mask’ pattern on. Exactly the same procedure as that described in section 3.1 above, except this time a Tungsten wire coil had to be used to melt the Platinum because of its excessive

evaporation temperature of 1700 ºC. Tungsten is a Refractory metal and thus has a huge

melting temperature. A thickness of 12 nm of Platinum was achieved.

3.5: Photoresist lift off

The wafer was then left in Acetone over night for the Photoresist to lift off. Because the PVD for the Platinum layer was done at such a high temperature, the Photoresist became quite hard, and so in addition to the Acetone, cotton buds were used to wipe off the Photoresist, as well as an Ultra-sonic bath used to break up the structure of the Photoresist. All of the Photoresist (including the Platinum on top of it came off to leave a pattern of Platinum dots. The lift off process is shown below in figure 6.

Acetone

Photoresist (purple)

Platinum (silver)

Figure 6 : Showing the lift off of Photoresist.

3.6: Forming the Platinum Silicide

The wafer was then annealed using the same procedure outlined in section 3.2, this time at a

temperature of 300 ºC (the eutectic temperature of Platinum and Silicon) for a period of 3

mins. The annealing formed Platinum Silicide (PtSi), which consumed a section of the Silicon at

the top of the wafer.

3.7: Use of Aluminium to contact the Silicide

The Photolithography (with the mask aligned in the same position), PVD and Photoresist lift off steps were repeated, although this time using Aluminium (which would provide a contact to the

PtSi. The thickness of Aluminium deposited was 450 nm.

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Section 4: I-V Characteristics

The I-V characteristics of numerous diodes on the wafer were measured using the Probe Station and Curve tracer (shown below in fig 7). There were two adjacent gold-plated glass plates on the stage, and the wafer was placed on these with the Ohmic contact touching the gold on the glass plates. The ground probe was then made to touch the gold on the glass plates, so as to make an electrical connection with the Ohmic contact. The signal probe was then positioned over and lowered onto the Schottky diode under test. This was done by getting the Schottky contact (dot) in focus with the Microscope, and then lowering the signal probe until it too was in focus. A voltage was then applied to the Schottky diode using the signal control on the Curve tracer, and the resultant I-V curve appeared on the screen. A co-ordinate system was devised for the wafer (as shown in fig 9) in order to identify each diode. Table 1 below gives the results obtained for the diodes tested.

Curve tracer

Ground probe

Signal probe

Gold covered glass plate

Microscope

Figure 8 : The Curve Tracer and Probe Station used for the I-V characterisation

0 1 2 3

-1

-2

-3

0

1

3

-1-2

-3

2

Big flat

Figure 9 : Showing the coordinate system used to identify diodes on the wafer

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Diode co-

ordinates (x,

y)

VON : turn-

on voltage

(V)

Slope of

asymptote in

forward bias

direction

(µA/V)

IO :

reverse

saturation

current

(µA)

VB : reverse

breakdown

voltage (V)

Picture

-1, -6 0.05 5555.6 -28 -56

+1, -6 0.06 7142.9 -16 -52 Figure 10

-2, -6 0.055 5555.6 -50 -56 Figure 11

-4, -6 0.06 5000.0 -60 -40 Figure 12

-5, -5 0.045 2000 -30 -40 Figure 13

-1, +6 0.06 4166.7 -10 -55

+1, +5 0.06 4166.7 -10 -58

Table 1 : Showing the I-V characteristics for the Schottky diodes tested

These results may be verified with Jonathan Cremer of the Electronics Department Clean room staff at the University of York.

Reverse bias

characteristicForward bias characteristic

Slope of asymptote in

forward biased direction

VON turn-on voltage

IO Reverse saturation

current

VB Reverse breakdown

voltage Figure 10 : I-V curve for the diode at +1, -6

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Figure 11 : I-V curve for the diode at -2, -6

Figure 12 : I-V curve for the diode at -4, -6

Figure 13 : I-V curve for the diode at -5, -5

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References

“Semiconductors” R.A. Smith 2nd Edition

“Semiconductor Devices Physics and Technology” S.M. Sze

“Solid State Electron Devices” Ben Streetman 5th Edition

“Refractory Metal Silicides; Semiconductor International” David McLachlan 1984

“Crystal Structure and Linear Thermal Expansivities of Platinum Silicide and Platinum Germanide” E.J.

Graeber

“Subthreshold and scaling of PtSi Schottky barrier MOSFETs” L.E. Calvet