IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 7, JULY 2015 2197

1D Selection Device Using Carbon Nanotube FETsfor High-Density Cross-Point Memory Arrays

Chiyui Ahn, Zizhen Jiang, Chi-Shuen Lee, Hong-Yu Chen, Jiale Liang,Luckshitha S. Liyanage, and H.-S. Philip Wong, Fellow, IEEE

Abstract— A novel one-transistor-n-resistors (1TnR) arrayarchitecture is demonstrated as a cost-effective solution to thesneak path problem in large-scale cross-point memory arrays.In a 1TnR array, a single transistor (1T) with a 1D channeleffectively controls a number of resistive switching nonvolatilememory (NVM) cells (nR) while limiting the sneak leakagecurrent within the 1D channel without sacrificing the devicedensity. To maximize these benefits, a carbon nanotubeFET (CNFET) is employed as the 1D selection device, due toits near-ballistic electrical transport properties even at a smalldevice width. Experimental demonstrations of the CNFET-based1TnR concept are presented with two promising resistiveswitching NVM candidates: 1) resistive random access mem-ory (RRAM) and 2) phase-change memory (PCM). Here, wereport that the integrated bipolar Al2O3-based RRAM consumesprogramming energies as low as 0.1–7 pJ per bit and has ahigh programming endurance of up to 106 cycles. The 1TnRRRAM cell also has self-compliance characteristics, because thesemiconducting carbon nanotube (CNT) that serves as the bottomelectrode limits the device current. The unipolar PCM cellsintegrated with CNFETs show uniform electrical characteristicswith high ON-/OFF-resistance ratios of >10. Owing to theextremely small contact area between the phase change material,Ge2Sb2Te5, and the CNT, remarkably low programming currentsof <1 µA are achieved.

Index Terms— Carbon nanotubes (CNTs), CNT transistors,memory array architecture, phase-change memory (PCM),one-transistor n-resistors (1TnR), one-transistorone-resistor (1T1R), resistive memory, resistive random-accessmemory (RRAM), selection device.

I. INTRODUCTION

THE energy efficiency of computing systems isincreasingly limited by the memory and data storage

devices [1], [2]. Next generation nonvolatile memory

Manuscript received January 22, 2015; accepted May 13, 2015. Dateof current version June 17, 2015. This work was supported in partby the Office of the Director of National Intelligence, the Intel-ligence Advanced Research Projects Activity Trusted Integrated Cir-cuits Program, the member companies of Stanford Non-Volatile Mem-ory Technology Research Initiative Affiliate Program, and Systems onNanoscale Information Fabrics Center, one of six centers of Semiconduc-tor Technology Advanced Research Network, a Semiconductor ResearchCorporation Program sponsored by Microelectronics Advanced ResearchCorporation and Defense Advanced Research Projects Agency. The workof Z. Jiang, H.-Y. Chen, and L. S. Liyanage was supported in part by theM. Stanley Rundel Fellowship, the Intel Ph.D. Fellowship, and the IBMPh.D. Fellowship, respectively. The review of this paper was arranged byEditor Y.-H. Shih.

The authors are with the Department of Electrical Engineering, StanfordUniversity, Stanford, CA 94305 USA (e-mail: cyahn@stanford.edu;jiangzz@stanford.edu; chishuen@stanford.edu; redrain1213@gmail.com;tpslele@gmail.com; luckylehigh@gmail.com; hspwong@stanford.edu).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2015.2433956

technologies based on resistive switching, such as resistiverandom access Memory (RRAM) [3], [4] and phase-changememory (PCM) [5], [6], have been extensively studiedas new storage class memories (SCM), because the flashmemory beyond the 1z-nm technology node is expected toface its ultimate scaling limit of few storage electrons [7].The RRAM has a simple capacitor-like metal–insulator–metalstructure composed of transition metal oxides sandwichedbetween two metal electrodes and unlike flash memory, it hasshown excellent scalability <10 nm along with fast switchingspeed (<10 ns), low switching energy (<0.1 pJ per bit), andhigh endurance (>107 Hz) [8]. The PCM, another promisingSCM candidate, relies on electronic switching between thelow-resistance crystalline and high-resistance amorphousphases of chalcogenide alloys [5]. The superb scalabilityof PCM to ultrasmall dimensions (<5 nm) has also beenexplored in [9]–[11], and it is one of the more matureemerging memories under development [6].

The cross-point structure is an attractive memory arrayarchitecture due to its inherent small cell size of 4F2, where Fis the minimum feature size, and potential for multilayerstacking. In a passive cross-point structure, bitlines (BLs) andwordlines (WLs) perpendicular to each other are employedas top electrode (TE) and bottom electrode (BE) for eachmemory cell sandwiched between them. It has the intrinsicdrawback of sneak leakage currents through unselected andhalf-selected cells [12], [13] and suffers from parasitic seriesresistance from the interconnect wires [14]. In addition tothe increased power consumption due to the leakage, sneakleakage currents lead to serious problems especially in large-scale arrays, such as reduced write voltage access margin andread margin, which in turn limits the maximum allowablearray size. Many studies have been thus devoted to developingselection devices that can relieve the sneak path problem,including diodes [13], [15], [16], transistors [17], and var-ious nonlinear devices [18]–[20]. However, we still lacka cost-effective selection device with outstanding electricalcharacteristics.

In this paper, we show that the previously discussed sneakpath problem in large-scale cross-point memory arrays canbe significantly mitigated using one-dimensional (1D) selec-tion devices to construct a novel one-transistor-n-resistors(1TnR) array architecture [see Fig. 1(a)]. In the 1TnR,each 1T selectively activates its corresponding WL suchthat all memory cells (nR) in the same row are simul-taneously selected or not selected depending on the gatevoltage of the transistor. The sneak leakage current is then

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2198 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 7, JULY 2015

Fig. 1. (a) 3-D bird’s eye view of the novel 1TnR array architecturewith CNFET 1D selector. The resistive switching layer (RSL) is sandwichedbetween the metal TE (BL, along the y-axis) and the s-CNT BE (WL,along the x-axis). (b) Example of 1D sneak leakage path in the 1TnR. Thesneak leakage current is limited within the selected CNT at the bottom. Vaccrepresents the access voltage to the selected cell. (c) Schematic of the writeoperation to a selected memory bit (VWL = VBL = Vdd, and one end of theCNT channel grounded) in the 1TnR. The conductivity of the s-CNT channelis tunable by varying the applied gate voltage (VWL). (d) SEM image of theimplemented 3-bit 1TnR array with memory cells (n = 1, 2, and 3) tightlyintegrated on a single CNFET. Various contact pads for TE (1) through TE(3), local back gate (LBG), burning (B), source (S), and drain (D) are alsoshown. The s-CNTs are located within the 1 μm ×10 μm active region, withmetallic CNTs electrically burned away.

isolated to the 1D channel of the turned-ON transistoror the selected WL [see Fig. 1(b)]. In other words, the2D sneak leakage across all the BLs and WLs is reduced to amuch smaller 1D leakage along the WL only. For a transistorwith a 1D channel to perform an ideal selection operationin a high-density 1TnR array, it should meet the followingrequirements: 1) high ON/OFF ratio (ION/IOFF > 106) for highselectivity of memory bits; 2) low OFF-state leakage current(IOFF < 10 pA) to accommodate unselected and half-selectedcells in large-scale arrays; 3) high ON-state current density(JON > 10 MA/cm2 for PCM RESET and slightly lowerfor RRAM); 4) low processing temperature of <300 °C toallow 3D stacking; and 5) bipolar operation to allow for best-of-breed RRAM operation. In the 1TnR presented here, the 1Dselector that fulfills these criteria is tightly integrated with thememory element without a separate contact electrode, makingit more cost-effective than the conventional 1T1R array [seeFig. 1(c) for the schematic write operation to a selectedcell and Fig. 1(d) for the SEM image of the fabricated3-bit 1TnR array].

In this regard, high-performance carbon nanotube field-effect transistors (CNFETs) [21] with 1D carbon nanotube(CNT) channel are among the best candidates for the 1Dselectors because they exhibit large ON/OFF ratio (>106)and ultrasmall leakage current (<10 pA) at high currentdensities over 20 MA/cm2. Furthermore, it has already beenshown that CNTs can serve as memory cell electrodes forRRAM [22], [23] and PCM [9], [10]. This is important,because in the 1TnR, the CNT channel is integrated intothe memory cell as one of its electrodes. The concept ofusing a CNFET 1D selection device was introduced in [24],where successful operation of a single integrated PCM cellwas shown. In this paper, we illustrate the generality of the1TnR concept by experimentally demonstrating both RRAM

Fig. 2. (a) Near-symmetric Id versus Vd characteristics of a fabricatedCNFET device for different gate voltages (Vg). Its typical p-type responseis shown at both polarities of the drain voltage with good electrostaticcontrol by the LBG. (b) Id versus Vg for three different CNFET devicesat Vd = −1 V. The inset in (b) shows the Id –Vg curves at Vd of −3, −2,and −1 V for a single CNFET. All the voltages are given in reference to thesource voltage (Vs).

(bipolar) and PCM (unipolar) cells integrated in a 1TnRstructure for both 1×n and n×n arrays. For the demonstrationof a 1TnR using RRAM, a bipolar Al2O3-based RRAM waschosen for this paper due to its low power consumption [23]. Inaddition to the low programming energy benefit, the integratedRRAM cells show self-compliance characteristics that allowfast and reliable electrical switching. For the 1TnR PCM,the SET and RESET programming currents were directlymeasured in this paper. From these measurements, it was foundthat when integrated into the 1TnR, the PCM can be pro-grammed with ultralow currents due to the small contact areaof the integrated CNT electrode while maintaining excellentelectrical properties. Projections of the maximum 1TnR arraysize obtained from SPICE circuit simulations indicate that the1TnR array with either RRAM or PCM as the memory elementcan be built to at least 1 Mb without much degradation in arrayperformance.

II. CNFET AS 1D SELECTION DEVICE

We fabricated back-gated CNFET devices with 1D semicon-ducting CNT (s-CNT) channels using BEOL compatible low-temperature (<300 °C) processes. The typical output (Id–Vd)and transfer (Id –Vg) characteristics of the CNFET are shownin Fig. 2(a) and (b), respectively. The Id (drain current)–Vd (drain voltage) characteristics of a single CNFET deviceexhibit a typical p-type response, where the conductancedecreases as the gate voltage is swept from a negative to apositive bias. The Id –Vd data also indicate that the fabricatedCNFET device can be readily turned ON and OFF by changingthe gate voltage bias (Vg). In addition to good electrosta-tic control by the local metal (Pt) back-gate, the CNFETin Fig. 2(a) has nearly symmetric I–V curves, indicatingbipolar operation at both polarities of the drain voltage. This issignificant, because bipolar RRAM requires a selection devicehaving a symmetric I–V to perform a selection operation withSET and RESET voltages similar in magnitude and oppositein polarity. Fig. 2(b) further examines the characteristicsof the fabricated CNFET that are relevant for a selectiondevice: 1) the ON-state current (ION); 2) the OFF-state leakagecurrent (IOFF); and 3) the ON/OFF ratio (ION/IOFF).Typical Id –Vg curves from three different CNFET devicesindicate that although the subthreshold turn-OFF characteristics

AHN et al.: 1D SELECTION DEVICE USING CNFETs FOR HIGH-DENSITY CROSS-POINT MEMORY ARRAYS 2199

are relatively gradual (SS > 200 mV/decade) possibly dueto traps in the gate dielectric close to the interface [25],ultralow OFF-state leakage currents of IOFF < 10 pA(with 105 ∼ 106 ON/OFF ratio) were obtained for mostCNFET devices. With an applied gate voltage of ∼2 V, theunselected cells would pass extremely small sneak leakagecurrents because the CNFETs along the corresponding uns-elected WLs are turned-OFF (IOFF < 10 pA). In the caseof the half-selected cells on the selected WL, theId –Vg characteristics of a single CNFET need to be inves-tigated for larger (more negative) drain voltages, as the half-selected cells may experience a larger voltage drop betweenthe unselected BL and the selected WL. As shown in theinset, when the drain voltage becomes more negative, IOFF

still remains very low at ∼1 nA for Vd = −3 V. Therefore,the fabricated CNFET integrated into the 1TnR array as a1D selector is proved to be able to help in reducing thepotential sneak paths through unselected and half-selectedcells, thus preventing the cells from being mistakenly read orprogrammed. Moreover, all CNFET devices fabricated havehigh ON-state currents of ION > 1 μA even at the lowdrain voltage bias of −1 V and ON-current densities (JON)of >20 MA/cm2 with the effective contact area of sub-5 nm2 between the memory cell and the CNT electrode [10].Based on these measurements, we conclude that the fabricatedCNFET fulfills all five above-mentioned criteria for the idealselection device, thus offering great potential for realizationof high-density 1TnR array.

III. 1TnR RRAM

We first integrated Al2O3-based RRAM cells with theabove-described high-performance CNFETs to fabricate theRRAM stacks of Al (30 nm)/Ti (1 nm)/Al2O3 (8 nm)/s-CNT.A resistive switching layer (RSL) of 8-nm Al2O3, obtainedfrom 60 cycles of atomic layer deposition on top of thenaturally formed Al2O3, was first deposited on top of theCNT channels with minimal physical damage to the CNT.Next, Al (30 nm)/Ti (1 nm) is e-beam evaporated perpen-dicular to the CNT channel to serve as the top crossbarelectrode of the memory cell. The thin Ti interfacial layerbrings the benefits of reliable and robust bipolar electricalcharacteristics to the integrated RRAM cell due to its abilityto getter oxygen [26].

A. Bipolar DC Switching Characteristics

The bipolar dc switching characteristics of the RRAM cellsintegrated with a single CNFET selection device are shownin Fig. 3(a). In order to compare selected and unselected/half-selected cell cases, two different gate voltages of Vg = −5 Vand +2 V were applied to the back-gate of the CNFET. Letus first study the electrical switching behavior of the selectedRRAM cell [the n = 1 cell in Fig. 1(d)] by examining the casewhere the CNFET is fully turned ON with Vg of −5 V. Sincethe ON-state resistance of the CNFET is much smaller than thatof the as-deposited Al2O3 RRAM cell, the initial conductioncurrent of the Al/Ti/Al2O3/s-CNT device is determined by themuch larger resistance of the fresh RRAM cell (>300 G�).

Fig. 3. (a) Bipolar dc switching characteristics of the integrated 1TnRRRAM cells. One RRAM cell (black) is selected by applying −5 V to theback-gate of the CNFET selection transistor and the other cells (blue and red)are nonselected (unselected or half-selected) by a positive Vg of +2 V.(b) Write/erase pulsed endurance characteristics of up to 106 cycles for theselected RRAM cell. The ON-/OFF-resistance ratio of ∼10 was maintained.

As we further increase the sweeping voltage, a suddenincrease of the conductivity occurs at the so-called formingvoltage (Vform), which is ∼4.5 V. The electroforming processdid not require any current limiter (as in setting the complianceof a parameter analyzer). This self-compliance property ofthe integrated RRAM cell is attributed to the fact that theCNFET selection device itself limits the RRAM current.The self-compliance RRAM is preferred because it reducesthe design complexity of driving circuits for limiting thecompliance current level. The subsequent bipolar switchingbehavior observed in the figure can be understood from thefilamentary conduction mechanism [4]. After the forming,the integrated RRAM cell remains in the low-resistancestate (LRS), because the current flows through the local-ized conductive filament (CF) composed of oxygen vacanciesinside the Al2O3 layer. Once a sufficiently large negativevoltage (<−4 V) is applied to the TE (anode), oxygen ionsdrift from the Ti interfacial layer, which serves as an oxygenreservoir, back to the bulk Al2O3 layer. This ruptures theCF and creates a gap between the CF and the Al/Ti elec-trode, thus returning the memory cell to the high-resistancestate (HRS) (RESET). The HRS resistance is much smallerthan that of the fresh device because after the forming, suffi-cient defects are already generated inside the Al2O3 dielectriclayer. The HRS is mainly determined by the small gap of theCF near the oxygen reservoir [4] instead of the entire thicknessof the oxide. The RRAM device can be switched back tothe LRS (SET) by an applied positive voltage of ∼3.5 V,and during this process a portion of the CF is recoverednear the anode. For the dc switching cycles, low SET andRESET currents of ISET ∼ 0.5 μA and IRESET ∼ 7 μA weremeasured, and we note that IRESET is nearly the same as theSET compliance current (ICC) provided by the CNFET. Thelinear relationship between IRESET and ICC will be discussedlater in detail.

Next, we consider the other behavior of RRAM cells onthe same CNFET but with a positive gate voltage of +2 Vto emulate the nonselected case of the same CNT WL. Whenwe tried forming the n = 2 RRAM cell in Fig. 1(d) in theas-deposited state (see the blue curve), this RRAM cell stillremained in the highly insulating state and a sudden changein conductance was not observed during the voltage sweep.

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Fig. 4. (a) Dependence of the RRAM switching behavior on the CNFETON-state current level. Three different CNFETs with different ON-statecurrent (ION) levels of 7, 10, 20 μA (at Vd ∼ Vform, see the inset) wereused and compared as selection devices in the 1TnR. The RRAM cellintegrated with the CNFET #3 (which has the highest ION) shows the largestON-/OFF-resistance ratio (∼100) but is accompanied by a larger RESETcurrent. (b) Tradeoff between RESET current and ON-/OFF-resistanceratio. The observed one-to-one relationship between the measured RESETcurrent (IRESET) and the SET compliance current level (ICC) provided bythe CNFET selector (IRESET = ICC) suggests that in the 1TnR, the parasiticcapacitances between the RRAM cell and the selector were minimized. Theerror bars in (b) represent the standard deviations from measurements for100 dc switching cycles.

Unlike the selected cell case, the turned-OFF CNFET is highlyresistive and can carry only a small amount of current even athigh drain voltages (<10 nA at Vd = 5 V). When the voltageis swept to SET or RESET the RRAM cell in the HRS or LRS[see the red curve for the n = 3 cell in Fig. 1(d)], the devicecurrent is limited to the CNFET’s OFF-state current, as boththe HRS and LRS resistances are much smaller than theOFF-state resistance of the CNFET. The applied BL bias ismostly dropped across the CNFET and the RRAM cell cannotreach the required voltage to affect a CF.

B. Pulsed Endurance Characteristics

Since Al2O3-based RRAM requires much lowerprogramming currents than RRAMs based on other metaloxides (HfOx , NiOx , TiOx , TaOx , and so on) [4], the size ofthe CF may be smaller in Al2O3-based RRAM. Therefore,investigating its ability to achieve stable programming at highspeed and with good endurance is of great importance. Theintegrated RRAM device of Al/Ti/Al2O3/s-CNT stacks showsexcellent endurance characteristics of up to 106 write/erasecycles in Fig. 3(b), as compared with the earlier studies usingsimilar device stacks [22], [23]. The low RESET current ofsub-10 μA and the fast switching speed of 50 ns observed inFig. 3(a) and (b), respectively, enable us to confirm the lowswitching energy benefit of the integrated Al2O3 RRAM cell.The programming energy consumptions estimated with theapplied constant voltage pulse (+/−5 V, 50 ns) and theaverage resistance values [in Fig. 3(b)] are as low as0.08 and 7.35 pJ per bit for the SET and RESET operations,respectively. Direct time-domain measurement of sub-10 μASET/RESET current within tens of nanoseconds remains achallenge due to the RC delay of the measurement circuit.

C. Revisiting the Self-Compliance Characteristics

We further investigate the self-compliance characteristics ofthe integrated RRAM cell, by focusing on the selection device

ON-state current level. Fig. 4(a) indicates that the switchingproperties of the RRAM cell strongly depend on the ON-statecurrent (ION) level of the CNFET selection device used.The CNFETs behave as built-in series resistors that preventthe permanent breakdown of the integrated RRAM cells,giving various SET compliance current levels of 5 to 20 μA(see the inset for different IONs of the various CNFETs atVd ∼ Vform). The RRAM cell with the CNFET with higherION displays higher LRS currents while its HRS current stillremains unchanged. This difference arises from the fact thatthe HRS of the integrated RRAM cell is dictated by theAl2O3 switching layer, whereas the LRS of the integratedRRAM cell is governed by the more resistive s-CNT elec-trode [23]. A key parameter of concern for RRAM technologyis the RESET current (IRESET) since the maximum powerconsumption is mostly determined by the RESET current.Fig. 4(b) shows how the RESET current scales with the SETcompliance current (ICC) that is determined by the CNFETON-state current. The maximum IRESET for the integratedRRAM device is almost the same as ICC provided by theCNFET selection device in the forming/set process. In the1TnR structure, because the RRAM cell was tightly integratedwith the CNFET, the parasitic capacitances between the mem-ory and the selector elements were minimized. Otherwise,the possible overshoot current during the forming/set processcould have caused an increase in IRESET. In addition tothe linear relationship between IRESET and ICC observed inthe sub-20 μA regime, we also note an inevitable tradeoffbetween RESET current and ON-/OFF-resistance ratio. For cer-tain applications requiring higher sensing margins, additionalefforts are needed to increase ICC by increasing the density ofthe s-CNTs and/or by reducing the contact resistances betweenCNT channel and source/drain contacts to allow for higherON-currents.

IV. 1TnR PCMWe next present the electrical characteristics of the

integrated PCM cells in the 1TnR. The PCM cells wereintegrated on top of the CNFET selection transistor usingthe same processes described for the RRAM, except that thesputtered Ge2Sb2Te5 (GST) film had to be patterned into small1 μm2 regions at each node of the cross-point memories. If theGST were not patterned, then all PCM cells in the array couldhave been crystallized into the LRS, because the temperatureduring the fabrication process can exceed the crystallizationtemperature of the GST (typically ∼140 °C, depending onthe heating rate [27]). This would have resulted in a seriousleakage across both the WLs and the BLs.

The electrical switching experiments were performed forover 100 cycles on the selected PCM cell, where Vg = −3 Vwas applied to the back-gate of the CNFET, by usinga dc voltage and a 50 ns 1 V voltage pulse for SET and RESET,respectively. The dc-SET switching behaviors presentedin Fig. 5(a) for the 1st, 10th, 50th, and 100th cycles showthat the SET voltages (VSET) are quite uniformly ∼3.7 V,except during the first cycle. The much larger SETvoltage (∼6 V) required to SET the fresh PCM cell canbe explained by the switching mechanism of the confined

AHN et al.: 1D SELECTION DEVICE USING CNFETs FOR HIGH-DENSITY CROSS-POINT MEMORY ARRAYS 2201

Fig. 5. (a) DC SET switching characteristics of the integrated 1TnRPCM cell. With the CNFET selector turned ON, the PCM cell wasSET-programmed by applying a dc voltage to the TE and RESET-programmedby a 1 V 10/50/10 ns (rise time/pulsewidth/fall time) voltage pulse.(b) Statistical distributions of the measured RESET currents (IRESET) from100 repeated measurements (see [10] for the pulse measurement setupwith microsecond pulsewidth). The data in (b) ignore a possible slightincrease in reset current when the pulsewidth is reduced. Inset: typicalresistance–current (R–I ) switching curve of the integrated PCM cell.

crystalline path [10]. As seen in the switching curve forthe first cycle, the as-deposited PCM cell is in the HRS(R > 500 M�) in contrast to the conventional PCM device.The first voltage sweep creates a crystalline GST path alongthe 10-nm GST thickness. Since the highest temperature regionis localized on top of the CNTs [10], only the portion of thecrystalline GST near the CNT surface is amorphized during thesubsequent RESET cycles. The subsequent SET voltages aremuch smaller than the first one, because the thickness of theactive amorphous region is significantly reduced from the ini-tial 10 nm and the threshold switching voltage scales linearlywith the amorphous thickness at constant threshold switchingfield. It should be also noted that VSET is much reduced relativeto our earlier work [10], most likely due to the smaller contactresistances at the GST/CNT and/or CNT/metal contact padsresulting from the improved fabrication processes.

The programming currents for SET (ISET) andRESET (IRESET) are key parameters of the PCM device,because they determine the energy consumption. Themeasured SET current (ISET) in Fig. 5(a) is ∼0.2 μA, whichis about two orders of magnitude smaller than that of thePCM using conventional metal electrodes [16]. TheRESET current, IRESET, is of greater importance as ascalability metric. This is because IRESET scales directly withthe area of the PCM’s BE contact due to the Joule heatingneeded to melt-and-quench the phase-change material [5].We directly measured the current during the RESET operationto plot a typical R–I switching curve of the integrated PCMcell in the inset of Fig. 5(b). Programming currents withpulse amplitudes of <0.2 μA lead to the initial annealing ofthe active amorphous volume and the consequent decreasein the cell resistance. As the applied current approachesthe value of IRESET, the melt-and-quench of the criticalvolume results in a rapid increase in the cell resistanceand the RESET transition occurs. The average measuredIRESET of ∼0.8 μA in Fig. 5(b) is remarkably low and is∼40% smaller than the ones reported in [10]. The sub-1 μARESET current corresponds to an estimated effectivecontact area of sub-2 nm2 [10], thus indicating that the

Fig. 6. Endurance characteristics of the 1TnR PCM for 100 dc-SETand ac-RESET cycles. Uniform resistance distributions with highON-/OFF-resistance ratio are achieved.

integrated CNT BE effectively confines the active device area(i.e., the dimension of the GST crystalline path) down to asingle-digit nanometer regime close to the diameter of theCNT (∼1.2 nm). The unselected and half-selected PCM cellsdid not exhibit any electrical switching from HRS to LRSand vice versa, because the integrated CNFET is turned OFF

and limits the PCM current far below the measured SET andRESET currents.

Fig. 6 shows the endurance characteristics of the integratedPCM cell for 100 dc-SET and ac-RESET programming cycles,where both HRS and LRS resistances were read at 1 V.Uniform cycle-to-cycle resistance distributions with highON-/OFF-resistance ratios exceeding 10 were observed. Unlikethe RRAM case in which the LRS resistance of the integratedmemory cell scales linearly with the much higher resistanceof the s-CNT electrode, the electrical properties of the1TnR PCM cell are less dependent on the conductivity of theCNT electrode or the CNFET ON-current. This difference isattributed to the fact that the typical resistance of the10-nm GST in the LRS is comparable with or larger than thatof the CNT electrode used in the experiment. With furtherdecreases in the CNT resistance (<1 M�) or equivalentlyusing a CNFET selection device with higher ION, the LRS ofthe integrated PCM cell comes solely from the GST itself andthe voltage drop mostly occurs across the higher resistanceGST in LRS instead of across the CNT electrode.

The ON-state and OFF-state current(LRS and HRS resistance) levels of the fabricatedCNFET selection device, the integrated RRAM cell andthe integrated PCM cell are compared in Fig. 7 to pointout the key differences between the RRAM and PCMtechnologies integrated into the 1TnR architecture. First,RRAM and PCM have different LRS resistance levels. TheLRS resistance of the Al2O3 RRAM cell is strongly affectedby the size of the CF inside the dielectric layer; the resistancelevel of the CF (plus possible interface resistances) can beas low as 1 k� [28]. Since the CNFET selector has anON-state resistance much larger than 1 k�, the LRS of theintegrated RRAM cell is mostly determined by the CNFET’sresistance. The SET current of the 1TnR RRAM cell canbe further reduced by adjusting the CNFET’s back-gatevoltage (VWL) to increase the CNFET ON-state resistance,which limits the growth of the CF and thus lowers the

2202 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 7, JULY 2015

Fig. 7. Box plots with statistical variations from repeated cycles(RRAM/PCM) and measurements (CNFET), comparing the typical cur-rent and resistance (R) levels for the CNFET selector [#1 in Fig. 4(a)],Al2O3 RRAM, and PCM. The CNFET current levels were extracted fromthe Id –Vd characteristics of a single CNFET with separate source and draincontacts. The smaller LRS current in the integrated RRAM cell than in theCNFET indicates that the larger contact resistances may be derived fromcontacts between the Al/Ti TE and the Al2O3 layer and/or between theAl2O3 layer and the CNT electrode.

RESET current. On the other hand, when PCM is integratedas a memory element in the 1TnR array, the overall LRSresistance of the integrated PCM cell is dominated neitherby the CNFET nor by the PCM, as their LRS resistancevalues are both ∼1 M�. Therefore, the RESET current of theintegrated 1TnR PCM is dependent on the effective contactarea between the GST and the CNT electrode. This areacan be as small as allowed by the CNT diameter and yieldssub-1-μA RESET currents. Unlike in the LRS, the HRSresistance levels for both RRAM and PCM are much largerthan the CNFET ON-state resistance. Since the CNFET isrelatively conductive compared with the RRAM/PCM cellin HRS, the 1TnR memory cell characteristics in HRS aredetermined mainly from the RRAM/PCM itself. Irrespectiveof these differences in the physical mechanisms behind theLRS and the low programming current, the 1TnR integrationenables realization of high-density memory arrays with bothRRAM and PCM technologies. Ultimately, this is becausethe 1D CNFET selector can offer high memory bit selectivityby having high ION (>1 μA) and ultralow IOFF (<10 pA).

V. PROJECTION OF MAXIMUM 1TnR ARRAY SIZE

In order to assess the maximum possible size of the1TnR array based on the CNFET 1D selector, we performedSPICE simulations and compared the write voltage accessmargins (Vacc/Vdd) of the three different array architec-tures in Fig. 8(a): 1R (without any selection device), 1T1R(with state-of-the-art Si-based MOSFET as the selectiondevice), and 1TnR (with CNFET as the selection device). Bothan ideal (ballistic) CNFET and the experimental CNFET pre-sented in this paper were used for the 1TnR simulation.As shown in the figure simulating the worst-case [14] RRAMcell with RLRS of 1 M�, the 1TnR structure with idealCNFETs outperforms the 1R case for arrays >10 kb. This isbecause the 1R structure experiences significant voltage dropsin the wires and the memory cells due to its inherent sneakleakage for large passive arrays. Since the 1TnR structure stillhas a similar device density as the 1R case, it offers a practical

Fig. 8. (a) Simulated write voltage access margins (Vacc/Vdd) for variousarray structures: 1R (passive cross-point structure) without any selectiondevices, 1T1R with state-of-the-art Si MOSFETs as selection devices, and1TnR with CNFETs as selection devices. Inset: a magnified view forVacc/Vdd > 0.9. (b) Dependence of Vacc/Vdd on the 1TnR array configuration(number of WLs × number of BLs): square (2N ×2N ), rectangular with moreWLs than BLs (4N × N ), and rectangular with more BLs than WLs (N ×4N ).

tradeoff between device density and write access voltage. Theideal 1TnR structure can have as large write access voltageas the 1T1R case due to the high current-drive of the idealCNFET at the small device width of 10 nm. However, theexperimental as-fabricated CNFETs currently exhibit muchsmaller ION than the ideal ones, typically <10 μA in theexperimental case versus 50 μA in the ideal case at a low drainvoltage bias of −1 V. This leads to a decreased access marginfor the non-ideal 1TnR case. For the smaller 1TnR arrays(n < n1D–>2D, where n1D–>2D is the array size at whichthe sneak leakage begins to deteriorate from 1D to 2D),the sneak current is limited to 1D leakage through theselected WL. Therefore, the access margin decreases withincreasing array size due to the higher CNFET channelresistances for longer CNTs. Despite the initial reduction inthe access margin at increasing array sizes, the 1TnR withexperimental CNFETs as selection devices maintains accessmargins as high as 80% until the array size (n) reachesn ∼ n1D–>2D (about 4 kb). As the 1TnR array size furtherincreases past n1D–>2D, sneak leakage currents across WLs areno longer negligible, as the CNFETs of unselected WLs areturned OFF but still conduct finite OFF-state currents. At thispoint, the write access margin starts to rapidly degrade dueto the 2D nature of the sneak leakage. We note that the ideal1TnR can still perform very well without much degradationof the access margin (>80% at 1 Mb) due to the CNFET’sideal SS value and thus negligible OFF-state currents. It is thusconcluded that in order to realize the large-scale 1TnR arrayof 1 Mb or higher, the electrical properties of the fabricatedCNFET need to be further improved such that it carries ahigher current-drive (ION > 30 μA) and achieves steepersubthreshold (SS < 100 mV/decade) characteristics.

Another way to enable larger-scale 1TnR array isinvestigated in Fig. 8(b), which compares the 1TnR arrays ofthree different configurations: square (2N × 2N), rectangularwith more WLs than BLs (4N × N), and rectangular withmore BLs than WLs (N × 4N). As described above, whenthe array size is small, the leakage current of the arrayis dominated by the 1D sneak leakage along the selectedCNT WL. Therefore, the 4N × N rectangular array with thesmaller number of BLs can be advantageous due to the smaller

AHN et al.: 1D SELECTION DEVICE USING CNFETs FOR HIGH-DENSITY CROSS-POINT MEMORY ARRAYS 2203

CNFET ON-state resistance. However, as the array sizeincreases, the leakage currents across both WLs and BLsbecome larger and the leakage becomes 2D, making theN × 4N rectangular array with the smaller number of WLspreferred. The N × 4N 1TnR array fully utilizes the excellent1D transport properties of the CNT by having sneak leakagesmostly limited to the 1D CNT channel. By constructing thisasymmetric 1TnR array, Vacc/Vdd of >50% is achieved for theN × 4N 1TnR array, as opposed to only ∼16% for thesquare (2N × 2N) array, for the array size of 300 kb.

VI. CONCLUSION

Experimental demonstrations of the 1TnR array architecturereveal that the integrated RRAM and PCM cells have outstand-ing electrical properties, such as large memory window, fastswitching speed, and exceptionally low programming current.The key enabling technology for the realization of the large-scale 1TnR array is the use of 1D selection devices to limit thesneak leakage current inside the 1D channel without requiringan enlarged area footprint. The CNFET is an ideal 1D selectiondevice for various types of resistive switching memories,because it allows for low processing temperatures, bipolaroperation, and high memory bits selectivity by providinghigh ION and sufficiently low IOFF. Furthermore, because the1D CNT channel is integrated into the memory cell as aBE, the CNFET 1D selector provides great opportunities tobring the lithography independent critical dimension of theintegrated memory cell down to a single-digit nanometer, thusmaking it possible to realize high-density cross-point memoryarrays.

REFERENCES

[1] P. Kogge, Ed., ExaScale Computing Study: Technology Challenges inAchieving Exascale Systems. Arlington, VA, USA: DARPA, Sep. 2008.

[2] (May 2012). Computing Community Consortium (CCC). [Online].Available: http://www.cccblog.org/2012/05/29/21st-century-computer-architecture

[3] R. Waser, R. Dittmann, G. Staikov, and K. Szot, “Redox-basedresistive switching memories—Nanoionic mechanisms, prospects, andchallenges,” Adv. Mater., vol. 21, nos. 25–26, pp. 2632–2663, 2009.

[4] H.-S. P. Wong et al., “Metal–oxide RRAM,” Proc. IEEE, vol. 100, no. 6,pp. 1951–1970, Jun. 2012.

[5] H.-S. P. Wong et al., “Phase change memory,” Proc. IEEE, vol. 98,no. 12, pp. 2201–2227, Dec. 2010.

[6] M. J. Kang et al., “PRAM cell technology and characterization in 20 nmnode size,” in IEDM Tech. Dig., Dec. 2011, pp. 3.1.1–3.1.4.

[7] C.-Y. Lu, K.-Y. Hsieh, and R. Liu, “Future challenges of flash memorytechnologies,” Microelectron. Eng., vol. 86, no. 3, pp. 283–286, 2009.

[8] B. Govoreanu et al., “10 × 10 nm2 Hf/HfOx crossbar resistive RAMwith excellent performance, reliability and low-energy operation,” inIEDM Tech. Dig., Dec. 2011, pp. 31.6.1–31.6.4.

[9] A. Behnam et al., “Sub-10 nm scaling of phase-change memory:Thermoelectric physics, carbon nanotube and graphene electrodes,” inProc. Eur. Symp. Phase Change Ovonic Sci. (E\PCOS), 2013, pp. 1–6.

[10] J. Liang, R. G. D. Jeyasingh, H.-Y. Chen, and H.-S. P. Wong,“An ultra-low reset current cross-point phase change memory withcarbon nanotube electrodes,” IEEE Trans. Electron Devices, vol. 59,no. 4, pp. 1155–1163, Apr. 2012.

[11] S. Raoux, J. L. Jordan-Sweet, and A. J. Kellock, “Crystallizationproperties of ultrathin phase change films,” J. Appl. Phys., vol. 103,no. 11, p. 114310, 2008.

[12] E. Linn, R. Rosezin, C. Kügeler, and R. Waser, “Complementaryresistive switches for passive nanocrossbar memories,” Nature Mater.,vol. 9, pp. 403–406, Apr. 2010.

[13] B. S. Kang et al., “High-current-density CuOx/InZnOx thin-film diodesfor cross-point memory applications,” Adv. Mater., vol. 20, no. 16,pp. 3066–3069, 2008.

[14] J. Liang and H.-S. P. Wong, “Cross-point memory array without cellselectors—Device characteristics and data storage pattern dependencies,”IEEE Trans. Electron Devices, vol. 57, no. 10, pp. 2531–2538,Oct. 2010.

[15] W. Y. Park et al., “A Pt/TiO2/Ti Schottky-type selection diode foralleviating the sneak current in resistance switching memory arrays,”Nanotechnology, vol. 21, no. 19, p. 195201, 2010.

[16] Y. Sasago et al., “Cross-point phase change memory with 4F2 cell sizedriven by low-contact-resistivity poly-Si diode,” in VLSI Symp. Tech.Dig., Jun. 2009, pp. 24–25.

[17] Y. Sasago et al., “Phase-change memory driven by poly-Si MOStransistor with low cost and high-programming gigabyte-per-secondthroughput,” in VLSI Symp. Tech. Dig., Jun. 2011, pp. 96–97.

[18] M. Son et al., “Excellent selector characteristics of nanoscale VO2 forhigh-density bipolar ReRAM applications,” IEEE Electron Device Lett.,vol. 32, no. 11, pp. 1579–1581, Nov. 2011.

[19] J.-J. Huang, Y.-M. Tseng, C.-W. Hsu, and T.-H. Hou, “Bipolarnonlinear Ni/TiO2/Ni selector for 1S1R crossbar array applications,”IEEE Electron Device Lett., vol. 32, no. 10, pp. 1427–1429, Oct. 2011.

[20] G. W. Burr et al., “Large-scale (512 kbit) integration of multilayer-readyaccess-devices based on mixed-ionic-electronic-conduction (MIEC) at100% yield,” in VLSI Symp. Tech. Dig., Jun. 2012, pp. 41–42.

[21] A. Javey, R. Tu, D. B. Farmer, J. Guo, R. G. Gordon, and H. Dai,“High performance n-type carbon nanotube field-effect transistors withchemically doped contacts,” Nano Lett., vol. 5, no. 2, pp. 345–348, 2005.

[22] Y. Wu, Y. Chai, H.-Y. Chen, S. Yu, and H.-S. P. Wong, “Resistiveswitching AlOx-based memory with CNT electrode for ultra-lowswitching current and high density memory application,” in VLSI Symp.Tech. Dig., Jun. 2011, pp. 26–27.

[23] C.-L. Tsai, F. Xiong, E. Pop, and M. Shim, “Resistive random accessmemory enabled by carbon nanotube crossbar electrodes,” ACS Nano,vol. 7, no. 6, pp. 5360–5366, 2013.

[24] C. Ahn et al., “A 1TnR array architecture using a one-dimensionalselection device,” in VLSI Symp. Tech. Dig., Jun. 2014, pp. 1–2.

[25] S. J. Wind, J. Appenzeller, R. Martel, V. Derycke, and P. Avouris,“Vertical scaling of carbon nanotube field-effect transistors using topgate electrodes,” Appl. Phys. Lett., vol. 80, no. 20, p. 3817, 2002.

[26] P.-S. Chen et al., “Improved endurance in ultrathin Al2O3 film witha reactive Ti layer based resistive memory,” Solid-State Electron.,vol. 77, pp. 41–45, Nov. 2012.

[27] I. Friedrich, V. Weidenhof, W. Njoroge, P. Franz, and M. Wuttig,“Structural transformations of Ge2Sb2Te5 films studied by electricalresistance measurements,” J. Appl. Phys., vol. 87, no. 9, p. 4130, 2000.

[28] Y. Wu, S. Yu, B. Lee, and P. Wong, “Low-power TiN/Al2O3/Ptresistive switching device with sub-20 μA switching current and gradualresistance modulation,” J. Appl. Phys., vol. 110, no. 9, p. 094104, 2011.

Chiyui (Ethan) Ahn received the B.S. andM.S. degrees in electrical engineering from theKorea Advanced Institute of Science and Technol-ogy, Daejeon, Korea. He is currently pursuing thePh.D. degree in electrical engineering with StanfordUniversity, Stanford, CA, USA.

His current research interests include emergingnonvolatile memory devices and architectures, andcarbon electronics.

Zizhen (Jane) Jiang received the B.S. degree fromPeking University, Beijing, China. She is currentlypursuing the Ph.D. degree in electrical engineeringwith Stanford University, Stanford, CA, USA.

She joined Stanford University in 2012. Hercurrent research interests include resistive randomaccess memory device and technology, includingmodeling and fabrication.

2204 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 7, JULY 2015

Chi-Shuen (Vince) Lee received the B.S. degreefrom National Taiwan University, Taipei,Taiwan, and the M.S. degree from StanfordUniversity, Stanford, CA, USA, where he iscurrently pursuing the Ph.D. degree.

His current research interests include modelingand simulation of nanoscale transistors andCMOS technology assessment.

Hong-Yu (Henry) Chen received the B.S. degreefrom National Tsing Hua University, Hsinchu,Taiwan, in 2007, and the M.S. and Ph.D. degreesfrom Stanford University, Stanford, CA, USA,in 2011 and 2014, respectively, all in electricalengineering.

His current research interests include carbonnanotubes and emerging memory, and he is currentlya Senior Hardware Engineer with SanDisk.

Jiale Liang received the B.S. degree inmicroelectronics from the Department ofMicroelectronics, Peking University, Beijing,China, in 2007, and the M.S. and Ph.D. degreesin electrical engineering from Stanford University,Stanford, CA, USA, in 2009 and 2012, respectively.

She is currently a Senior Hardware Engineerwith Oracle, Santa Clara, CA, USA, where she isinvolved in the design of Oracle’s next-generationmicroprocessor.

Luckshitha S. Liyanage received the B.S. degreefrom Lehigh University, Bethlehem, PA, USA, andthe M.S. and Ph.D. degrees from Stanford Uni-versity, Stanford, CA, USA, in 2011 and 2014,respectively, all in electrical engineering.

He has been with Stanford University since 2009,where he has been involved in carbon nanotubetechnologies, including growth and characterizationand device/circuit fabrication.

H.-S. Philip Wong (F’01) is currently theWillard R. and Inez Kerr Bell Professor withthe School of Engineering, Stanford University,Stanford, CA, USA. His current research inter-ests include carbon electronics, 2D layered mate-rials, wireless implantable biosensors, directedself-assembly, nanoelectromechanical relays, devicemodeling, brain-inspired computing, and emergingnonvolatile memory devices.

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