A High-Density 45nm SRAM Using Small-Signal Non-

Strobed Regenerative Sensing

Naveen Verma and Anantha ChandrakasanMassachusetts Institute of Technology

ISSCC 2008

21.3

2

High-Density SRAM Limiting Factors

Counter severe variability through sense-amp

MC

MC

MC

MC

WL[0]

WL[255]

WLE STRB

Severe variation degrades worst-case

1) Cell current (IREAD)2) Read SNM

3) Offset limits min. BL discharge, area scaling

4) Strobe signal tracks array read-path poorly

0.25µm2

6T bit-cell

3

Outline

• High Density 45nm SRAM challenges• Single-ended read architectures• Non-strobed regenerative sense-amp

(NSR-SA) operation• Prototype measurements• Conclusions

4

IREAD Degradation

Variation causes larger fractional

degradation

Mean

5σMC

MC

MC“1”

“0”

“0”

IREAD

Upto

256

cells

per

c olu

mn

f orm

ax.d

ensi

ty

5

Read SNM-IREAD Degradation

Read SNM of 0.25µm2 cell is too low and must be

improved at the cost of IREAD

Strong for IREAD

Weak for RSNM

WL WL

5σ

Mean

6

SA Strobe Timing Uncertainty

Array and strobe paths track poorly; required timing margin increases worst-case access time by ~20%

Del

ay (n

s)

PVT Corner

Array Path Strobe Path

Worst-case array delay: 820psWorst-case strobe delay: 980ps

980ps

820ps MC

MC

MC

MC

WLESTRB

Array read path

Strobe path

7

Single-Ended Sensing - TechniquesAsymmetric cells can have wider operating margins

e.g. 8T [Morita, Chang, Joshi, etc. VLSI’07]Full-Swing Sensing Pseudo-Differential Sensing

• Need to minimize CBL/IREAD limits density

[Zhang, VLSI’00]

• Need to generate reference that tracks IREAD,MIN

MC“1”

“0”

(Use large cell to maximize)

Min

imiz

ece

llson

loca

lRD

BL

(e.g

.8)

Logic gate SA (CMOS, domino)

for min. area

IREAD

MC[Tzartzanis, ISSCC’04]

Ref

Ref

“1”

“0”

“0”

“1”

MC

MC

IREAD

IREF ≈IREAD/2

8

Single-Ended Sensing – Trade-off

Single-ended sensing introduces trade-off between sensitivity and noise-rejection

Differential SA Single-Ended SASingle-ended SA has no common-mode rejection…

MC

MC

BLBLB

SA rejects CM noise

MC

MC

BL

SA should respond to

min. BL discharge

MC

MC

BL

SA should reject noise

9

Non-Strobed Regenerative (NSR) SA

RST RST

RSTB

RSTB

RSTB

QB

RSTB

Regenerative feedback

device

Inverter amplifiersBL<A>BL<B>BL<C>BL<D>

Col

.mux Sense-

amp

10

NSR-SA Operation: Reset Phase

Want X≈Y(takes <100ps)

Time (ns)

Bit-

lines

(V)

NSR

-SA

(V)

PREBL

XY RST

“0”“0”

M1

M2

M3

M4

Precharge

Precharge

X YBL

11

NSR-SA Operation: Sense “1”

VGS5,7 remains 0 (or negative)

Time (ns)

Bit-

lines

(V)

NSR

-SA

(V)

WLBL

YX QB

RST

QB

“1”“1”

M1

M2

M3

M4

X Y

M5

M7

VGS≈0

VGS≈0

BL

12

NSR-SA Operation: Sense “0”

VGS7 >> 0, triggering

regeneration

Time (ns)

Bit-

lines

(V)

NSR

-SA

(V)

WLBL

YX QBRST

QB

“1”“1”

M1

M2

M3

M4

X Y

M5

M7

VGS >> 0

VGS >> 0Actively pulled low

by M7

BL

13

NSR-SA Output Clocking

NSR-SA latches data, so output can be clocked

after PRE begins

NSR

-SA

(V)

PRE/

RST

(V)

BL/

WL

(V)

Time (ns)

PRERST

BLWL

Y

X

QB

SRAM ARRAY

STRB

CLK

QB valid until RST (not PRE)

14

NSR-SA Offset Compensation - I

Negative of offset voltages are stored on C1/C2; VTCs from IN-X and X-Y are offset free

Nodes A & B get charged to ≈VM-VOS

VOS1,2

Offset voltages

VOS3,4

VOS7

XY

M7

Ideal inverter (with trip-point VM)

IN

C1

C2A B

RST RST

IN

OU

T

VOS

VM≈VM –VOS

15

NSR-SA Offset Compensation - IIFirst

inverter’s offset

dominates

All offsets are diminished by at least gmro(i.e. inverter gain) when input referred

VOS1,2 VOS3,4

VOS7

XY

M7

INC1 C2

A B

VM + VOS1,2/gmro VM + VOS3,4/gmro

(gmro + (gmro)2)VOS7

VOS3,4/(gmro)2

16

SA Access Time Distribution

• Mean bit-cell• Nominal process corner

• Variation applied to all SA devices

NSR-SA offset compensation yields superior sigma

STRB

QB

INBIN

RSTBRSTB

Conventional SAMean: 500psSigma: 37ps

NSR-SAMean: 418psSigma: 18ps

172.5 3 3.5 4 4.5 50

0.5

1

Charge Injection Error Immunity

Charge injection errors oppose regeneration

NSR

-SA

(V)

Time (ns)

RSTX

Y

Charge-injection opposes regeneration

XY

M7

IN

C1

C2A B

False regeneration

RSTB

PMOS (positive charge injection)

NMOS (negative charge injection)

RST

18

Regeneration Trip Point

Adjust reset value of X & Y to set

desired BL discharge required

for regeneration

Requires small device (0.2µm x0.2µm)

M1

M2

M3

M4

X Y

Injected current trims

reset value of X

VGS (at reset) sets BL discharge required

M7

19

Test-Chip ArchitectureConventional SA

NSR-SA

64x64

8

64kb Array(256 x 256

0 ..25µm2 cells)

64 8

64kb Array(256 x 256

0 ..25µm2 cells)

4:1

x64

8:18:1

4:1

2:1

ADDR[7:0] CSEL[1:0] STRB GSEL[2:0]

WLE CLKIN BSEL

8

Q[7:0]

Conventional SA

NSR-SA

WLE

CLKIN

STRB1

2

WLE

CLKIN

20

Noise Injection Circuit

MC

MC

CBL CBL

50 Ohm

TrimInv1 TrimInv2

M8-9 adjust reset point of inverters

to trim VGS,M7

CNOISE

M8

M9

CNOISE

M7NSR-SA

Noise estimated from ratio of CNOISE to CBL

21

Prototype SRAM

• 45nm low-powerCMOS

• 2, 256x256 arrays(compare SA performance)

• 0.25µm2 bit-cells

1.80mm

1.25

mm

64kbArray

64kbArray

Decoders/WL drivers

Decoders/WL drivers

Conv. SA NSR-SA

Col.periph.

22

Measured Access Times

-2 -1 0 1 2 30

10

20

30

Occ

urre

nces

Access Time (ns)

Conventional SAMean: 1.59nsSigma: 401psMax.: 2.46nsNSR-SA – Conv.

(difference)

NSR-SAMean: 1.27nsSigma: 103psMax.: 1.63ns

Measured 53 chips; NSR-SA gives 34% speed-up in worst-case

access-time

23

Noise Rejection

1 1.05 1.1 1.15 1.2-10

0

10

20

30

40

50

Access Time from Sample Bit-Cell (ns)

BL

Noi

se R

ejec

tion

(mV)

Reduce regeneration trip-point

Increase coupling noise

50mV of bit-line noise margin can be reduced for up to 20% performance increase

24

Performance Summary

7%2%% of array power (at 100MHz)

1.67ns2.46nsMax. access-time1.27ns1.59nsMean access-time

103ps401psAccess-time sigma

23µW-Power in reset19µm2 *12µm2Area

64kbCapacity256 x 256Array configuration0.25µm2Cell size

45nm low-power CMOSTechnologyNSR-SAConventional SA

*NSR-SA includes testability features

25

Conclusions

• Bit-cell design for high-density SRAM is highly constrained, leading to low IREAD

• NSR-SA improves sensing stability with offset compensation and overcomes strobe uncertainty, enhancing speed up to 34%

• Single-ended small-signal sensing improves trade-offs for asymmetric bit-cells

Acknowledgements: Funding by Intel Foundation Ph.D. Fellowship Program. IC fabrication by TI.