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A 40-Gb/s Clock and Data Recovery Circuit in 0.18-um CMOS Technology
Jri Lee, Student Member ,IEEE, and Behzad Razavi, Fellow, IEEEIEEE Jorunal of Solid State Circuits, VOL. 38, NO. 12, DECEMBER 2003
Dae-hyun Kwon
Contents
Clock and Data Recovery circuits– Why quarter-rate?
– CDR building blocks Sampler Xor V/I converter VCO
– Non-ideal Effect Staggered Outputs Group velocity
– Results
– Conclusion
Clock and Data Recovery Circuits
Why quarter-rate CDR?
– The limitation of fabrication 0.18-um
fT=50[GHz] Gain X BW =constant, Gain=1 BW=? Fanout one 12 Gb/s
180 160 140 120 100 80 60
40
60
80
100
120
140
160
180
200
220
TSMC 90nm
TSMC 65nm
SEC 65nm
SEC 130nm
Freescale SOI 130nm
Tran
sit F
requ
ency
[GH
z]
Technology [nm]
TSMC 180nm
Clock and Data Recovery Circuits
Why quarter-rate CDR?
– Half –rate CDR Latch X 4 (necessary inductor X 8)
– The speed limitation of frequency divider
– Lots of FF(Flip-Flop) for making full or half-rate CDR
Clock and Data Recovery Building Blocks
Sampler Design
– Conventional type of Flip-Flop
Voltage headroom speed limitation Data can affect to the output without isolation
– Inductive peaking type Bulky
Clock and Data Recovery Building Blocks
Modified Flip-Flop
– Isolation input and output Clock feed-through– Solving problem of voltage headroom– Without inductor small area– Systematic delay mismatch Buffering with Cherry-Hopper Amp.
Conventional type
Inductive peaking
Modified FF
Xor– Conventional type voltage headroom and speed limitation– Other types of Xor is used– Controlling the VGS , Xor can be operated
Clock and Data Recovery Building Blocks
Clock and Data Recovery Building Blocks
V to I converter– Not switch every phase comparison Free from dead-zone
Dead-zone cause of Charge pump (Every phase switching for current flowing)
Dead-zone
Data
CK0 CK45 CK90
up down
High
Low
High
Low
up
down
Data
Clock
Δɸ
I
Bang-bang PD gain
Dead-zone
Clock and Data Recovery Building Blocks
Voltage controlled Oscillator– LC oscillator
Lower phase noise & larger voltage swing
Clock and Data Recovery Building Blocks
Phase Detector– Bang-bang PD– Sampler X 8 + Xor X 8 quarter-rate clock sampling
Non-ideal Effects
Staggered Outputs
0 45 90 135No data transition
I1
I2
X1
X2
X3
Vcont
87.5 ps
0 45 90 135
D Q
D Q
D Q
D Q
CK0
CK45
CK90
CK135
VCO
X1
X2
X3
X4
I1
I2
– Low pass filter extract value of the V/I output– Misalignment creates ripple on the oscillator control Voltage– Kvco = 1GHz / V
Non-ideal Effects
Group Velocity
– Limited BW of CDR reject jitter– Data duty cycle + Multiphase clock align– Without inductor and compact layout for decreasing length between input Flip-Flop
Results
Test set-up & Experimental results
– PRBS 231-1– BER = 10-6
– RMS jitter =0.9 [psec]– Power dissipation = 144 [mW]
Conclusion
0.18 – um CMOS technology being used for 40-Gb/s CDR
Without inductors, Flip-Flop could sample the 40-Gb/s data with 10GHz clock
Decreasing dead-zone by using V to I converter
Decreasing phase noise by making VCO with LC, passive components