JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.6, DECEMBER, 2015 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/JSTS.2015.15.6.594 ISSN(Online) 2233-4866

Manuscript received Dec. 5, 2014; accepted Aug. 8, 2015 1 College of Information & Communication Engineering, Sungkyunkwan University, Suwon, Korea 2 Samsung Electronics, Hwasung, Korea 3 Electronics Engineering Department, Konkuk University, Seoul, Korea E-mail : keewkwon@skku.edu, jhchun@skku.edu

A 1.25 GHz Low Power Multi-phase PLL Using Phase Interpolation between Two Complementary Clocks

Xuefan Jin1, Jun-Han Bae2, Jung-Hoon Chun1, Jintae Kim3, and Kee-Won Kwon1

Abstract—A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from 0° to 360° with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies 0.047 mm2. The jitterrms and jitterpk-pk of the output clock are 1.91 ps and 18 ps, respectively. Index Terms—Phase interpolation, PLL, PFD controller, phase-rotating PLL

I. INTRODUCTION

High-speed and low-power clock and data recovery (CDR) circuits are widely used in wireline communication systems. The multi-phase clock generator and the phase rotator [1] are critical components for phase detection and data sampling in CDR operations. In order to reduce the power and area, it

is desirable to combine the clock generator and the phase rotator. There have recently been a few research groups that developed phase rotating PLLs that are integrated with internal phase adjustment function [2-4]. For example, in [2], a programmable phase shift is achieved by adding the weighted outputs of multiple XOR phase detectors. With no additional phase rotators, this architecture can achieve both low power and small area. However, the design is vulnerable to frequency offset because the XOR phase detectors cannot detect the frequency difference. In a dual phase frequency detector (PFD) phase rotating PLL [3], the internal phase interpolation is realized by two weighted charge pumps (CP) whose contributions are determined by the output pulse widths of the two PFDs before the CPs. However, it demands additional clock multiplexers for coarse phase selection, and the interpolated internal clock phase and the PLL output clock phases are not actually deterministic [4].

This paper proposes a compact and reliable phase rotating PLL which does not need additional multiplexers required in [3], but still covers the entire phase range from 0° to 360°. By controlling the initiation timing of the PFDs, this architecture also solves the problem of non-deterministic behavior.

This paper is organized as follows. Section 2 describes the operation mechanism of the conventional phase rotating PLL and its problems. The proposed phase rotating PLL is introduced in Section 3 and its measurement results are demonstrated in Section 4, followed by the conclusions in Section 5.

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II. THE PHASE ROTATING PLL DESIGN

Fig. 1(a) shows the overall architecture of the dual-PFD phase rotating PLL which consists of two MUXes, two PFDs, two weighted CPs, a loop filter (LF), and a ring-type voltage controlled oscillator (VCO). In this design, the phase adjustment is realized by adding a PFD and a CP to the conventional PLL architecture.

There are two control signals for coarse and fine control of the clock phase, respectively. The coarse control signals [M0, M1] for two 2-to-1 MUXes select the clock phases out of two 90° apart VCO outputs. The phases of the two selected clocks (ΦOUT1 and ΦOUT2) are compared with the reference clock ΦREF in each PFD. The UP/DN signals from the two PFDs are then fed into the two charge pumps, CP1 and CP2, respectively. The charge pump currents, ICP1 and ICP2, are complementarily controlled by the fine control signal. That is, if ICP1 is ‘α x I’, then ICP2 is set to ‘(1- α) x I’. Here, α is the weighting factor. In this way, the phase of ΦREF is finely controlled and locked between the selected clocks. For example, Fig. 1(b), illustrates the case when ΦOUT1 is Φ180

and ΦOUT2 is Φ90 with [M0, M1] being [1, 0]. The ΦREF is then determined by the weighted sum of ΦOUT1 and ΦOUT2:

1 21 0 1= + - £ £REF ΟUΤ ΟUΤΦ αΦ ( α)Φ ( α ) (1)

To cover the entire phase range, a CDR circuit should

control [M0, M1] and α to obtain the optimum sampling points. Fig. 2(a) shows the timing relationship between data, reference clock, and sampling clocks when the CDR is locked. Note that the sampling clocks are located at the optimum sampling positions. In this example, the ΦREF is located between Φ90 and Φ180; therefore, the CDR circuit should set [M0, M1] as [1, 0]. The fine control signal, α is also determined by the CDR, so that Φ180

comes close to ΦREF. As a result, Φ0 and Φ180 are aligned with the center of the data eyes, and Φ90 and Φ270 are aligned with the edges. Fig. 2(b) shows the UP/DN signals from the PFDs and charge pump currents when the CDR is locked. The peak of ICP2 is higher than that of ICP1, but the net average charge to the LF is zero because

(a)

(b)

Fig. 1. (a) The dual-PFD phase rotating PLL, (b) Operating principle.

(a)

(b)

Fig. 2. (a) Timing diagram of CDR operation, (b) The phase interpolation result when [M0, M1] is [1, 0] and α is 0.2.

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Φ180 is closer to ΦREF than Φ90. In other words, the amount of charge supplied by ICP2 as denoted as A2 in Fig. 2(b) is equal to the charge drawn by ICP1 as denoted as A1.

However, the dual-PFD phase rotating PLL has the problem of nondeterministic characteristics. That is, the interpolation process and the resulting clock locations can vary even though all control signals are fixed. An example of failure is illustrated in Fig. 3. In this example, [M0, M1] is [0, 0] and the weighting factor α is 0.2. Hence, the PFDs receive the same input phases, Φ0 and Φ90, and we would expect ΦREF to eventually be located between Φ0 (=ΦOUT1) and Φ90 (=ΦOUT2) as shown in Fig. 3(a). In this case, PFD1 compares the 1st rising edge of ΦOUT1 with ΦREF to generate the DN1 signal and PFD2 compares the 1st rising edge of ΦOUT2 with ΦREF to generate the UP2 signal. As a result, ΦREF is locked between Φ0 and Φ90 and is closer to Φ90 than Φ0 because the weighting factor α is as low as 0.2.

However, there is another possible interpolation result, which is illustrated in Fig. 3(b). In this case, PFD1 compares the 2nd rising edge of ΦOUT1, not the 1st, with

ΦREF to generate the UP1 signal and PFD2 compares the 1st rising edge of ΦOUT2 with ΦREF to generate the DN2 signal. As a result, ΦREF is locked between Φ90 and Φ360 and is closer to Φ90. A new method to avoid this nondeterministic problem is described in the next section.

III. THE PROPOSED PHASE ROTATING PLL

There is a preconception that phase interpolation cannot be achieved by only using two complementary clocks, Ф0 and Ф180. As illustrated in Fig. 4, the waveform C is the outcome of the interpolation between waveforms A (Ф0) and B (Ф180).

When the phase interpolation is achieved by two clocks which are spaced 180° apart, only the amplitude of the interpolated clock is reduced, while the phase is still 0° or 180°, depending on the interpolation weight. Therefore, the dual-PFD phase rotating PLL in Fig. 1 utilizes the four clocks from the VCO and employs two multiplexers in front of the two PFDs to get the interpolation clocks.

This work replaces the multiplexors by a PFD controller (PFDC) in order to overcome the limitation of a conventional multiplexer-based interpolator as well as solving the nondeterministic problem described in the previous section. In the proposed PLL shown in Fig. 5(a), the phase interpolation is realized by only two complementary clocks Φ0 and Φ180. PFD1 receives the reference clock, ФREF, and Ф0 from the VCO and PFD2 receives ФREF and Ф180. The PFDC controls the activation timing of the two PFDs and determines where ФREF is placed, in either the upper or lower plane in Fig. 5(b).

Fig. 6 shows the structure of the PFDC. The PFDC receives Φ0 and Φ180 from VCO and, depending on the coarse control signal, it selects either Φ0 or Φ180 to adjust the activation timing. Whenever the coarse signal changes, the PFDC first deactivates the two PFDs.

(a)

(b)

Fig. 3. Two different phase interpolation results when α is 0.2 (a) Desired interpolation between 0° and 90°, (b) Undesired interpolation between 90° and 360°.

Fig. 4. Phasor diagram.

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Afterwards, the internal pulse generator, PG, generates a short pulse whose width is about one clock period. This short pulse is fetched by Φ0 if the coarse signal is ‘1’ or by Φ180 if the coarse signal is ‘0’. That is, the timing of EN assertion is determined by the coarse signal. Fig. 7(a) and (b) show how the PFDC is incorporated with the other parts of the PLL to perform the phase interpolation. Fig. 7(a) shows the phase interpolation between Ф0 and Ф180 when the coarse signal is 0 and α is 0.2. Fig. 7(b) shows the phase interpolation between Ф180 and Ф360 with the same value of α, but when the coarse signal is 1. As shown in Fig. 7, if we want to adjust ФREF from Ф0 to Ф180, the PFDC asserts EN right after the rising edge of

Ф180 and then the PFDs are activated. On the contrary, if we want to adjust ФREF from Ф180 to Ф360, the PFDC selects Ф0 and sends EN signal to activate the PFD. As a result, the PFDC can adjust the activation timing of the PFDs depending on the desired phase, so that the proposed PLL can effectively solve the non-deterministic problem in the dual-PFD phase rotating PLL.

The resolution of phase interpolation is determined by the 1-bit coarse control signal and 4-bit fine control signal. The total net current to the loop filter is controlled by the fine control signal and finally the phase is adjusted from Ф0 to Ф360.

In the previous design [3], the fine control signal is used to select the number of current sources in each CP, which results in relatively poor linearity of the CP

(a)

(b)

Fig. 5. (a) Architecture of the proposed PLL, (b) Operating principle.

Fig. 6. The proposed PFDC circuit.

(a)

(b)

Fig. 7. Timing diagram for the proposed PLL (a) interpolation between 0° and 180°, (b) between 180° and 360°.

Fig. 8. Interpolation results according to 4-bit fine digital code.

598 XUEFAN JIN et al : A 1.25 GHZ LOW POWER MULTI-PHASE PLL USING PHASE INTERPOLATION BETWEEN TWO …

current, because the drain voltage will vary with the number of selected current sources. In the proposed PLL, the CP consists of multiple segments and the fine control signal determines the number of selected segments, improving overall linearity of phase control. Fig. 8 shows the simulated waveforms of the single-phase clock while incrementally changing the 4-bit fine digital code. It shows that the phase is controlled linearly by the 4-bit fine digital code.

Fig. 9(a) shows the VCO control voltage in the proposed and conventional circuits, with two different PLL loop bandwidth, BWloop. When the reference clock is locked in the middle of two adjacent clocks (e.g. Φ0 and Φ90 for the conventional, Φ0 and Φ180 for the proposed), the pulse width of UP/DN signal in the proposed circuit is twice as wide as the pulse width in the

conventional circuit. So, the fluctuation of the VCO control voltage in the proposed circuit becomes larger, which may result in slight degradation of output clocks. However, the fluctuation of the control voltage is also affected by the PLL loop bandwidth. The proposed PLL is designed with 1.25 GHz reference clock and 31.25 MHz loop bandwidth. As shown in Fig. 9(a), with the PLL loop bandwidth of 31.25 MHz, the fluctuations of the control voltage in the proposed circuit (solid lines) and that in the conventional circuit (dashed lines) are 1.2 mV and 0.8 mV, respectively. As a result, the peak-to-peak jitter, jitterPK-PK, of the proposed PLL is degraded comparing with the conventional PLL, but the difference is only 0.15 ps as shown in Fig. 9(b). The difference in the peak-to-peak jitter between the proposed and the conventional PLLs is increased to 0.2 ps as the loop bandwidth is doubled to 62.5 MHz. However, the jitter induced by the fluctuation of the control voltage is still negligible.

IV. MEASUREMENT RESULTS

The proposed phase rotating PLL is implemented in a 110 nm CMOS process and the operation frequency is 1.25 GHz. The proposed PLL occupies 190 µm x 250 µm, as shown in Fig. 10, and consumes 3.36 mW of power from a 1.2 V supply. As shown in Fig. 11, at a frequency of 1.25 GHz, the jitterrms and jitterpk-pk are 1.9 ps and 18 ps, respectively. The phase interpolation is controlled by the 5-bit digital code and its resolution is 25 ps (800 ps/25).

Fig. 12(a) shows a comparison of the measured delay and ideal delay with the 5-bit digital code. It shows close agreement between the measured delay and ideal delay

(a)

(b)

Fig. 9. The simulation results of (a) VCO control voltage, (b) output clock performance with two different PLL loop bandwidth in the proposed and conventional circuits.

Fig. 10. Photomicrograph of the test chip.

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for the entire range of 5-bit digital code. Fig. 12(b) shows the DNL and INL of the proposed PLL. As illustrated, the DNL is -0.2 LSB ~ +0.2 LSB and the INL is -0.4 LSB ~ +0.12 LSB, showing that the DNL and INL are below 0.5 LSB. The performance of the proposed phase rotating PLL is summarized in Table 1.

V. CONCLUSIONS

In this study, a phase rotating PLL with a PFD controller is proposed and implemented. This phase rotating PLL solves the critical problem which causes the phase interpolation to fail in the dual PFD phase rotating

PLL. By employing a PFD controller that mandates the operation of the PFD occur at the right timing, the unwanted phase interpolation is avoided. With the PFD controller, only two complimentary clocks are needed for phase interpolation, which greatly simplifies the feedback path of the PLL. This new phase interpolation technique can be adopted in the clocking circuits such as conventional LC-PLLs where multi-phase clocks are not available.

ACKNOWLEDGMENTS

This research was supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2015-H8501-15-1010) supervised by the IITP (Institute for Information & communication Technology Promotion). The chip fabrication and EDA tools were supported by the IC Design Education Center at KAIST.

REFERENCES

[1] Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama, and Hubert Siedhoff, “A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 0018-9200, March 2005.

[2] Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel Kossel, Thomas Morf, Robert Reutemann, Michael Ruegg, Martin Schmatz, "A 0.94ps-RMS-jitter 0.016mm2 2.5GHz multi-phase generator PLL with 360° digitally programmable phase shift for 10Gb/s serial links," IEEE J. Solid-State Circiuts, vol. 40, no. 12, pp. 2700-2712, Dec. 2005.

[3] Sungjoon Kim, Dongyun Lee, Young-Soo Park, Yongsam Moon, and Daeyun Shim, "A dual PFD rotating multi-phase PLL for 5Gbps PCI express Gen2 multi-lane serial link receiver in 0.13um CMOS," in IEEE Symposium on VLSI Circuits, Papers, pp. 234-235, 2007.

[4] Jun-Han Bae, Kyoung-Ho Kim, Seok Kim, Kee-Won Kwon, Jung-Hoon Chun, "A low-power dual-PFD phase rotating PLL with a PFD controller for 5Gb/s serial links," in IEEE International

Fig. 11. Measured jitter histogram of output clock.

(a) (b)

Fig. 12. (a) Measured phase steps, (b) DNL and INL of the proposed PLL.

Table 1. Performance Summary

Technology 110 nm CMOS Process Power 3.36 Mw Area 0.047 mm2

Operating Frequency 1.25 GHz PI resolution 25 ps

INL -0.4 LSB~0.12 LSB DNL -0.2 LSB~0.2 LSB

JitterRMS/JitterPK-PK 1.9 ps / 18 ps

600 XUEFAN JIN et al : A 1.25 GHZ LOW POWER MULTI-PHASE PLL USING PHASE INTERPOLATION BETWEEN TWO …

Symposium on Circuits and Systems, Papers, pp. 2159-2162, 2012.

Xuefan Jin received his B.S. degree in the Department of Electronic Communication Engineering from Yanbian University of Science and Technology (YUST), China, in 2010. He is currently pursuing the Combined Master/Ph.D. degree in

the Department of Electrical and Computer Engineering from Sungkyunkwan University, Korea. His research interests are in the design of integrated circuits for high-speed chip-to-chip communications, including clock and data recovery blocks.

Jun-Han Bae received his B.S. and M.S., degrees in the Department of Semiconductor Systems Engineering from Sungkyunkwan University, Korea, in 2011, and 2013, respect- tively. In 2011, he joined at Samsung Electronics, where he has been

working in the area of high-speed interface circuit design. His interests include high speed CMOS circuit design and digital mixed-signal ICs.

Jung-Hoon Chun is an Associate Professor at Sungkyunkwan Univer-sity, Korea. He received his B.S. and M.S. degrees in electrical engineering from Seoul National University, Korea, in 1998 and 2000, respect- tively. In 2006, he received his Ph.D.

degree in electrical engineering from Stanford University. From 2000 to 2001, he worked at Samsung Electronics where he developed BiCMOS RF front-end IC for wireless communication. From 2006 to 2008, he was with Rambus Inc. where he worked on high-speed serial interfaces such as FlexIOTM, XDRTM, XDR2TM. Dr. Chun also consults for several IC design and foundry companies in Korea and Silicon Valley. His current research includes high-speed serial link, on-chip ESD protection and I/O design, new memory devices, etc.

Jintae Kim received the B.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from University of California, Los Angeles, CA, in 2004 and 2008,

respectively. He held various industry positions at Barcelona Design, CA, SiTime Corporation, CA, Agilent Technologies, CA, and Invensense, CA, as a key technical contributor for many sensor, timing, and instrumentation IC products. Since 2012, he has been an assistant professor in Electronics Engineering Department, Konkuk University, Seoul, Korea. Dr. Kim is a recipient of the IEEE Solid-State Circuits Predoctoral Fellowship in 2007-2008.

Kee-Won Kwon received his B.S. degree in metallurgical engineering from Seoul National University, in 1988. He also received his M.S. degree in electrical engineering and the Ph.D. degree in materials science and engineering from Stanford

University, Stanford, CA, in 2000 and 2001, respectively. From 1990 to 1995, he was with Samsung Electronics, Giheung, Korea, where he developed tantalum pentoxide dielectric thin films and successfully implemented them into the commercial product of DRAM. In 2000, he worked for Maxim Integrated Products, Sunnyvale, CA where he was involved in two projects of data converting circuit design. He rejoined Samsung Electronics in 2001, and worked in the areas of high performance DRAM designs including Rambus DRAM and XDR DRAM. In 2007, he moved to Sungkyunkwan University, where he is doing research on memory IP design, and low power high speed circuit solutions for analog and mixed-signal devices.