8 7 6 5 4 3 REV SCHEM,MLB DVT,K99 · mcp conn pwr sata rgb out j9000 external conn display conn j9400 pg 62 display ext usb u1000 pg 38 conn pg 52-57 pg 44 pg 42,43 j5600 pg 45 dp1[1:0]

TABLE_TABLEOFCONTENTS_ITEM







































































3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPDCK

DESCRIPTION OF REVISION

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD


DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL


SCHEM,MLB DVT,K9907/22/10

Schematic / PCB #’s

1 OF 73

051-8379

4.4.0

1 OF 110

2010-07-22

4556

K16_MLB

07/07/2010

Fan

4455

K16_MLB

07/07/2010

Thermal Sensors

4354

K16_MLB

07/07/2010

Current Sensing

4253

K16_MLB

07/07/2010

Voltage & Current Sensing

4152

K16_MLB

07/07/2010

K16/K99 SMus Connections

4051

K16_MLB

07/07/2010

LPC+SPI Debug Connector

3950

K16_MLB

07/07/2010

SMC Support

3849

K16_MLB

07/07/2010

SMC

3747

N/A

N/A

LIO CONNECTORS

3646

K16_MLB

07/07/2010

External USB Connectors

3545

K16_MLB

07/07/2010

SATA CONNECTOR

3440

K16_MLB

07/07/2010

X21 WIRELESS CONNECTOR

3339

K16_MLB

07/07/2010

FSB/DDR3 Vref Margining

3237

K16_MLB

07/07/2010

Memory Active Termination

3136

K16_MLB

07/07/2010

DDR BYPASSING 2

3035

K16_MLB

07/07/2010

DDR BYPASSING 1

2934

K16_MLB

07/07/2010

DDR3 DRAM Channel B (32-63)

2833

K16_MLB

07/07/2010


2732

K16_MLB

07/07/2010

DDR3 DRAM Channel A (32-63)

2631

K16_MLB

07/07/2010


2528

K6_MLB

12/11/2009

SB Misc

2426

K16_MLB

07/07/2010

MCP Graphics Support

2325

K16_MLB

07/07/2010

MCP Standard Decoupling

2224

K16_MLB

07/07/2010

MCP89 GFX Core Rail Gating

2123

K16_MLB

07/07/2010

MCP89 Memory Rail Gating

2020

K16_MLB

07/07/2010

MCP Power & Ground

1919

K16_MLB

07/07/2010

MCP HDA, LPC & MISC

1818

K16_MLB

07/07/2010

MCP SATA, USB & Ethernet

1717

K16_MLB

07/07/2010

MCP Graphics

1616

K16_MLB

07/07/2010

MCP PCIe Interfaces

1515

K16_MLB

07/07/2010

MCP Memory Interface

1414

K16_MLB

07/07/2010

MCP CPU Interface

1313

K16_MLB

07/07/2010

eXtended Debug Port (Micro-XDP)

1212

K16_MLB

03/24/2010

CPU Decoupling & VID

1111

K16_MLB

07/07/2010

CPU Power & Ground

1010

K16_MLB

07/07/2010

CPU FSB

99

K6_MLB

12/11/2009

SIGNAL ALIAS

88

K6_MLB

12/11/2009

Power Aliases

77

K6_MLB

12/11/2009

FUNCTIONAL TEST

66

K24_MLB

01/19/2009

Revision History

55

K24_MLB

07/20/2009

BOM Configuration

44

K6_MLB

12/11/2009

K99 BOM Variants

33

K6_MLB

12/11/2009

Power Block Diagram

22

K6_MLB

12/11/2009

System Block Diagram

110

Acoustic Cap BOM Config Tables K16_MLB

07/07/2010

73

109

K99 RULE DEFINITIONS K16_MLB

07/07/2010

72

108

K16/K99 Specific Constraints K16_MLB

07/07/2010

71

106

SMC Constraints K16_MLB

07/07/2010

70

104

Ethernet Constraints K16_MLB

07/07/2010

69

103

MCP Constraints 2 K16_MLB

07/07/2010

68

102

MCP Constraints 1 K16_MLB

07/07/2010

67

101

Memory Constraints K16_MLB

07/07/2010

66

100

CPU/FSB Constraints K16_MLB

07/07/2010

65

99

Additional CPU/GPU Decoupling K16_MLB

07/07/2010

64

98

LCD Backlight Support K16_MLB

07/07/2010

63

97

LCD Backlight Driver K16_MLB

03/31/2010

62

94

DisplayPort Connector K16_MLB

07/07/2010

61

93

External DisplayPort Support K16_MLB

07/07/2010

60

90

Internal DisplayPort Connector K16_MLB

07/07/2010

59

79

Power FETs K16_MLB

07/07/2010

58

78

Power Sequencing K16_MLB

07/07/2010

57

77

Misc Power Supplies K16_MLB

07/07/2010

56

76

CPUVTT (1.05V) Power Supply K16_MLB

07/07/2010

55

75

MCP VCore Regulator K6_MLB

12/11/2009

54

74

IMVP6 CPU VCore Regulator POWER

07/13/2005

53

73

1.5V/1.35V LVDDR3 Supply K16_MLB

07/07/2010

52

72

5V / 3.3V Power Supply K16_MLB

07/07/2010

51

70

PBus Supply & Battery Charger K6_MLB

11/09/2009

50

69

DC-In & Battery Connectors K84_MLB

11/09/2009

49

66

AUDI0: SPEAKER AMP AUDIO

02/09/2010

48

61

SPI ROM K16_MLB

07/07/2010

47

SCHEM,MLB,K99

Contents(.csa)

SyncDate

Page(.csa)

ContentsDate

SyncPage57

WELLSPRING 1 K16_MLB

07/07/2010

46

1 CRITICALPCB820-2796 PCBF,MLB,K99

SCH1 CRITICAL051-8379 SCHEM,MLB,K99

11

Table of Contents

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:


36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

1.6 GHZ XDP CONN

GPIOMAIN

FSB INTERFACE

PG 36

PG 19

NVIDIA

MCP89U-A01

24.5X24.5MM0.6MM PITCH

1244P

SPEAKER

J6903

SIL+SPEAKER

(IPD)

FAN CONN

ADC

U4900

TRACKPAD

PG 37

AUDIO CODEC

LIO FLEX CONN

PG 34

EXTCAMERAHDA

PE0[4,5]:X2,X1 GEN2,UP TO 2 LANES

PG 35

PG 25

UP TO 2 PORTS

SATA_A0

J4501

PG 25

PG 19

RTC XTAL

PG 13

J1300

1GBPG 10

PG 28,29

PG 48

CONN

PG 19

PG 18

PG 19

USB_4

PG 19

HDA

PG 18PG 16

LAN

PG 17

PG 18

PANELFLAT

PG 26,27

SUPPORT GEN3,6.0GB/S

PG 19BOOTROM

SPI

PG 15

PG 14

USB 2.0

J4600

RIGHT

LPC

PG 10

PG 9

J6702

CONNPG 10

PG 5

LIO BOARD

CONN

J4001

PE1_0PCIE GEN1

Y2815

MCP

CONN

PWR

SATA

RGB OUT

J9000

EXTERNAL

CONN

DISPLAY

CONN

J9400

PG 62

DISPLAY

EXT USB

U1000

PG 38

CONN

PG 52-57

PG 44

PG 42,43

J5600

PG 45

DP1[1:0]

CONN

CONN

CONN

POWER SUPPLY

LIO

CTRL

J5100

A

B

HDMI OUTDVI OUT

RGMII

128MX8

MEMORYU3100,U3200

128MX8

U3300,3400

PG 40

PORTSERIAL

SMB_BSA SMB_B/0 FAN0 SMS

LIDPM_SLP

SYS_LED SMB_A

U5920

HALL EFFECT

PG 50

PG 46

PG 50PG 49

I2C

USBMIKEYI2C

J4610

ALSCONN

CAMERA+J4702

LEFT

PG 6

EXT USB

PG 11

FILTERLINE IN

PG 8

FILTERHEADPHONE

JACKLINE IN

HEADPHONE/J6700

SPEAKERLEFT

AMPS

U6620

SPEAKER

PG 6

CONN

INTERNAL

SSD

PCI-E

CPU/MCP TEMP SENSOR

J6950,U7000

U5515.U5535

SATA

PG 50,51

VOLTAGE/CURRENT SENSOR

PG 47

SMS

CHARGER,BATT CONN

U6610

J6955

S3/S4

DP0[3:0]

PG 60

FCPBGA

SATA 2.0 3GBIT/S

32.768KHZ

X4 DP LINK

25MHZ

BLUETOOTH

Y2810

AIRPORT+

J4700

U6201

AMPS

J5700

USB_2

USB_6

USB_0

USB_5

SMCLPC+SPI

USB_7

(UP TO 8 DEVICES)

LVDS OUT

TMDS OUT

USB SPK

SPI

U6100

INTEL CPU

MISC

PG 19

DDR3-1066/1333MHZ

DDR3-1066/1333MHZ

64-BIT

MEMORY

64-BIT

FSB64-BIT800MHZBASE FREQ.=200MHZ

PENRYN

PE1[0,1]:X1,X1 GEN1,UP TO 2 LANES

X2 DP LINK

SMB

1GB

MEMORY

SYNC_MASTER=K6_MLB SYNC_DATE=12/11/2009

System Block Diagram

2 OF 110

4.4.0

051-8379

2 OF 73




36

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SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MAX8840

PP1V05_S0_MCP_PLL_REG

MCP89

DELAY

RC

DELAY

RC

DELAY

RC

RC P1V8S0_EN

MCPCORES0_EN

CPUVTTS0_EN

DDRVTT_EN

16-5

16-6

PM_SLP_S3_L

16-3

16-4

AP_PWR_ENQ7890

(9 TO 12.6V)

3S2P

PM_SLP_S3_L

U1400

PM_SLP_S4_L

MCP89 11

15

DELAYRC

11-2

RCDELAY

11-3

11-1

J6950

PBUSVSENSE_EN

DELAY

PM_WLAN_EN_L

RC P3V3S0_EN

(S0)

(S0)

16-2

16-1

16-1

04-1

=DDRREG_EN

=DDTVTT_EN

S5

S3

U7300

MCPCORES0_EN

VOUT2

TPS51116

0.75V

VOUT1

02

VIN

EN

VIN

02

1.5V

P5VS3_EN_L

P3V3S3_EN

BKLT_EN

U4900

SMC

P60

P16

ENA

02

(S5)

01

A

ADAPTER

AC

IN

6A FUSE

01

A

ENABLES

PP18V5_DCIN_CONN

VOUT

PPVBAT_G3H_CHGR_REG

Q7085

P3V3S5_EN_L

IMVP_VR_ON_R

25

02

U7500

VOUT

(25A MAX CURRENT)

20

PP1V5_S3_REG

ISL8009B

VIN

VOUT

R7525

P3V3S0_EN

U7720

1.2V

U7710

ISL8009B

U7740

1.8V

TPS62202

U7760

1.5V

EN2

05

VIN

EN1

02

3.3V

(RT)5V

VREG3

VR_ON

VIN

PP3V3_S5_REG

Q7910

28

V

PP3V3_S0_FET

PP1V8_S0_REG

PP1V5_S0_REG

PP3V3_S0

PP1V5_S0

PP1V05_S0

V2

V1

RST*

U7870

P1V5S0_PGOOD

P5V3V3_PGOOD

MCPCORES0_PGOOD

SLP_S5_L

SLP_S4_L

SLP_S3_L

09

ALL_SYS_PWRGD

05

SMC_ONOFF_L

RSMRST_PWRGD

SLP_S4_L(P94)

SLP_S3_L(P93)

SLP_S5_L(P95)

U4900

PWRGD(P12)

PWR_BUTTON(P90)

RSMRST_IN(P13)

99ms DLY

26

VIN

EN

U6200VOUT

4.5V AUDIO

PP4V5_AUDIO_ANALOG

24

07

17

Q7940

P5VS0_EN

PP5V_S0_FET

SMC

29

U1000

CPU

U1400

PWRGD

02

CPUVTTS0_EN

02

EN_PSV

VIN

LT3470

ENABLE

U6990VOUT

3.425V G3HOT

PBUS_G3H_VSENSE

PP1V05_S0

(8A MAX CURRENT)

PP3V42_G3H_REG03

RN5VD30A-F

SMC PWRGD

U5010

04

RST*

P17(BTN_OUT)

IMVP_VR_ON(P16)

RSMRST_OUT(P15)

PLT_RST*

CPU_RESET#

PWRBTN*

PLTRST*

RESET*

CPUPWRGD(GPIO49)

PWRGOOD

RSMRST*

IMVP_VR_ON_R

PM_PWRBTN_L

SMC_RESET_L

25

PM_RSMRST_L

32

10

FSB_CPURST_L

30

CPU_PWRGD

LPC_RESET_L

31

06-1

13

PP5V_S3_REG

(5.5A MAX

PGOOD1,2

ISL88042V3

PPBUS_G3H

V

PPDCIN_G3H_OR_PBUS

16

21

Q5315

EN

Q7890,Q7891

DELAY

P1V5S0_ENP5VS0_EN

DCIN(16.5V)

DDRREG_EN

P5VS3_EN_L

SMC_DCIN_ISENSE

(S0)F6905

Q7055

PPVBAT_G3H_CHGR_R

R7020

VIN

(S5)

ISL6259

U7000

8A FUSE

F7040

VOUT

Q7080

PBUS_VSENSE

PGOOD

U7600

SMC_CPU_VSENSE

CPUVTTS0_PGOOD

VOUT

CPUVTT

ISL95870

(1.05V)

PPBUS_G3H

CPU VCORE

ISL6261A

U7400

PGOOD

VOUT1

VOUT2

VR_PWRGOOD_DELAY

SMC_CPU_ISENSE

PPVCORE_S0_CPU

(44A MAX CURRENT)

MC34845

VIN

VOUT

U9700

TPS51980

P5V3V3_PGOOD

04

PPVOUT_SW_LCDBKLT

ST1S12G12R

U7201

PPMCPCORE_S0_R

14

PM_SLP_S3_L

SMC_ADAPTER_EN

ISL9563B

1.05V

PP1V2_ENET_REG

TPS74701

S0PGOOD_RST_L

U7750

(13A MAX CURRENT)

CURRENT)

P3V3S3_EN

Q7930

(12A MAX CURRENT)

PP0V75_S0_REG(1A MAX CURRENT)

PPMCPCORE_S0_REGMCP_CORE

MCPMEM_GATE

Q2300

MCP_PS_PWRGD

U2850

CPUVTTS0_PGOOD

MCPPLLDO_PGOOD

18

P3V3_S3_WLAN

PM_WLAN_EN_L

Q4050

PP3V3_S3_FET

PPVBAT_G3H_CONN

CHGR_BGATE

PP1V5R1V35_SW_MCP

PP0V9_S5_REG

U7840

SMC_PM_G2_EN

BATTERY CHARGER

PBUS SUPPLY/

CHGR_EN

SMC_BATT_ISENSER7050

K99 POWER SYSTEM ARCHITECTURE Need to update!!!

SYNC_DATE=12/11/2009SYNC_MASTER=K6_MLB

Power Block Diagram

3 OF 110

4.4.0

051-8379

3 OF 73

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

BOM Variants

Sub-BOMs

Bar Code Labels / EEE #’s

4GB

DIE REV CFG 3CFG 2

1

0

B

A

HYNIX

1

0

SIZE

2GB

DRAM CFG CHART

0 0

1

CFG 0CFG 1VENDOR

0SAMSUNG

0 1

1ELPIDA 1

MICRON

K99_CMNPTS,CPU:1.6GHZ,EEE:DD0L,DDR3:HYNIX_4GB,CAPS:TY639-1039 PCBA,MLB,HY 4GB,TY CAP,K99

PCBA,MLB,SA 4GB,TY CAP,K99639-1040 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0M,DDR3:SAMSUNG_4GB,CAPS:TY

K99_CMNPTS,CPU:1.6GHZ,EEE:DD0W,DDR3:MICRON_2GB,CAPS:TY639-1047 PCBA,MLB,MI 2GB,TY CAP,K99

639-1051 PCBA,MLB,MI 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD11,DDR3:MICRON_4GB,CAPS:SS

639-1446 PCBA,MLB,1.6GHZ,EL 2GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4Q,DDR3:ELPIDA_2GB,CAPS:SS

K99_CMNPTS,CPU:1.4GHZ,EEE:DF83,DDR3:HYNIX_2GB,CAPS:MU639-1341 PCBA,MLB,1.4GHZ,HY 2GB,MU CAP,K99

K99_CMNPTS,CPU:1.4GHZ,EEE:DF8N,DDR3:SAMSUNG_2GB,CAPS:TYPCBA,MLB,1.4GHZ,SA 2GB,TY CAP,K99639-1357

1 CRITICALLABEL,MLB,K16/K99 [EEE_DG4M] EEE:DG4M825-7557

1 LABEL,MLB,K16/K99 CRITICAL[EEE_DG4R] EEE:DG4R825-7557

1 CRITICALLABEL,MLB,K16/K99 [EEE_DG4L] EEE:DG4L825-7557

CRITICAL1 LABEL,MLB,K16/K99 [EEE_DG4V] EEE:DG4V825-7557

1 CRITICALLABEL,MLB,K16/K99 [EEE_DG4T] EEE:DG4T825-7557

1 LABEL,MLB,K16/K99 CRITICAL[EEE_DG4Q] EEE:DG4Q825-7557

1 CRITICALLABEL,MLB,K16/K99 [EEE_DG4P] EEE:DG4P825-7557

1 LABEL,MLB,K16/K99 CRITICAL[EEE_DG4N] EEE:DG4N825-7557

1 LABEL,MLB,K16/K99 CRITICAL[EEE_DG4K] EEE:DG4K825-7557

1 CRITICALLABEL,MLB,K16/K99 [EEE_DG4J] EEE:DG4J825-7557

1 CRITICALLABEL,MLB,K16/K99 [EEE_DG4G] EEE:DG4G825-7557

CRITICAL1 LABEL,MLB,K16/K99 EEE:DF8N[EEE_DF8N]825-7557

1 CRITICALLABEL,MLB,K16/K99 EEE:DF8L[EEE_DF8L]825-7557

1 LABEL,MLB,K16/K99 CRITICAL[EEE_DF8J] EEE:DF8J825-7557

1 LABEL,MLB,K16/K99 CRITICAL[EEE_DF8G] EEE:DF8G825-7557

1 LABEL,MLB,K16/K99 CRITICAL[EEE_DF8D] EEE:DF8D825-7557

1 LABEL,MLB,K16/K99 CRITICAL[EEE_DF89] EEE:DF89825-7557

EEE:DF87LABEL,MLB,K16/K99 CRITICAL1 [EEE_DF87]825-7557

EEE:DF86LABEL,MLB,K16/K99 CRITICAL1 [EEE_DF86]825-7557

EEE:DF85CRITICAL1 LABEL,MLB,K16/K99 [EEE_DF85]825-7557

EEE:DF84CRITICAL1 LABEL,MLB,K16/K99 [EEE_DF84]825-7557

EEE:DF83[EEE_DF83]1 CRITICALLABEL,MLB,K16/K99825-7557

CRITICAL1 EEE:DD15LABEL,MLB,K16/K99 [EEE_DD15]825-7557

[EEE_DD13]1 CRITICAL EEE:DD13LABEL,MLB,K16/K99825-7557

1 CRITICAL[EEE_DD12] EEE:DD12LABEL,MLB,K16/K99825-7557

[EEE_DD10]1 LABEL,MLB,K16/K99 CRITICAL EEE:DD10825-7557

1 CRITICAL[EEE_DD0X] EEE:DD0XLABEL,MLB,K16/K99825-7557

LABEL,MLB,K16/K991 [EEE_DD0W] EEE:DD0WCRITICAL825-7557

[EEE_DD0V]LABEL,MLB,K16/K99 CRITICAL1 EEE:DD0V825-7557

[EEE_DD0T]1 EEE:DD0TCRITICALLABEL,MLB,K16/K99825-7557

CRITICAL1 [EEE_DD0Q]LABEL,MLB,K16/K99 EEE:DD0Q825-7557

CRITICAL1 EEE:DD0P[EEE_DD0P]LABEL,MLB,K16/K99825-7557

1 CRITICAL[EEE_DD0N]LABEL,MLB,K16/K99 EEE:DD0N825-7557

[EEE_DD0M] CRITICAL EEE:DD0MLABEL,MLB,K16/K991825-7557

1 CRITICAL[EEE_DD0L] EEE:DD0LLABEL,MLB,K16/K99825-7557639-1055 PCBA,MLB,HY 2GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD15,DDR3:HYNIX_2GB,CAPS:MU

PCBA,MLB,HY 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0R,DDR3:HYNIX_4GB,CAPS:MU639-1044

639-1054 K99_CMNPTS,CPU:1.6GHZ,EEE:DD14,DDR3:SAMSUNG_2GB,CAPS:MUPCBA,MLB,SA 2GB,MU CAP,K99

K99 BOM VariantsSYNC_DATE=12/11/2009SYNC_MASTER=K6_MLB

1 LABEL,MLB,K16/K99 CRITICAL[EEE_DG4H] EEE:DG4H825-7557

1 LABEL,MLB,K16/K99 CRITICAL[EEE_DF8K] EEE:DF8K825-7557

639-1445 PCBA,MLB,1.6GHZ,EL 4GB,TY CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4P,DDR3:ELPIDA_4GB,CAPS:TY

K99_COMMONCMN PTS,PCBA,MLB,K99607-6999 1 CRITICALLABEL,MLB,K16/K99 [EEE_DF88] EEE:DF88825-7557

1 CRITICALLABEL,MLB,K16/K99 [EEE_DF8C] EEE:DF8C825-7557

1 CRITICALLABEL,MLB,K16/K99 [EEE_DF8F] EEE:DF8F825-7557

1 CRITICALLABEL,MLB,K16/K99 [EEE_DF8H] EEE:DF8H825-7557

CRITICAL EEE:DF8M1 LABEL,MLB,K16/K99 [EEE_DF8M]825-7557

K99_CMNPTS,CPU:1.4GHZ,EEE:DF8L,DDR3:HYNIX_2GB,CAPS:SS639-1355 PCBA,MLB,1.4GHZ,HY 2GB,SS CAP,K99

K99 MLB DEVELOPMENT BOM K99_DEVEL:ENG085-1121

639-1448 PCBA,MLB,1.6GHZ,EL 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4T,DDR3:ELPIDA_4GB,CAPS:MU

PCBA,MLB,1.6GHZ,EL 4GB,SS CAP,K99639-1449 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4V,DDR3:ELPIDA_4GB,CAPS:SS

639-1444 PCBA,MLB,1.6GHZ,EL 2GB,TY CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4N,DDR3:ELPIDA_2GB,CAPS:TY

639-1438 PCBA,MLB,1.6GHZ,EL 2GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4G,DDR3:ELPIDA_2GB,CAPS:MU

639-1050 K99_CMNPTS,CPU:1.6GHZ,EEE:DD10,DDR3:MICRON_4GB,CAPS:TYPCBA,MLB,MI 4GB,TY CAP,K99

639-1049 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0Y,DDR3:SAMSUNG_2GB,CAPS:TYPCBA,MLB,SA 2GB,TY CAP,K99

1 CRITICAL[EEE_DD11] EEE:DD11LABEL,MLB,K16/K99825-7557

EEE:DF82CRITICAL[EEE_DF82]LABEL,MLB,K16/K991825-7557

[EEE_DD14] EEE:DD14CRITICAL1 LABEL,MLB,K16/K99825-7557

LABEL,MLB,K16/K99 [EEE_DD0Y] EEE:DD0YCRITICAL1825-7557

K99_CMNPTS,CPU:1.6GHZ,EEE:DX7,DDR3:HYNIX_2GB,CAPS:SS639-0651 PCBA,MLB,HY 2GB,SS CAP,K99

PCBA,MLB,HY 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0Q,DDR3:HYNIX_4GB,CAPS:SS639-1043

PCBA,MLB,1.4GHZ,HY 4GB,TY CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8C,DDR3:HYNIX_4GB,CAPS:TY639-1348

639-1356 PCBA,MLB,1.4GHZ,HY 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8M,DDR3:HYNIX_4GB,CAPS:MU

639-1350 PCBA,MLB,1.4GHZ,HY 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8F,DDR3:HYNIX_4GB,CAPS:SS

639-1045 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0T,DDR3:SAMSUNG_2GB,CAPS:SSPCBA,MLB,SA 2GB,SS CAP,K99 [EEE_DD0R]1 CRITICAL EEE:DD0RLABEL,MLB,K16/K99825-7557

PCBA,MLB,1.4GHZ,EL 2GB,SS CAP,K99639-1442 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4L,DDR3:ELPIDA_2GB,CAPS:SS

PCBA,MLB,1.4GHZ,EL 2GB,MU CAP,K99639-1443 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4M,DDR3:ELPIDA_2GB,CAPS:MU

LABEL,MLB,K16/K99 [EEE_DX7]1 CRITICAL825-7557 EEE:DX7

K99_CMNPTSCRITICALCMNPTSCMN PTS,PCBA,MLB,K99607-6999 1

DEVEL_BOMK99 MLB DEVELOPMENT BOM DEVEL CRITICAL085-1121 1

K99_CMNPTS,CPU:1.4GHZ,EEE:DF88,DDR3:MICRON_2GB,CAPS:MUPCBA,MLB,1.4GHZ,MI 2GB,MU CAP,K99639-1346

PCBA,MLB,1.4GHZ,EL 2GB,TY CAP,K99639-1447 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4R,DDR3:ELPIDA_2GB,CAPS:TY

PCBA,MLB,1.4GHZ,EL 4GB,TY CAP,K99639-1440 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4J,DDR3:ELPIDA_4GB,CAPS:TY

PCBA,MLB,1.4GHZ,EL 4GB,MU CAP,K99639-1439 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4H,DDR3:ELPIDA_4GB,CAPS:MU

PCBA,MLB,1.4GHZ,EL 4GB,SS CAP,K99639-1441 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4K,DDR3:ELPIDA_4GB,CAPS:SS

K99_CMNPTS,CPU:1.4GHZ,EEE:DF82,DDR3:MICRON_4GB,CAPS:TYPCBA,MLB,1.4GHZ,MI 4GB,TY CAP,K99639-1340

PCBA,MLB,1.4GHZ,MI 4GB,MU CAP,K99639-1345 K99_CMNPTS,CPU:1.4GHZ,EEE:DF87,DDR3:MICRON_4GB,CAPS:MU

K99_CMNPTS,CPU:1.4GHZ,EEE:DF84,DDR3:MICRON_2GB,CAPS:SSPCBA,MLB,1.4GHZ,MI 2GB,SS CAP,K99639-1342

K99_CMNPTS,CPU:1.4GHZ,EEE:DF8K,DDR3:SAMSUNG_4GB,CAPS:TYPCBA,MLB,1.4GHZ,SA 4GB,TY CAP,K99639-1354

639-1353 PCBA,MLB,1.4GHZ,HY 2GB,TY CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8J,DDR3:HYNIX_2GB,CAPS:TY

K99_CMNPTS,CPU:1.4GHZ,EEE:DF8G,DDR3:SAMSUNG_2GB,CAPS:MU639-1351 PCBA,MLB,1.4GHZ,SA 2GB,MU CAP,K99

PCBA,MLB,1.4GHZ,SA 2GB,SS CAP,K99639-1349 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8D,DDR3:SAMSUNG_2GB,CAPS:SS

PCBA,MLB,1.4GHZ,MI 4GB,SS CAP,K99639-1347 K99_CMNPTS,CPU:1.4GHZ,EEE:DF89,DDR3:MICRON_4GB,CAPS:SS

K99_CMNPTS,CPU:1.4GHZ,EEE:DF85,DDR3:MICRON_2GB,CAPS:TYPCBA,MLB,1.4GHZ,MI 2GB,TY CAP,K99639-1343

K99_CMNPTS,CPU:1.4GHZ,EEE:DF86,DDR3:SAMSUNG_4GB,CAPS:SS639-1344 PCBA,MLB,1.4GHZ,SA 4GB,SS CAP,K99

K99_CMNPTS,CPU:1.4GHZ,EEE:DF8H,DDR3:SAMSUNG_4GB,CAPS:MUPCBA,MLB,1.4GHZ,SA 4GB,MU CAP,K99639-1352

639-1052 PCBA,MLB,SA 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD12,DDR3:SAMSUNG_4GB,CAPS:SS

PCBA,MLB,MI 2GB,SS CAP,K99639-1042 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0P,DDR3:MICRON_2GB,CAPS:SS

PCBA,MLB,MI 2GB,MU CAP,K99639-1053 K99_CMNPTS,CPU:1.6GHZ,EEE:DD13,DDR3:MICRON_2GB,CAPS:MU

639-1041 PCBA,MLB,MI 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0N,DDR3:MICRON_4GB,CAPS:MU

PCBA,MLB,SA 4GB,MU CAP,K99639-1046 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0V,DDR3:SAMSUNG_4GB,CAPS:MU

639-1048 PCBA,MLB,HY 2GB,TY CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0X,DDR3:HYNIX_2GB,CAPS:TY

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TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM


TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD




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BOM Groups

Programmable PartsModule Parts

Alternate Parts

BOM ConfigurationSYNC_MASTER=K24_MLB SYNC_DATE=07/20/2009

104S0018104S0023 CYNTEC/DALE AS ALTERNATESALL

155S0367 TAIYO AS ALTERNATEALL155S0578

ALL376S0926 376S0610 FAIRCHILD AS ALTERNATE

TAIYO AS ALTERNATE138S0673138S0671 ALL

107S0139 CYNCTEC AS ALTERNATE107S0075 ALL

138S0681 138S0638 ALL TAIYO YUDEN AS ALTERNATE

MAGLAYERS AS ALTERNATEALL152S0516152S0874

IC,SMC,HS8/2117,9X9MM,TLP,HF338S0563 U4900 CRITICAL SMC:BLANK1

DEVEL_BOM,SMC_DEBUG:YES,XDPK99_DEBUG:ENG

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NOK99_DEBUG:PVT

BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NOK99_DEBUG:PROD

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GBDDR3:HYNIX_2GB

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GBDDR3:HYNIX_4GB

DDR3:ELPIDA_4GB DRAM_CFG0:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB

BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,MCPPLL_LDO,S3_S0_LEDK99_DEVEL:ENG

HVDDLDO:FIXED TPS71725DCK AS ALTERNATE FOR U2590353S2987 353S2988 ALL

335S0610 U6100 CRITICAL BOOTROM:BLANKIC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP1

341T0262 CRITICALIC ASSY,EFI UNLOCKED,K99 U61001 BOOTROM:UNLOCKED

333S0555 HYNIX,LVDDR3,2GBIT,9X11.1 DRAM_TYPE:HYNIX_4GBU3400,U3410,U3420,U3430 CRITICAL4

CRITICALU3200,U3210,U3220,U3230SAMSUNG,LVDDR3,2GBIT,7.5X11.04333S0556 DRAM_TYPE:SAMSUNG_4GB

SAMSUNG,LVDDR3,2GBIT,7.5X11.0 CRITICAL DRAM_TYPE:SAMSUNG_4GBU3400,U3410,U3420,U34304333S0556

MICRON,LVDDR3,2GBIT,9X11.5333S0557 CRITICAL4 DRAM_TYPE:MICRON_4GBU3100,U3110,U3120,U3130

333S0566 DRAM_TYPE:ELPIDA_4GBU3200,U3210,U3220,U3230 CRITICAL4 ELPIDA,LVDDR3,2GBIT,9X11.5

U3400,U3410,U3420,U3430333S0566 DRAM_TYPE:ELPIDA_4GB4 CRITICALELPIDA,LVDDR3,2GBIT,9X11.5

ISL6259_SCREENED:NOIC,ISL6259,BATCHARGER,4X4MM,QFN28353S2392 1 U7000 CRITICAL

U7000 ISL6259_SCREENED:YES353S2929 1 IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28 CRITICAL

U3200,U3210,U3220,U3230333S0555 4 DRAM_TYPE:HYNIX_4GBHYNIX,LVDDR3,2GBIT,9X11.1 CRITICAL

333S0557 MICRON,LVDDR3,2GBIT,9X11.54 CRITICAL DRAM_TYPE:MICRON_4GBU3200,U3210,U3220,U3230

333S0557 DRAM_TYPE:MICRON_4GB4 CRITICALU3300,U3310,U3320,U3330MICRON,LVDDR3,2GBIT,9X11.5

333S0566 U3100,U3110,U3120,U31304 CRITICALELPIDA,LVDDR3,2GBIT,9X11.5 DRAM_TYPE:ELPIDA_4GB

ASSEMBLY,SUBASSY,PCBA HALL EFFECT, K99 J6955 CRITICAL1607-6811

U3100,U3110,U3120,U3130333S0555 DRAM_TYPE:HYNIX_4GBHYNIX,LVDDR3,2GBIT,9X11.14 CRITICAL

ELPIDA,LVDDR3,1GBIT,7.5X10.6 DRAM_TYPE:ELPIDA_2GB333S0565 U3400,U3410,U3420,U34304 CRITICAL

U3300,U3310,U3320,U3330333S0555 DRAM_TYPE:HYNIX_4GBCRITICAL4 HYNIX,LVDDR3,2GBIT,9X11.1

U3300,U3310,U3320,U3330333S0556 SAMSUNG,LVDDR3,2GBIT,7.5X11.0 DRAM_TYPE:SAMSUNG_4GB4 CRITICAL

MAGLAYERS AS ALTERNATE155S0329155S0457 ALL

SAMSUNG,LVDDR3,2GBIT,7.5X11.0333S0556 U3100,U3110,U3120,U3130 DRAM_TYPE:SAMSUNG_4GB4 CRITICAL

U3100,U3110,U3120,U3130333S0552 HYNIX,LVDDR3,1GBIT,7.5X11.04 CRITICAL DRAM_TYPE:HYNIX_2GB

HYNIX,LVDDR3,1GBIT,7.5X11.0 U3200,U3210,U3220,U3230333S0552 CRITICAL4 DRAM_TYPE:HYNIX_2GB

333S0552 HYNIX,LVDDR3,1GBIT,7.5X11.04 U3300,U3310,U3320,U3330 DRAM_TYPE:HYNIX_2GBCRITICAL

HYNIX,LVDDR3,1GBIT,7.5X11.0333S0552 U3400,U3410,U3420,U34304 DRAM_TYPE:HYNIX_2GBCRITICAL

333S0553 U3200,U3210,U3220,U3230 CRITICAL4 DRAM_TYPE:SAMSUNG_2GBSAMSUNG,LVDDR3,1GBIT,7.5X11.0

U3300,U3310,U3320,U33304 DRAM_TYPE:SAMSUNG_2GBCRITICAL333S0553 SAMSUNG,LVDDR3,1GBIT,7.5X11.0

333S0554 CRITICALU3100,U3110,U3120,U31304 MICRON,LVDDR3,1GBIT,8X11.5 DRAM_TYPE:MICRON_2GB

CRITICAL333S0554 MICRON,LVDDR3,1GBIT,8X11.54 U3200,U3210,U3220,U3230 DRAM_TYPE:MICRON_2GB

DRAM_TYPE:ELPIDA_2GBELPIDA,LVDDR3,1GBIT,7.5X10.6333S0565 U3200,U3210,U3220,U32304 CRITICAL

DRAM_TYPE:ELPIDA_2GBELPIDA,LVDDR3,1GBIT,7.5X10.6333S0565 U3300,U3310,U3320,U33304 CRITICAL

DRAM_TYPE:ELPIDA_2GBELPIDA,LVDDR3,1GBIT,7.5X10.6333S0565 4 U3100,U3110,U3120,U3130 CRITICAL

CRITICAL4 MICRON,LVDDR3,1GBIT,8X11.5333S0554 U3300,U3310,U3320,U3330 DRAM_TYPE:MICRON_2GB

MICRON,LVDDR3,1GBIT,8X11.5 CRITICAL4333S0554 U3400,U3410,U3420,U3430 DRAM_TYPE:MICRON_2GB

337S3820 U1400 CRITICAL1 MCP89U:A01IC,MCP89U-A01,24.5MMX24.5MM,1244FCBGA

333S0553 4 DRAM_TYPE:SAMSUNG_2GBSAMSUNG,LVDDR3,1GBIT,7.5X11.0 CRITICALU3100,U3110,U3120,U3130

337S3947 U10001 CRITICALPDC,SLGFN,PRQ,1,6,10W,R0,3M,BGA CPU:1.6GHZ

337S3792 U1000 CPU:1.2GHZ1 CRITICALCDC,QKWH,QS,1,2,10W,800,R0,1M,BGA

IC,MCP89U-A02,24.5MMX24.5MM,1244FCBGA1 U1400 MCP89U:A02CRITICAL337S3868

PDC,SLGAK,PRQ,1,4,10W,R0,3M,BGA CPU:1.4GHZ337S3954 CRITICAL1 U1000

IC,MCP89U-A03,24.5MMX24.5MM,1244FCBGA MCP89U:A03U14001 CRITICAL337S3939

333S0553 SAMSUNG,LVDDR3,1GBIT,7.5X11.0 CRITICAL4 U3400,U3410,U3420,U3430 DRAM_TYPE:SAMSUNG_2GB

MAGLAYERS AS ALTERNATE152S0586 ALL152S0847

IC ASSY,EFI,LOCKED,K99341T0263 CRITICAL1 BOOTROM:LOCKEDU6100

DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GBDDR3:MICRON_2GB

341T0261 U49001 IC ASSY,SMC EXTERNAL,K99 CRITICAL SMC:PROG

ONSEMI AS ALTERNATE377S0066377S0107 ALL

DP_ESD,DP_PWR:SMC,VFRQ:SLPS3,HVDDLDO:FIXED,MCPHVDD:P2V5,MCPPLL_R:REG,S0PGOOD_BJT,ISL6259_SCREENED:YES,DPI2C:SMCK99_MISC

DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:MICRON_4GBDDR3:MICRON_4GB

DRAM_CFG0:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GBDDR3:SAMSUNG_4GB

DRAM_CFG0:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GBDDR3:SAMSUNG_2GB

LPCPLUSK99_DEVEL:PVT

K99_PROGPARTS BOOTROM:UNLOCKED,SMC:PROG

COMMON,ALTERNATE,PROJ:K99,K99_MISC,MCP89U:A03,K99_DEBUG:ENG,K99_PROGPARTS,SPI:41MHZ,LVDDR3:YES,WLAN_PCTL:HW,IPD_5V:S5_INT,IPD_3V3:S5K99_COMMON

DDR3:ELPIDA_2GB DRAM_CFG0:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_2GB

CAPS:SS SS_CAP_2_2UF,SS_CAP_10UF,SS_CAP_1UF,SS_CAP_22UF

CAPS:MU MU_CAP_2_2UF,MU_CAP_10UF,MU_CAP_1UF,MU_CAP_22UF

CAPS:TY TY_CAP_2_2UF,TY_CAP_10UF,TY_CAP_1UF,TY_CAP_22UF

333S0557 MICRON,LVDDR3,2GBIT,9X11.5 CRITICAL DRAM_TYPE:MICRON_4GB4 U3400,U3410,U3420,U3430

U3300,U3310,U3320,U3330333S0566 DRAM_TYPE:ELPIDA_4GBCRITICAL4 ELPIDA,LVDDR3,2GBIT,9X11.5

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7/12/2010: Release 4.3.0 (MAJOR)-

- Page 4: Updated BOM options table with correct EEEEs for Elpida configs- Page 4: Added label table with correct EEEEs for Elpida configs- Page 5: Updated Elpida 2Gb configs with correct APN 333S0566

- Page 74: Deleted IMVP6_CS_P/N & IMVP6_CS_R_P/N nets from the constraints set as the

(2Gb APN is not ready yet- using 2Gb Micron APN as a placeholder)

- Page 97: Changed min neck width of PPBUS_SW_BKL to 0.25mm

05/19/2010: Release 3.3.0 (Major)-- Page 76: Replaced Q7630 & Q7635 with APN 376S0895 (RJK03E0) per Dayu- Page 73: Replaced Q7330 with APN 376S0749 (SIS426) per Dayu- Page 72: Changed R7220 to 41.2K APN 118S0360 to boost 5V, per Dayu- Page 72: Replaced Q7220 & Q7225 with APN 376S0895 (RJK03E0) per Dayu- Page 70: Changed BOM OPTION attribute of U7000 to OMIT_TABLE

- PAGE 19: REMOVED R1955 PULL-UP ON MLB_RAM_CFG1 (INTERNAL PULL-UP)

- PAGE 78: ADDED BYPASS PROPERTIES TO C7895 AND C7896

- PAGE 72: RENAMED =P5VS3_EN_L TO =P5VS3_EN AND =P3V3S5_EN_L TO =P3V3S5_EN

03/05/2010: RELEASE 0.41.0 (MAJOR)-

Revision History 07/07/2010: Release 4.2.0 (MAJOR)-

these would get NOSTUFF’ed

Constraint (TDK)

OMIT_TABLE to NOSTUFF

<rdar://problem/8168390> K99 MLB BOM: Swap 155S0556-> 155S0578, fix 0402

- Page 5: Added DRAM_TYPE:ELPIDA_4GB BOM option to the Module Parts table

- Page 4: Added 12 new BOMs corresponding to Elpida 2GB and 4GB configs- Page 5: Added DDR3:ELPIDA_4GB BOM group

<rdar://problem/8151087> K99 MLB BOM: Add new Elpida 2Gb memory

- Page 4: Updated Label table with correct EEEEs for SU9400 configs- Page 4: Updated SU9400 BOMs with correct EEEEs (Elpida’s still pending)<rdar://problem/8065425> K99 MLB: Add new CPU APN for U1000 - SU9400

- Moved BOM group table on page 4 to page 5 for space limitations<rdar://problem/7993210> K99 MLB: Cosmetic updates

<rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD

- Page 2: Updated CPU block to reflect 1.6GHz<rdar://problem/7993210> K99 MLB: Cosmetic updates05/21/2010: Release 3.4.0 (Major)-

- Page 69: Fixed netname =PP3V3_S3_DBGLEDs (= sign was missing)

- Page 4: Activated PROJ:K99 BOMOPTION to select proper APN for U9701

-Page 90: Added Q9090 isolation FET to support LCD panel power-down per

- PAGE 52: CONNECTED SMC 0 SMBUS INTERFACE TO THE TCON-A CHIP IN THE

- PAGE 108: ADDED SMBUS_SMC_0_S0_SCL/SDA_R CONSTRAINTS SET

- PAGE 78: MOVED P3V3S5_EN_L NET FROM PIN 4 TO PIN 3 (NON-INVERTING) AND

- PAGE 4: ADDED DRAM_CFG0:L TO RAM TABLES NOT CALLING OUT DRAM_CFG0:H, AND

- Page 52: Changed R5250 & R5251 with 2K APN 117S0052 to reduce rise time<rdar://problem/8064296> K99 MLB: Change pull-up values for SMC 0 SMBus for TCON I2C

- Page 5: Added APN 377S0107 as an alternate for APN 377S0066 per GSM/CE- Page 5: Added APN 155S0457 as an alternate for APN 155S0329 per GSM/CE- Page 5: Added APN 376S0926 as an alternate for APN 376S0610 per GSM/CE- Page 5: Added APN 155S0556 as an alternate for APN 155S0367 per GSM/CE- Page 5: Added APN 138S0671 as an alternate for APN 138S0673 per GSM/CE- Page 5: Added APN 107S0139 as an alternate for APN 104S0075 per GSM/CE- Page 5: Added APN 104S0023 as an alternate for APN 104S0018 per GSM/CE<rdar://problem/8065428> K99 MLB: Add alternates per GSM

parts and Alternate parts tables as space was limited- Page 5: Deleted revision history and replaced it with BOM module parts, Programmable<rdar://problem/7993210> K99 MLB: Cosmetic updates

- Page 110: Removed C1200-C1231 from 10uF caps BOM config tableC7360, C7361 and C9480 to these groupsMurata (138S0676) and Taiyo (138S0688). Also assigned C1200-C1231, C4902,

- page 110: Added BOM config table for 22uF caps for three vendors - Samsung (138S0635),- Page 94: Added OMIT_TABLE BOM option to C9480- Page 73: Added OMIT_TABLE BOM option to C7360 & C7361- Page 49: Added OMIT_TABLE BOM option to C4902vendor BOM group- Page 4: Added SS_CAP_22uF, MU_CAP_22uF and TY_CAP_22uF BOM options for corresponding<rdar://problem/8066033> K99 MLB BOM: Change CPU VCORE 0603 bypass caps for acoustics

ELPIDA_2GB BOM option

- Page 4: Added Elpida DRAM to the CFG table- Page 5: Added Elpida 1Gb APN 333S0565 to the BOM module parts table with DRAM_TYPE:

- Page 4: Added DDR3:ELPIDA_2GB BOM group and set appropriate CFG bits<rdar://problem/8065431> K99 MLB: Add new Elpida 1Gb memory APN - 333S0565

- Page 5: Added SU9400 1.4GHz APN 337S33954 to the BOM module parts table- Page 4: Added 18 new EEEs corresponding to new BOMs- Page 4: Added 18 new 639-XXXX BOMS corresponding to 1.4GHz SU9400 CPU<rdar://problem/8065425> K99 MLB: Add new CPU APN for U1000 - SU9400

06/06/2010: Release 4.1.0 (MAJOR)-

- Page 77: Added U7760 and surrounding circuits. BOM table need to replace later

- Page 54: Changed R5471 from 4.53K to 15k for higher PMON pin sink capability

<rdar://problem/7871918> K99 MLB: Investigate larger replacement for LCD backlight fuse


- No changes since last release 3.6.0

- Page 50: Added PLACE_NEAR property on R5022 to ensure no stub in fallback case.

<rdar://problem/7794868> K99 MLB: Change to single USB port power switch

***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below***

<rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V (not POR)- Page 25: Changed BOM table from ISL 353S2986 to MIC5366 353S2988, as Intersil is NOT

<rdar://problem/8027047> K99 MLB BOM: Swap 132s0247 w/132s0257, 138s0621 w/138s0653, 138s0635 w/138s0654- Page 25,26: Swapped 138s0621 w/138s0653 as per GSM- Page 31-34,37,49: Swapped 132s0247 w/132s0257 as per GSM- Page 49,73: Swapped 138s0635 w/138s0654 as per GSM

- Page 75: Changed C7580 to 560pF APN 132S4001 per Intersil FAE

- Page 74: Renamed VSNS nets to VSEN to match page 100 constraints and deleted these

<rdar://problem/7795028> K99 MLB: 5V/3V3 power supply BOM changes per characterization

<rdar://problem/7993210> K99 MLB: Cosmetic updates

convention compliant power net

- Page 4: Replaced label APN 826-4393 with 825-7557

- Page 4: Changed SPI:62Mhz to SPI:41MHZ BOM option

- Proto 1+ OK2FAB Agile Release!!!

- PAGE 19: ADDED 10K R1954 APN 117S0007 PD ON MLB_RAM_CFG0 AS THERE IS NO

6/4/2010: EVT Agile Release 4.0.0 (FAB)-

*** EVT OK2FAB Agile Release ***

- Upcoming changes (Acoustic, Alternates) will be reflected in 4.1 major release, whichwill match Quanta’s deviations for EVT

<rdar://problem/7838450> K99 MLB: WoW / WoL power control architecture change- Page 78: Swapped unused gate to Q7890 and SMC_Adapter_En fet to Q7891.

- This release matches Quanta’s official BOM for EVT build

- Page 4: Deleted 138S0635 from alternate table as it’s been replaced per GSM(see below)

<rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V (not POR)

05/28/2010: Release 3.6.0 (Major)-

to GND and, U7840.4 output to P3V3S5_EN_L

<rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep


it with actual POR APN 138S0673 symbol. Also, deleted it from

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

- PAGE 78: ALIASED =P0V9S5_EN TO CONNECT TO =PP3V3_S5_P0V0S5- PAGE 78: DELETED Q7891 (PINS 3,4,5) SYMBOL AS P5VS3_EN_L IS ACTIVE HIGH

SIGNAL (SO NO NEED TO INVERT) AND RENAMED IT TO P5VS3_EN. ALSO,

RENAMED IT TO P3V3S5_EN AS IT IS ACTIVE HIGH SIGNAL. LEFT PIN 4

<rdar://problem/8033353> K99 MLB: Change to dual USB port power switch

<rdar://problem/7744955> K99 Proto0 Task: Characterize Voltage/Current/Temperature

<rdar://problem/8033256> K99 MLB: Implement 3V3 S5 bleed resistor to satisfy IPD Cumulus

- Page 77: Fixed BOM table attribute to attach BOM option value to TBL_BOMOPTION

from PP3V3_S3_WLAN**** Didn’t sync page 40 as K16 needs to sync it first from K99 to remove neck width** Didn’t sync page 52 as K16 need to sync it first from K99 to remove accelerometer*****Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below***

05/26/2010: Release 3.5.0 (Major)-

- Page 49: Changed port P94 from SMC_DP_HPD_L to PM_SLP_S4_L

- Page 49: Changed port P92 from SMC_BS_ALRT_L to SMC_PME_S4_L

- Page 97: Deleted OMIT_TABLE BOM option attribute from C9797 and replaced

-Page 108: Added constraints for new nets on page90, I2C_TCON_SCL/SDA_CONN

-Page 97: Reversed previous change, U9701 back to 353S2896, handled via a

- Page 97: Swapped pins of R9700 to match original orientation before

3/31/2010: Proto 1+ Release 2.1.0 (MAJOR)

- Page 108: Changed Therm, Sense, Audio line-to-line spacing to 1:1 instead of 2:1<rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements

connected R7899 to pin 3 of Q7890; Q7890.5 gate tied to P3V3S5_EN_L; Q7890.4

- Page 54: For IN1C, change R5412 to 118 Ohms, APN : 114S0127

** Didn’t sync pages 79 & 99 as K16 need to sync it first from K99 to fix OMIT_TABLE

- Page 52: Added notes about I2C addresses on panel, may not be 100% accurate yet

***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16***

- Page 78: Added R7899 0ohm 0603 (will change later) pull-up to =PP3V3_S5_REG and

- Page 76: Cleaned-up page, including correcting application of two PLACE_NEARproperties and changing an OMIT to OMIT_TABLE

<rdar://problem/8036605> K99 MLB BOM: Implement MCP VCORE characterization changes

power sequencing on shutdown

Sensors

- Page 4: Deleted ZS0904 entry from the module parts table as symbol is ready

- PAGE 4: ADDED APN 376S0895 UNDER MODULE PART TABLE FOR Q7220 & Q7225 PER

- PAGE 4: DELETED MODULE TABLE ENTRY FOR ZS0907 AS POR SYMBOL IS READY

- PAGE 78: REPLACED R7813 WITH 0 OHMS APN 117S0002 FOR NOW

POR

353S2986 with 353S2988, making TI its alternate-Page 4: Removed MIC5366 from alternate BOM table as it is primary now and replaced

<rdar://problem/7963570> K99 MLB: Remove SMS circuit from layout

- Page 9: Replaced ZS0904 with actual symbol for APN 870-1940 and deleted OMIT_TABLE

- Page 74: Changed C7451/C7452 to same APN 131S0287 as C7237/C7239 for BOM consolidation

- Page 46: Changed USB port power switch U4690 back to dual port TPS2052B APN 353S2298

_ Page 53: For IZDM, change U5360 to INA210 (APN : 353S2073)

- Page 4: Deleted APN 353S3047 entry from the alternate table

- Page 25: Replaced APN 353S3048 with 353S2986 in the BOM table for U2590 as primary

***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below***** Didn’t sync page 52 as K16 need to sync it first from K99 to remove accelerometer**** Didn’t sync page 25 as K16 need to sync it first from K99 to revert to 2.5 LDO**** Didn’t sync page 40 as K16 needs to sync it first from K99 for above change**

<rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements- Page 24: Changed PPVCORE_SW_MCP_GFX min neck width to 0.12mm for routing

<rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V

<rdar://problem/7851979> K16/K99: Set SPI operating frequency to 42Mhz

<rdar://problem/7986457> K99 MLB: Change LIO Flex connector J4700 to accommodate new LIO- Page 47: Connected pin 38 to GND

<rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V- Page 4: Added APN 353S2988 (MICREL) as an alternate for 353S2986- Page 4: Added APN 353S2987 (TI) as an alternate for 353S2986

- Page 25: Reverted U2590 back to the 2.5 LDO APN 353S2988

for HVDDLDO:FIXED

<rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD- Page 77: Changed IPD_PWR:S5 to IPD_5V:S5_EXT BOM option- Page 77: Changed IPD_PWR:S3 to IPD_5V:S3 BOM option

IPD 5V supply. Added BOM option IPD_5V:S5_INT to R7761


- Page 57: Changed IPD_PWR:S3 to IPD_3V3:S3 BOM option

- Page 78: Removed =USB_TPAD_MUX_EN alias to DDREG_EN as MUX has been removed

- Page 19: Added alias for PM_SLP_S4_L to PM_SLP_S5_L

- Page 49: Changed port P95 from PM_SLP_S4_L to PM_SLP_S5_L

- Page 50: Removed R5095 PU resistor on SMC_PB6

Flex

switcher for IPD 5V supply

- Page 7: Renamed =PP3V3_S3_TPAD to PP3V3_TPAD_CONN and =PP5V_S3_TPAD TO PP5V_TPAD_FILT- Page 8: Added =PP3V3_SMC_PME alias to PP3V3_S5

<rdar://problem/8009884> K99 MLB: Add new CPU APN for U1000- Page 4: Added SU9600 CPU APN 337S3947 1.6GHz to the module part table. And, updated

BOM variant table to call out this new APN

<rdar://problem/8011930> K99 MLB: Remove SIL BOM option as SIL is not POR- Page 4: Removed SIL BOM option from the development BOM

- Page 8: Changed min neck width of PP3V3_S3 to 0.1mm- Page 40: Deleted line/neck width attributes from =PP3V3_S3_WLAN as duplicates

CONNECTED IT TO PM_SLP_S4_L VIA RC NETWORK - R7813 & C7813

- PAGE 4: ADDED MODULE TABLE ENTRY FOR Z0920 MLB STIFFENER: 806-1176

- Page 7: Renamed PP3V3_S0_DPPWR to PP3V3_SW_DPPWR to match page 94 changes, making it

- Page 49: Changed port PB6 from SMC_PB6 to SMC_DP_HPD_L

<rdar://problem/7779132> K99 MLB: Implement deeper sleep S4 state

- Page 57: Renamed pin 10 to PP5V_TPAD_FILT- Page 57: Renamed pins 5 & 6 to USB_TPAD_CONN_P/N as before

- Page 57: Removed U5750, R5751,R5750 and C5750 USB_IPD Debug Mux as it is not needed

- Page 57: Changed IPD_PWR:S5 to IPD_3V3:S5 BOM option

- Page 50: Changed R5076 to a PU to =PP3V3_SMC_PME. And, renamed SMC_BS_ALERT_L toSMC_PME_S4_L

- Page 77: Added place near J5700.10:1.5mm to R7761 to avoid long stub

- Page 77: Added R7761 0 ohm bypass option to use internal LDO of 5V/3.3V switcher for

<rdar://problem/7963570> K99 MLB: Remove SMS circuit from layout

- Page 52: Deleted Accelerometer block from the SMBUS page

<rdar://problem/7993210> K99 MLB: Cosmetic updates- Page 8: Added =PP3V3_S3_DBGLEDS alias to =PP3V3_S3_FET for debug LEDS (like K16)- Page 57: Changed PP3V3_S5_TPAD_CONN to PP3V3_TPAD_CONN

- Page 4: Deleted SMS:NO BOM option as SMS has been removed- Page 50: Deleted BOM option SMS:NO from R5093

<rdar://problem/8007333> K99 MLB: Stuff R7872 to enable output connection of ISL power

- Page 78: Added BOM option S0PGOOD_ISL to R7872

03/30/2010: Release 1.5.0 (MAJOR)-- PAGE 9: ADDED Z0920 (OMIT) APN 998-3068 METAL TAB SYMBOL FOR MDP

- PAGE 39: REMOVED CRITICAL ATTRIBUTE FROM THE BOM TABLE AS IT IS NOT

- PAGE 72: CHANGED R7246 AND R7247 TO 1.69K, 1% APN 118S0134 PER VENDOR

- PAGE 4: UPDATED MICRON 2GB APN 333S0557 IN THE BOM TABLE

- Page 77: Changed R7751 to 2.55K APN 118S0234 & R7752 to 20K APN

- Page 97: Stuff C9799

<rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements- Page 8: Changed min neck width of PP3V3_S3 to 0.1mm- Page 8: Changed min neck width of PP5V3_S3 to 0.2mm

bottom of the page

<rdar://problem/7993210> K99 MLB: Cosmetic updates

- Page 69: Changed BOM OPTION attribute of C6999 to OMIT_TABLE- Page 69: Changed BOM OPTION attribute of U6955 to OMIT_TABLE

Dayu

- Page 14: Swapped BCLK_IN_N/P after library symbol refresh- Page 17: Added CKPLUS_WAIVE properties to VDD_IFPx pins that are legally

- Page 19: Removed PM_SLP_S5_L alias. Other cleanup to make all CRefs

- Page 19: Removed pull-up on MLB_RAM_CFG1 (internal pull-up), changedpull-down to 470 ohms. Added pull-down on MLB_RAM_CFG0, madeboth pull-up and pull-down 10K

- Page 25: Added MCPHVDD LDO, SC-70 version. Added 1uF 0201 input cap and10K pull-up resistor, BOMOPTIONed same as LDO. L2590 retained

grounded on K16

visible

DRIVEN FROM MCP89 0 SMBUS [R5240-R5243 APN 117S0002] PER

IDEA IS TO PULL THIS NET TO S5 RAIL WHEN SMS IN NOT STUFFED,

- NON-FUNCTIONAL PROTO 1 OK2FAB RELEASE!!!


- PAGE 72: ADDED OMIT BOM OPTION TO Q7220 & Q7225 AS SYMBOL IS NOT READY

- Proto 1 Ok2FAB Agile Release!!!

- Page 25: Changed BOM OPTION attribute of C2600 to OMIT_TABLE

- Page 9: Changed BOM OPTION attribute of ZS0904 to OMIT_TABLE

Proto 1

between high & low side FETs, per Dayu

- Page 4: Changed BOM OPTION SPI:25MHz to 62MHz

- Page 52: Changed R5290 & R5291 to 2K APN 118S0174 per RADAR# 7810865

Dayu

- Page 14-20: Changed BOM OPTION attribute of U1400 to OMIT_TABLE- Page 10-11: Changed BOM OPTION attribute of U1000 to OMIT_TABLE

- Page 4: Deleted DPI2C:SMC BOM OPTION as eDP I2C Bus won’t be routed on

- Page 4: Deleted 376S0895 alternate part entry to avoid mixing of vendors

RADAR 7749046

NEEDED

INTERNAL PD ON GPIO 48

OPTION ATTRIBUTE SMS:YES PER RADAR 7765442

APN 117S0103

with MCPHVDD:P3V3 BOMOPTION- Page 25: Added voltage divider for HVDD LDO. OMIT_TABLE’d U2590, added

to PM_SLP_S4_L- Page 49: C4902 changed from 0805 to 0603 to free up some layout space forMCP VCore regulator

including deleting unused alias for SMC_PB3

BOMOPTION of DP_PWR:S0

- Page 53: Removed PP prefix from non-power nets. Added OMIT_TABLE to

C5310 for vendor control- Page 59: Sync’ed with K99 (adds R5924, S3 pull-up on SMS_INT_L), pluslots of cleanup including removing PP prefix from signal net,

are active-high

original net

left indicated as unused. Removed inverter from P5VS3_EN and

Added BYPASS properties to C7895 and C7896. Changed base netfor PM_SLP_S4_DLY_L

- Page 93: Added RC between DP_CA_DET and DDC bypass FETs. Also cleaned uppage, adding offpages, fixed grid issues, made power netsconvention-compliant and added note about DP_CA_DET pull-up /FET Vgs reqirements

- Page 93: Added RC between DP_CA_DET and DDC bypass FETs. Also cleaned up

convention-compliant and added note about DP_CA_DET pull-up /

pins

common-mode chokes and cosmetic changes

report (except for 4 false errors). Other cleanup includingremoving some unnecessary net properties

page, adding offpages, fixed grid issues, made power nets

FET Vgs reqirements

- Page 94: Renamed DP_PWR nets to indicate ’SW’ state instead of ’S0’.

3.3V S5 rail. Cleaned up page including fixing grid issues.

reconnected P3V3S5_EN to be non-inverted. R7813 changed frompull-up to series R (0-ohms). P0V9S5_EN changed to alias to

- Page 4: Updated EEE numbers

between 18 BOMs

added

- Page 72: Changed C7237, C7239 to 100pF, 10% APN 131S0287 per Dayu- Page 97: Replaced U9701 with new improved E00 version APN 353S2967- Page 97: Changed R9704 to 33 ohms APN 117S0080 per Kiran- Page 97: Stuffed C9704 per Kiran

- Page 39: Removed CRITICAL flag from 0-ohm resistor tabletables for fixed (2.5V Intersil) and adjustable (TI) regulators

- Page 49: PB3 changed from SMC_DRAM_S3_PWRDN to SMC_SLPS5_L. P74 changedfrom PM_SLP_S4_L to SMC_DP_HPD_L. P75 changed from PM_SLP_S5_L

- Page 50: Added SMS:NO BOMOPTION to SMS_INT_L pull-up. Other cleanup

- Page 50: Added 2 resistors to control DP_PWR and one to connectDP_EXT_HPD_L to SMC. Updated netname on R5090 and added

- Page 52: Added TCON I2C block and R’s to connect to SMC 0 and MCP 0

buses. Other cosmetic cleanup including grid compliance

correcting BYPASS & PLACE_NEAR properties, correcting offpages,

- Page 76: Value changes to R7641/R7642 and OCP note correction per Dayu

Changed C7288 to match C7218. Removed alias that was serving no- Page 72: Value changes to C7237/C7239/R7216/R7246/R7247/R7256 per Dayu.

etc- Page 72: Changed Q7220 & Q7225 to 376S0895 per Dayu’s request. Fixednetnames on switcher enables, removing _L suffixes since they

purpose and was incorrect since it lacked a MAKE_BASE anyhow

- Page 78: Removed RAM power-down circuit, reconnecting =DDRREG_EN to

- Page 78: Disconnected half of Q7891 from 5V S3 power sequencing, gate

corresponding to this new sub-BOM consisting of common parts

to fix USB short issue

- Page 54: Changed R5418 to 4.53K 0201 APN 118S0384

- Page 72: Changed R7246, R7247 to 1.87K, 1% APN 118S0159 per Dayu

- Page 72: Changed C7236, C7238 to 0.01uF, 10% APN 132S0097 per Dayu- Page 72: Changed R7216, R7256 to 3.16K, 1% APN 118S0289 per Dayu

- Page 54: Changed R5471 to 4.53K 0402 APN 114S0281

- Page 46: Changed BOM attribute OMIT to OMIT_TABLE for C4690 & C4695

CAPS:SS/MU/TY

deleted OMIT

duplicated on page 72

- Page 4: Replaced K99_SS/MU/TY_CAP BOM option with better nomenclature -

- Page 4: Fixed DRAM CFG table - swapped CFG 1 and 0 columns

- Page 4: Pulled new 607-XXXX APN and added K99_CMNPTS BOM option

- Page 4: Replaced K99_COMMON with K99_CMNPTS in the BOM variant table

- Page 4: Removed K99_ prefix from K99_DDR3_ BOM Group- Page 4: Deleted 376S0895 APN module parts table entry as it is already

- Page 4: Deleted module table entry for 806-1176 as actual symbol has been

3/26/2010: Release 1.4.0 (MAJOR)-- Page 4: Added 376S0895 as an alternate for 376S0749 per Dayu- Page 4: Added 138S0681 as an alternate for 138S0638 per GSM- Page 4: Added 138S0676 as an alternate for 138S0635 per GSM- Page 4: Removed alternates that were NA to K99- Page 72: Deleted OMIT_TABLE attribute from Q7220 & Q7225. Also deletedthe BOM table. Plan is to use 376S0895 as alternate instead

03/25/2010: Release 1.3.0 (MAJOR)-

- Page 61: Changed BOM OPTION attribute of U6100 to OMIT_TABLE

- Page 49: Changed BOM OPTION attribute of U4900 to OMIT_TABLE- Page 35-36: Changed BOM OPTION attribute of all caps to OMIT_TABLE- Page 31-34: Changed BOM OPTION attribute of U3100-U3430 to OMIT_TABLE

138S0672 to improve noise immunity & reduce inrush stress, per- Page 69: Changed R6905 to 10 Ohms APN 101S0089 & C6990 to 2.2uF APN

3/31/2010: Proto 1+ Release 2.2.0 (MAJOR)

***Sync’ed from K16***

03/31/2010 - Proto 1 Agile Release 2.0.0 (FAB)

- Page 93: Added CKPLUS_WAIVE properties to _P nets connecting to FET DRAIN

per radar 7761747

table now to support/clarify different values for K16/K99

radar 7761747

5/12/2010: Proto 1+ Agile Release 3.0.0 (FAB)

syncing with K16

Switch input changed from PM_SLP_S3_L to =DP_PWR_EN. HPD_Lnetname changed, offpage added and pull-up changed to DP_PWR.Other cleanup including removing PLACE_NEARs that should behandled via constraints, OMIT_TABLEs for caps, CRITICAL flags on

- Page 108: Added net constraints for diffpairs reported by diffpNoPhysNet

INTERNAL DISPLAY. ALSO, PROVIDED 0 OHMS STUFFING OPTIONS TO BE

- PAGE 50: ADDED BOM OPTION ATTRIBUTE SMS:NO TO R5093 PU ON SMS_INT_L.

- PAGE 4: REMOVED SMS_YES BOM OPTION FROM K99_DEVEL:ENG BOM GROUP. INSTEAD,

RESPECTIVELY PER RADAR 7749046

- PAGE 59: ADDED 10K R5924 PU ON SMS_INT_L TO =PP3V3_S3_SMS WITH BOM

- Page 4: Added APNs 353S2987 & 353S2988 as alternates for 353S2986

<rdar://problem/7964678> K99 MLB BOM: Change MCP APN to A03 version- Page 4: Added MCP89U:A03 BOM table. Changed K99_Common to call out A03

<rdar://problem/7861271> K99 MLB: Set SPI operating frequency to 42MHz

<rdar://problem/7838450> K99 MLB: WoW / WoL power control architecture change- Page 4: Added WLAN_PCTL:HW to K99_Common

<rdar://problem/7953783> K99 IPD power regulator new design- Page 4: Added IPD_PWR:S5 to K99_Common- Page 8: Aliased =PPBUS_5V_S5 to PPBUS_G3H signal

<rdar://problem/7825507> K99 MLB BOM: Change label P/N

<rdar://problem/7749046> K99 MLB: Connect SMBUS to internal display connector

convention compliant power net- Page 7: Renamed PP3V3_LCDVDD_SW_F to PP3V3_SW_LCD to match page 90, making it

- Page 7: Removed SYS_LED_ANODE_R

- Page 8: Added =PP3V3_S5_TPAD to PP3V3_S5 net

- Page 59: Deleted csa page as SMS is no longer POR

<rdar://problem/7993241> K99 MLB: Cleanup of CheckPlus warnings/errors

- Page 9: Renamed stiffener Z0920 to MT0900, similar to K16

- Page 9: Cleaned-up TP/NC _P/_N errors

nets from constraints table on the same page

attribute as mentioned above**

<rdar://problem/7749046> K99 MLB: Connect SMBUS to internal display connector

<rdar://problem/7993210> K99 MLB: Cosmetic updates- Page 13: Changed XDP SMBus nets to =I2C_XDP_* for new aliases on page52- Page 52: Added XDP to MCP_0 SMBus diagram


- Page 46: Corrected Refdes from Q4690 to U4690

<rdar://problem/7993278> K99 MLB: Schematic sync with K16 MLB- Page 26: Sync’ed with K16, OMIT changed to OMIT_TABLE- Page 73: Sync’ed with K16, OMITs changed to OMIT_TABLE and cosmetic clean-up

- Page 10: Added Need_TP=True attribute to pin E37 & D40

<rdar://problem/7871167> K99 MLB: Change RC on CPUVCORE PMON output

- Page 54: Changed C5470 from 0.22UF to 68nF 10%. Only one in the library

- Page 23: Changed Q2300 from 376S0868 to 376S0912

- Page 77: Added min line and neck width properties to PP5V_S5_LDO- Page 78: Aliased =P5V_S5_EN to =P5V3V3_REG_EN- Page 78: Added R7846 and C7846 0ohm 0.47F (NO STUFF) stuffing options

<rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep- Page 57: Added R5730 & R5731 for power switch on PP3V3_TPAD- Page 57: Added U5750 USB Mux- Page 57: Added R5751 (NO STUFF) to bypass U5750 MUX- Page 78: Added =USB_TPAD_MUX_EN to DDRREG_EN

<rdar://problem/7935301> K99 MLB BOM: Change BOM per CE request- Page 39: Added Critical attribute to U3920, U3940- Page 54: Added Critical attribute to Q5401,U5413

5/17/2010: Release 3.1.0 (Major)-

- PAGE 9: REPLACED ZS0907 WITH POR APN 870-1938 AND DELETED OMIT ATTRIBUTE

REMOVED DRAM_CFG1:H AS IT IS NO LONGER NEEDED

- PAGE 78: NO STUFF C7801NC

CONNECTOR

03/05/2010: RELEASE 0.42.0 (MAJOR)-

- PAGE 72: CHANGED C7237 AND C7239 TO 1000PF, 10% APN 132S0122 PER VENDOR


- Page 8: Removed =PP3V3_S5_PWRCTL alias

- Page 9: Tagged POGOS and MT0900 as CRITICAL

- Page 79: Changed OMIT associated with C7980 to OMIT_TABLE

<rdar://problem/7935301> K99 MLB BOM: Change BOM per CE request- Page 75: Added Critical attribute to R7560

- Page 99: Changed OMIT associated with all caps to OMIT_TABLE

- Page 97: Added Critical attribute to R9700

<rdar://problem/7994057> K99 MLB: Need to add Need_TP=True property to CPU

<rdar://problem/7934374> K99 MLB BOM: Replace 376S0868 with 376S0912

- Page 78: Added BOM Options WLAN_PCTL:HW to Q7891 both halves- Page 78: Added R7891 0 ohm 5%- Page 78: Added Bom option WLAN_PCTL:SW to R7891

- Page 77: Added R7760 for switching capability

- Page 57: L5720.2 now connects to PP5V_S5_LDO<rdar://problem/7953783> K99 IPD power regulator new design<rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD

- Page 98: Changed F9800 to 0603 package APN 740S0115

- Page 98: Added Critical attribute toF9800- Page 77: Removed Critical from C7710, C7715

- Page 46: Replaced Q4690 with single port switch APN 353S1930 (Higher DCR)

- Page 9: Replaced Z0920 with POR stiffener symbol for APN 806-1176 and

<rdar://problem/8006037> K99 MLB: Change RC Filter Values on AMON, and BMON- Page 54: Changed R5481 to 150K APN 118S0106 and C5487 to 0.0068uF APN 132S0009- Page 54: Changed R5401 to 300K APN 118S0276 and C5490 to 0.0033uF APN 132S0049

<rdar://problem/7986457> K99 MLB: Change LIO Flex connector J4700 to accommodate new LIO

- Page 47: Replaced J4700 with new POR connector APN 516S0862Flex

- Page 4: Deleted APN 353S2988 entry from the alternate table<rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V

- Page 25: Replaced U2590 with 2.85V LDO APN 353S3048 (MICREL)- Page 4: Replaced APN 353S2987 entry with APN 353S3047 (TI) as an alternate

- Page 25: Replaced APN 353S2986 with 353S3048 in the BOM table too for HVDDLDO:FIXED


<rdar://problem/8004981> K99 MLB: Connect eDP SMBUS interface to SMC SMBUS 0

- Page 57: Connected a new PME signal SMC_PME_S4_L to pin 2

- Page 4: Added BOM option DPI2C:SMC to stuff R5242 & R5243

5/19/2010: Release 3.2.0 (Major)-

- PAGE 9: REPLACED POGO PIN ZS0906 WITH APN 870-1938 PER PD

- PAGE 19: REPLACED R1957 WITH 10K APN 117S0007 TO BE CONSISTENT 118S0175 to improve noise immunity & reduce inrush stress, per

monitor to ALL_SYS_PWRGD

- PAGE 19: CHANGED R1956 PULL-DOWN TO 470 OHMS (STRONGER PD VS 8.5K PU)

- PAGE 78: CHANGED BASE NET FOR PM_SLP_S4_DLY_L PER WILL

03/05/2010: RELEASE 0.43.0 (MAJOR)-- PAGE 2: REPLACED THIS PAGE WITH QUANTA’S UPDATED ONE- PAGE 4: SWITCHED BOM TABLE TO USE SCREENED ISL6259 PART

- PAGE 4: MOVED SMS_YES BOM OPTION FROM K99_MISC TO DEVEL_BOM

- PAGE 9: FIXED MCPCOREISNS SIGNALS ALIASES PER WILL’S CHANGES ON K16

- PAGE 70: NO STUFF Q7080, D7005,Q7055 AND F7040 FOR NON-FUNCTIONAL BOARD

- PAGE 76: CHANGED OCP TEXT NOTE PAR VENDOR

- PAGE 78: ADDED NC SYMBOL TO PIN 5 OF U7896

03/07/2010: PROTO1 NON-FUNCTIONAL AGILE RELEASE 1.0.0 (FAB)-

3/19/2010: RELEASE 1.1.0 (MAJOR)-

ADDED SMS:NO TO K99_MISC [ALSO SEE BELOW CHANGES FOR PAGES 50,59]

ELSE PU TO S3 RAIL (PAGE 59) PER RADAR 7765442

- PAGE 59: REPLACED BOM OPTION SMS_YES WITH SMS:YES

- PAGE 70: STUFF BACK Q7080, D7005,Q7055 AND F7040

to OMIT_TABLEs and performed other cleanup- Page 12: Fixed invisible pins on CPU bypass caps. Also changed all OMITs

release. Below list depicts all the changes since 3/1 K16 release **Please NOTE that some of the below changes were already part of 1.1***Sync’ed ALL but pages 1-9,28,47,69,70,74,75 and 97 from K16***

- Page 90: After syncing, renamed PP3V3_S5_LCD to PP3V3_S0_LCD- Page 12: After syncing from K16, deleted C1273 as it NA to K99- Page 7: Added =I2_TCON_SCL/SDA FCTs under INT DP FUNC_TEST group- Page 8: Moved PP3V3_S0_LCD & PP3V3_S5_DP_PORT_PWR to S5 rail

- Text sizes have been fixed - safe to sync03/24/2010: Release 1.2.0 (MAJOR)-

RADAR 7742010- PAGE 93: ADDED 3300PF APN 132S0241 C9302 CAP ON DP_CA_DET TO GND PER

- PAGE 90: ROUTED NEWLY ADDED =I2C_TCON_SDA/SCL TO PINS 1 & 30 OF J9000- PAGE 75: REPLACED L7560 WITH 10X10X3MM APN 152S1236 PER RADAR 7769386

- Page 8: Renamed PP3V3_S5_LCD to PP3V3_S0_LCD

syncing from K16- Page 97: Changed BOM OPTION attribute of C9797 to OMIT_TABLE after

DAYU FOR PART SUPPLY ISSUE


BOM table as it is no longer required - Fixed typo in APN (first column)<rdar://problem/7825507> K99 MLB BOM: Change label P/N

<rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements

<rdar://problem/8151087> K99 MLB BOM: Add new Elpida 2Gb memory

- Page 90: Changed FL9000, FL9001 from 155S0423 to 155S0559

- Page 9: Deleted CRITICAL attribute from MT0900 and NOSTUFF’ed it<rdar://problem/8180364> K99 MLB BOM: Remove 806-1176 stiffener

- Page 4: Added IPD_3V3:S5 BOM option under K99_COMMON to select 3.3V S5 power supply<rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep

- Page 4: Changed IPD_PWR:S5 to IPD_5V:S5_INT BOM option to use internal LDO of 5V/3.3V

- Page 110: Removed caps listed above on page 12 from the BOM table as

- Page 94: Changed FL9400-FL9403 from 155S0423 to 155S0559

***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16***

C1219, C1220,C1221,C1222,C1224,C1225,C1228,C1229,C1231 fromC1205,C1206,C1207,C1208,C1209,C1211,C1212,C1213,C1215,C1216,

- Page 12: Changed BOM option attribute of C1200,C1201,C1202,C1203,C1204,<rdar://problem/8151651> K99 MLB BOM: Reduce CPU VCORE 0603 bypass caps

alternate parts- Page 5: Changed 155S0556 to 155S0578 to address the 0603 0402 mismatchpad with 0603

<rdar://problem/8007524> K99 MLB: Stuff C9799 to provide better phase margin

- Page 69: Renamed PP3V3_S3 going to debug LEDs to =PP3V3_S3_DBGLEDS

<rdar://problem/8151651> K99 MLB BOM: Reduce CPU VCORE 0603 bypass caps

<rdar://problem/8118512> K99 MLB BOM: Swap 155S0423 -> 155S0559, Supply

<rdar://problem/8175202> K99 MLB: Move MCP Temp Sensor to SMC B SMBUS- Page 52: Move MCP TEMP I2C connections to SMC B Bus- Page 52: NOSTUFF’ed R5250 & R5251- Page 52: Changed MCP TEMP I2C address note to reflect 0XD8/0XD9- Page 55: Changed R5536 to 15K APN 118S0105 to set ADDR = 0XD8/0XD9.

Updated schematic note too for address

<rdar://problem/8141673> K99 MLB: Change eDP connector J9000 pinout- Page 90: Changed pine 2 to NC and connected pin 4 to PPVOUT_SW_LCDBKLT

<rdar://problem/8224515> K99 MLB: Remove Q9090 isolation FET- Page 90: Removed Q9090 FET and directly connected TCON I2C bus J9000- Page 90: Deleted =I2C_TCON_SCL/SDA_CONN net names and kept

=I2C_TCON_SCL/SDA

<rdar://problem/8224857> K99 MLB: Replace APN 155S0559 with 155S0423

- Page 90: Changed FL9000 and FL9001 back to the original APN 155S0423(incompatible pad sizes)

- Page 94: Changed FL9400-FL9403back to the original APN 155S0423

<rdar://problem/8224921> K99 MLB: Change R9714 (BKLT_ISET) resistor to18.2K 1% APN 118S0155

- Page 97: Change R9714 to 18.2K 1% APN 118S0155

<rdar://problem/7993210> K99 MLB: Cosmetic updates- Page 97: Fixed schematic note - I_LED=369/Riset

7/22/2010: Release 4.4.0 (MAJOR)-


Revision History

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Apple Inc.

PAGE


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B

C

345678

D

B

8 7 5 4 2 1

(NEED TO ADD 5 GND TP)


SPEAKER FUNC_TEST



Fan Connectors



AIRPORT / BT

DEBUG VOLTAGE

FSB SIGNALS WITH NOTEST

(NEED 2 TP)

(NEED 2 TP)

(NEED 6 TP)

LIO CONNECTOR

(NEED TO ADD 4 GND TP NEAR J6950 AND 1 FOR SHIELD)

(NEED 4 TP)

(NEED 2 TP)

DC POWER CONN

Functional Test Points

LCP + SPI CONN

(NEED 5 TP)

BATT POWER CONN

SATA HDD


(NEED 6 TP)


HALL EFFECT CONN (PLACEHOLDER)

INT DP FUNC_TEST


IPD_FLEX_CONN

I12

I15

I16

I228

I230

I246

I247

I248

I249

I251

I252

I253

I254

I255

I256

I257

I259

I260

I261

I305

I313

I314

I315

I317

I318

I319

I320

I321

I322

I455

I456

I479

I480

I488

I489

SYNC_MASTER=K6_MLB

FUNCTIONAL TESTSYNC_DATE=12/11/2009

=PP5V_S3_LIO_CONNTRUE

TRUE PP5V_S3

TRUE =PP3V3_S3_BT

PP5V_TPAD_FILTTRUE

TRUE PP3V3_S3

TRUE FAN_RT_PWMTRUE PP5V_S0

FAN_RT_TACHTRUE

SMC_TPAD_RST_LTRUE

SMC_PM_G2_ENTRUE

PM_SLP_S4_LTRUE

PP0V9_ENETTRUE

PM_SLP_S3_LTRUE

PPVOUT_SW_LCDBKLTTRUE

TRUE PPBUS_G3H

PP3V3_S5TRUE

PP3V42_G3HTRUE

TRUE PP5V_S0PP3V3_S0TRUE

TRUE PPVCORE_S0_CPUPPVCORE_S0_MCPTRUE

PP1V05_S0TRUE

PP1V5_S0TRUE

PPBUS_G3H_ISNSTRUE

PP5V_S3_RTUSB_A_FTRUE

PP3V3_SW_DPPWRTRUE

PP3V3_ENETTRUE

TRUE PP3V3_S0_HDD_RPP3V3_WLAN_FTRUE

PP0V9_S5TRUE

SMC_TDITRUE

LPC_PWRDWN_LTRUE

TRUE AUD_I2C_INT_L

LPC_SERIRQTRUE

TRUE SMC_BC_ACOKTRUE =PP3V42_G3H_ONEWIRE

TRUE SMC_LID_R

TRUE PCIE_AP_D2R_P

SMC_TCKTRUE

LPCPLUS_GPIOTRUE

AP_CLKREQ_Q_LTRUE

AP_RESET_CONN_LTRUE

PCIE_WAKE_LTRUE

USB_TPAD_CONN_NTRUE

TRUE =I2C_TPAD_SCL

TRUE PCIE_CLK100M_AP_P

TRUE USB_BT_P

TRUE PCIE_AP_D2R_N

TRUE SMBUS_SMC_BSA_SDA

USB_CAMERA_PTRUE

SATA_HDD_R2D_NTRUE

TRUE SMC_HDD_OOB_TEMPSATA_HDD_D2R_C_NTRUE

TRUE SATA_HDD_D2R_C_P

NO_TEST=TRUE FSB_ADS_LNO_TEST=TRUE FSB_ADSTB_L<1..0>NO_TEST=TRUE FSB_D_L<63..0>

NO_TEST=TRUE FSB_DSTB_L_P<3..0>

FSB_LOCK_LNO_TEST=TRUE

FSB_HITM_LNO_TEST=TRUE

NO_TEST=TRUE FSB_REQ_L<4..0>

TRUE =PP3V3_S5_LPCPLUS

PM_CLKRUN_LTRUE

SMC_TMSTRUE

LPCPLUS_RESET_LTRUE

SMC_TRST_LTRUE

LPC_CLK33M_LPCPLUSTRUE

SPI_ALT_CLKTRUE

SPI_ALT_CS_LTRUE

SMC_TX_LTRUE

SYS_DETECT_LTRUE

PPVBAT_G3H_CONNTRUE

TRUE SMBUS_SMC_BSA_SCL

TRUE SPKRAMP_INR_N

USB_EXTD_PTRUE

USB_EXTD_OC_LTRUE

TRUE =PP3V3_S0_AUDIO

TRUE DP_INT_AUX_CH_C_N

NO_TEST=TRUE FSB_DSTB_L_N<3..0>

FSB_HIT_LNO_TEST=TRUE

NO_TEST=TRUE FSB_DINV_L<3..0>

FSB_A_L<35..3>NO_TEST=TRUE

=I2C_LIO_SCLTRUE

TRUE SPIROM_USE_MLBTRUE =I2C_MIKEY_SDA

PCIE_AP_R2D_PTRUE

TRUE PCIE_CLK100M_AP_N

DP_INT_HPD_CONNTRUE

TRUE PCIE_AP_R2D_N

TRUE HDA_BIT_CLK

TRUE SPI_ALT_MISO=USB_PWR_ENTRUE

=I2C_LIO_SDATRUE

TRUE =I2C_MIKEY_SCL

TRUE SPKRAMP_INR_PTRUE AUD_IP_PERIPHERAL_DET

TRUE PP3V3_WLAN_F

TRUE WIFI_EVENT_LTRUE USB_BT_N

TRUE LED_RETURN_1

TRUE PP3V3_S0_HDD_R

SMC_HDD_TEMP_CTLTRUE

SATA_HDD_R2D_PTRUE

TRUE SYS_ONEWIRE

TRUE =PP1V8R1V5_S0_AUDIO

TRUE HDA_SDIN0SMC_RESET_LTRUE

TRUE SMC_NMISMC_RX_LTRUE

TRUE SMC_MD1

SMC_TDOTRUE

TRUE LPC_FRAME_L

TRUE SPI_ALT_MOSILPC_AD<3..0>TRUE

TRUE =PP5V_S0_LPCPLUS

AUD_GPIO_3TRUE

USB_EXTD_NTRUE

USB_CAMERA_NTRUE

TRUE =PP18V5_DCIN_CONN

PP1V05_S0_MCP_PLL_UFTRUE

PP1V5R1V35_S3TRUE

PP3V3_SW_LCDTRUE

PPDCIN_S5_S5TRUE

TRUE SPKRAMP_R_N_OUTTRUE SPKRAMP_R_P_OUT

PPVOUT_SW_LCDBKLTTRUE

PP3V3_SW_LCDTRUE

TRUE LED_RETURN_5

TRUE =PP3V42_G3H_HALL

TRUE =I2C_TCON_SCLTRUE LED_RETURN_6

TRUE =I2C_TCON_SDA

TRUE HDA_SDOUT

HDA_SYNCTRUE

TRUE HDA_RST_LTRUE AUD_IPHS_SWITCH_EN

LED_RETURN_4TRUE

TRUE LED_RETURN_3TRUE LED_RETURN_2

TRUE DP_INT_AUX_CH_C_P

TRUE DP_INT_ML_F_P<1>DP_INT_ML_F_N<1>TRUE

TRUE DP_INT_ML_F_P<0>DP_INT_ML_F_N<0>TRUE

USB_TPAD_CONN_PTRUE

PP3V3_TPAD_CONNTRUE

=PP3V42_G3H_TPADTRUE

=I2C_TPAD_SDATRUE

SMC_ONOFF_LTRUE

SMC_LIDTRUE

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8 49

8

8 34

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8

45

7 8 57

45

39 46

38 57

19 38 57

8

19 38 39 57

7 42 59 62

8 42 49

8 57 71

8

7 8 57

8 57 71

8 42

8 42

8 57

8 57 71

8

36

61

8

7 35

7 34 39

8

38 39 40

19 38 40

19 37

19 38 40

9 37 38 39

8 37

49

16 34 67

38 39 40

19 40

34

34

16 34

46 71

41 46

16 34 67

18 34 68

16 34 67

41 70

18 37 68

35 67

35 38

35 67

35 67

10 14 65

10 14 65

10 14 65

10 14 65

10 14 65

10 14 65

10 14 65

8 40

19 38 40

38 39 40

25 40

38 40

25 40 68

40 68

40 68

36 38 39 40

49

49 50

41 70

37 48 71

18 37 68

18 37

8 37

59 71

10 14 65

10 14 65

10 14 65

10 14 65

37 41

19 40 47

37 41

34 67

16 34 67

59

34 67

19 37 68

40 68 36 37 57

37 41

37 41

37 48 71

17 37

7 34 39

34 38 39

18 34 68

59 62

7 35

35 38

35 67

37 38

8 37

19 37 68

38 39 40 50

38 40

36 38 39 40

38 40

38 39 40

19 38 40 68

40 68

19 38 40 68

8 40

37 48

18 37 68

18 37 68

8 49

8

8 71

7 59

8

48 49

48 49

7 42 59 62

7 59

59 62

8 49

41 59

59 62

41 59

19 37 68

19 37 68

19 37 68

19 37

59 62

59 62

59 62

59 71

59 71

59 71

59 71

59 71

46 71

46

8 46

41 46

38 39 46

38 39 46 49




36

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REVISION

DRAWING NUMBER SIZE

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SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

11.30 A

LVDDR (1.5V/1.35V) Rails

3.30 A

(MCP VCORE AFTER SENSE RES)

9.40 A

"S0,S0M" RAILS

0.100 A

5.40 A

400mA

300mA

(OR 1.35V)

0 mA

4250 mA

0.064 18 A

LVDDR VRef/VTT (0.75V/0.675V) Rails

1.20 A

23.8 A

.210 A

"G3H" RAILS"S3" RAILS

"ENET" RAILS

~100mA

1.274 A

"S5" RAILS

105 mA/241 mA

0.290 A

1.07 A + S3 + S0


Power Aliases

=PP5V_S3_AUDIO_AMP=PP5V_S3_DDRREG

=PP5V_S3_LIO_CONN

=PP5V_S3_MCPDDRFET

=PP5V_S3_P5VS0FET

=PP5V_S3_REG

=PP5V_S3_RTUSB

=PP5V_S3_SYSLED=PP5V_S3_TPAD

MIN_NECK_WIDTH=0.25 mmVOLTAGE=5V

MIN_LINE_WIDTH=0.5 mmPP5V_S3

MAKE_BASE=TRUE

=PP3V3_ENET_MCP_RMGTMAKE_BASE=TRUE

PP3V3_ENETMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

=PPVCORE_S0_MCPGFXFET=PPVCORE_S0_MCP

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

PP3V3_S5

MAKE_BASE=TRUEVOLTAGE=3.3V

=PP3V3_SMC_PME=PP3V3_S0_LCD

=PP0V9_ENET_P0V9ENETFET

=PP0V9_S5_REG

=PP0V9_S5_MCP_VDD_AUXC

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm


PP0V9_S5

=PP3V3_S5_MCP

=PP3V3_S5_DP_PORT_PWR=PP3V3_S5_TPAD

=PP3V3_S5_REG

=PP3V3_S0_SMC

=PP3V3_S0_MCP_PLL_UF=PP3V3_S0_MCP_GPIO

=PP3V3_S0_FAN

=PP1V5_S0_CPUMAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V5_S0MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.5V

MAKE_BASE=TRUE

PPDDRVTT_S0MIN_NECK_WIDTH=0.2 mmVOLTAGE=0.75V

MIN_LINE_WIDTH=0.4 MM

=PP3V3_S3_TPAD=PP3V3_S3_WLAN

=PP3V3_S3_1V5S3ISNS

=PP3V3_S3_DBGLEDS

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_SMS

=PPBUS_G3H_R_OUT

=PP5V_S0_CPU_IMVP

=PP5V_S0_LPCPLUS

MIN_NECK_WIDTH=0.20mmMIN_LINE_WIDTH=1mmPPDCIN_S5_S5

VOLTAGE=18.5VMAKE_BASE=TRUE=PPDCIN_S5_CHGR

=PPVIN_S0_MCPCORE=PPVIN_S3_DDRREG

=PPBUS_5V_S5=PPBUS_G3H_R_IN

=PPBUS_S0_LCDBKLT

=PP5VR3V3_S0_DPCADET

MIN_NECK_WIDTH=0.2 MMVOLTAGE=5V

PP5V_S0

MAKE_BASE=TRUE


=PP3V3_S0_FET

=PPVIN_S5_P5VP3V3

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP1V05_S0MIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

=PP1V05_SW_MCP_FSB

=PP3V3_S0_BKLTISNS

=PP3V3_S0_DPCONN

=PP5V_S0_CPUVTTS0=PP5V_S0_BKL

=PP3V3_S0_P1V5S0

=PP5V_S0_MCPREG

=PP5V_S0_FET

=PP3V3_S0_MCPDDRISNS

=PP3V3_S0_MCP_PLL_VLDO

=PP3V3_S0_PWRCTL

=PP3V42_G3H_CHGR

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_PLL_OR

=PP1V8R1V5_S0_AUDIO

=PP1V5_S0_REG


=PPVTT_S3_DDR_BUF PPDDRVREF_S3MIN_NECK_WIDTH=0.2 mm



=PPVTT_S0_DDR_LDO

=PPDDRVTT_S0_MEM_A

=PPMCPCORE_S0_REG

=PP1V05_S0_MCP_SATA_DVDD=PP1V05_S0_MCP_PLL_UF_R

=PPCPUVTT_S0_REG

=PPVCORE_S0_CPU

PP1V05_S0_MCP_PLL_UFMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05VMAKE_BASE=TRUE

PPVCORE_S0_MCP


MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPUMIN_NECK_WIDTH=0.25 MM



=PP3V42_G3H_PWRCTL

=PP3V42_G3H_HALL=PP3V3_S5_SMC

=PP3V42_G3H_SMCUSBMUX

=PP3V3_ENET_FET_R

=PP1V5R1V35_S0_MCPDDRFET

=PPDDR_S3_REG=PP3V42_G3H_REG

=PP3V3_S0_DEBUGROM

=PP3V3_S0_SMBUS_MCP_0=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_IMVP

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_AUDIO

=PP3V3_S0_MCPTHMSNS

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_ENET_MCP_PLL_MAC

=PP3V3_S0_MCPCOREISNS

=PP3V3_S5_ROM

=PP3V3_S5_P3V3S3FET=PP3V3_S5_P3V3S0FET=PP3V3_S5_P3V3ENETFET

=PP0V9_ENET_FET

=PP0V9_ENET_MCP_RMGTMAKE_BASE=TRUEVOLTAGE=0.9VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmPP0V9_ENET

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_XDP=PP3V3_S0_MCP

=PPLVDDR_S3_MEM_B

=PP3V42_G3H_TPAD

=PP3V42_G3H_SMBUS_SMC_BSA=PPVIN_S5_SMCVREF

=PP3V42_G3H_ONEWIRE

PP3V42_G3HMIN_LINE_WIDTH=0.6 MM


MIN_NECK_WIDTH=0.2 MM

PP3V3_G3_RTC

=PP3V42_G3H_BMON_ISNS=PP3V3_S5_LPCPLUS

=PP5V_S0_FAN

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S5_SMBUS_SMC_MGMT

=PP1V05_S0_CPU

=PP1V05_S0_MCP_M2CLK_DLL=PP18V5_DCIN_CONN


PPBUS_G3H_ISNS



=PPVIN_S0_CPUVTTS0=PPVIN_S5_CPU_IMVP

MAKE_BASE=TRUE

PPBUS_G3HMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.4 mm

VOLTAGE=8.4V

=PP3V3_S0_CSREGISNS=PP3V3_S0_BKL_VDDIO

=PP3V3_S5_MCPPWRGD

=PP3V3_S5_P0V9ENETFET

=PP3V3_S5_VMON=PP3V3_S5_P0V9S5

=PP3V3_S5_MCP_GPIO

=PP1V05_S0_MCP_DP0_VDD

=PP1V05_S0_MCP_AVDD_UF

=PP5V_S0_MCPFSBFET

=PPDDRVTT_S0_MEM_B

=PP1V05_S0_XDP

=PP1V05_S0_MCP_PE_DVDD

=PPVCORE_S0_CPU_REG

=PPLVDDR_S3_MEM_A

=PPVIN_S0_DDRREG_LDO

=PP1V5R1V35_S3_MCP_MEM

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.5V

PP1V5R1V35_S3

MAKE_BASE=TRUE

=PP3V3_S3_MCP_GPIO=PP3V3_S3_VREFMRGN=PP3V3_S3_PDCISENS

=PP3V3_S3_FET

=PPBUS_G3H

=PP3V3_S3_WLANISNS

=PP1V05_S0_MCP_FSB

MAKE_BASE=TRUE


PP3V3_S0

=PP3V3_S0_HDDISNS

=PP3V3_S0_HDD

=PP3V3_S0_MCP_HVDD

=PP3V3_S3_BT


PP3V3_S3

MAKE_BASE=TRUE

8 OF 110

4.4.0

051-8379

8 OF 73

48

52

7 49

21

58

51

36

39

56

7

18 20 23

7

22

20 23

7 57 71

39

59

58

56

20 23

7

20 23

61

46

51 57

39

23

17 18 19

45

11 12

7 57 71

46

34

42

49

41

43

53

7 40

7

50

54

52

56

43

63

61

7 57

58

51

7 57

20 23

42

61

55

62

56

54

58

43

56

57

50 57

23

56

7 37

56

56

33 52

52

32

54

20 23

56

55

11 12 64

7

7 42

7 42

57

7 49

38 39

36

9

21

52 49

40

41

41

53

44

7 37

44

19 23

23

43

47

58

58

58

58

20 23

7

41

13

20 23

28 29 31

7 46

41

39

7 37

7

19 20 23

43

7 40

45

41

41

10 11 12

15 23 7 49

7

55

53

7 42 49

43

62

25

58

57

56 57

18 19

17 24

23

22

32

13

20 23

53

26 27 30

52

15

7 71

19

33

52

58

50

42

14 20 23

7 57 71

42

35

20 23

7 34

7

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUTIN

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MDP CONN METAL TAB

EMI IO POGO PINS

UNUSED USB PORTS

USB ALIASES

HEAT SINK MOUNTING BOSSES

FAN BOSS

CHARGER SIGNAL

MCPCOREISNS SIGNAL

SSD BOSS

BSEL<2..0> FSB MHZ

333

266

200133

(RSVD)

100(400)

(166)

1 1 1

0 1 1

0 1 0

1 0 01 0 11 1 0

0 0 00 0 1

CPU ALIASES

MCP89 ALIASES

X16 BOSS

LVDS ALIASES

DISPLAY PORT ALIASES

UNUSED SATA ODD SIGNALS

ETHERNET ALIASES

SATA ALIASES

UNUSED GPU LANES

PCI-E ALIASES

18 69

18 69

18 69

18 69

18 69

18 69

18 69

18

2

1R0981

1/20W5%

201MF

10K

2

1R098010K

1/20W5%

201MF

7 37 38 39 50

21

R0911

MF-LF1/16W5%

402

0

PLACE_NEAR=U7980.A1:5MM

8

18

2

1R098210K

201

1/20W5%

MF

2

1R098410K

1/20W5%

201MF

2

1R0983

1/20W5%

201

10K

MF 2

1R098510K1/20W5%

201MF

1

ZS0905CRITICAL

1.4DIA-SHORT-SILVER-K99SM

1

ZS0906POGO-2.0OD-3.6H-K86-K87

CRITICAL

SM

1

ZS0907POGO-2.0OD-3.6H-K86-K87

CRITICAL

SM

1

Z0906STDOFF-4.5OD1.8H-SM

1


1


1


1


1


1


1


1


1


1


1

MT0900SM-SP

STIFFENER-K16-K99

NOSTUFF

1

ZS0904SM

POGO-2.0OD-2.95H-K86-K87

CRITICAL


SIGNAL ALIAS

MIN_NECK_WIDTH=0.20MM

GNDVOLTAGE=0V

MIN_LINE_WIDTH=0.50MM

MAKE_BASE=TRUEENET_RXD_PD

=PP3V3_ENET_FET_R

ENET_ENERGY_DET

NC_ENET_CLKREQ_LMAKE_BASE=TRUENO_TEST=TRUE

NC_PEG_D2RP<5:4>NO_TEST=TRUE MAKE_BASE=TRUE

NC_PEG_R2DCP<5:4>NO_TEST=TRUE MAKE_BASE=TRUE

NC_PEG_D2RN<5:4>NO_TEST=TRUE MAKE_BASE=TRUE

NC_PEG_CLKREQ_LNO_TEST=TRUE MAKE_BASE=TRUE

DP_AUX_CH_C_P

DP_INT_ML_P<1:0>MAKE_BASE=TRUEDP_IG_ML1_N<1:0>

DP_IG_AUX_CH1_P

ENET_RXD<2>

NO_TEST=TRUENC_USB_MINIPMAKE_BASE=TRUE

NO_TEST=TRUENC_USB_SDCARDNMAKE_BASE=TRUE

=PP3V3_ENET_FET

MAKE_BASE=TRUETP_LVDS_DDC_DATA

TP_DP_INT_MLN<3:2>MAKE_BASE=TRUE

MCP_MEM_VDD_SEL_1V5 TP_MEM_VDD_SEL_1V5 MAKE_BASE=TRUE

TP_MCP_RGB_DAC_VREF

TP_MEM_A_CLKN<1>MAKE_BASE=TRUETP_MEM_B_CLKP<1> MAKE_BASE=TRUE

TP_MEM_B_CLKN<1> MAKE_BASE=TRUEMEM_B_CLK_N<1>

MEM_B_CLK_P<1>

NC_LVDS_IG_B_CLKNMAKE_BASE=TRUENO_TEST=TRUE

SATA_ODD_D2R_N

MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM


PP3V3_ENET_FET

MCP_RGMII_VREF

ENET_CLK125M_RXCLK

ENET_RXD<3>

ENET_RXD<1>ENET_RXD<0>

NC_SATA_ODD_D2RNMAKE_BASE=TRUENO_TEST=TRUE

SATA_ODD_R2D_P NC_SATA_ODD_R2DPMAKE_BASE=TRUENO_TEST=TRUE

SATA_ODD_D2R_P NC_SATA_ODD_D2RPMAKE_BASE=TRUENO_TEST=TRUE

SATA_ODD_R2D_N NC_SATA_ODD_R2DNMAKE_BASE=TRUENO_TEST=TRUE

SATA_ODD_R2D_C_P NC_SATA_ODD_R2DCPMAKE_BASE=TRUENO_TEST=TRUE

SATA_ODD_R2D_C_N NC_SATA_ODD_R2DCNMAKE_BASE=TRUENO_TEST=TRUE

DP_IG_ML1_P<3:2> TP_DP_INT_MLP<3:2>MAKE_BASE=TRUEDP_IG_ML1_N<3:2>

DP_IG_HPD1MAKE_BASE=TRUE

DP_INT_HPD

DP_IG_AUX_CH1_N DP_INT_AUX_CH_NMAKE_BASE=TRUE

DP_INT_AUX_CH_PMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_INT_ML_N<1:0>

DP_IG_ML1_P<1:0>

DP_CA_DET

DP_AUX_CH_C_NMAKE_BASE=TRUE

DP_EXT_AUX_CH_C_NDP_IG_AUX_CH0_NDP_IG_AUX_CH0_P DP_EXT_AUX_CH_P

MAKE_BASE=TRUE

DP_IG_HPD0MAKE_BASE=TRUE

DP_EXT_HPD

DP_IG_ML0_P<0..3> DP_EXT_ML_P<0..3>MAKE_BASE=TRUE

MAKE_BASE=TRUETP_LVDS_DDC_CLK

MAKE_BASE=TRUELCD_BKLT_EN MAKE_BASE=TRUELCD_IG_PWR_EN MAKE_BASE=TRUELCD_BKLT_PWM

=MCP_IFPB_TXD_N<0..3>=MCP_IFPB_TXD_P<0..3> NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUENO_TEST=TRUE

NC_LVDS_IG_B_CLKPMAKE_BASE=TRUENO_TEST=TRUE

=MCP_IFPA_TXD_P<0..3> NC_LVDS_IG_A_DATAP<0..3>MAKE_BASE=TRUE

NO_TEST=TRUE

=MCP_IFPA_TXD_N<0..3>MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<0..3> NO_TEST=TRUE

=MCP_IFPA_TXC_P NC_LVDS_IG_A_CLKPMAKE_BASE=TRUE

NO_TEST=TRUE

USB_EXTC_N

USB_MINI_N NO_TEST=TRUENC_USB_MININMAKE_BASE=TRUE

NO_TEST=TRUENC_USB_SDCARDPMAKE_BASE=TRUE

TP_MEM_B_A<15> MAKE_BASE=TRUE

MEM_A_A<15> TP_MEM_A_A<15> MAKE_BASE=TRUE

MEM_A_CLK_P<1> TP_MEM_A_CLKP<1> MAKE_BASE=TRUE

MAKE_BASE=TRUETP_CPU_PECI_MCP

MAKE_BASE=TRUECPU_BSEL<0:2> =MCP_BSEL<0:2>

SMC_BC_ACOKMAKE_BASE=TRUE

=MCP_IFPA_TXC_N

NO_TEST=TRUEMAKE_BASE=TRUE

NC_USB_EXTCN

NC_LVDS_IG_B_DATAN<0..3>MAKE_BASE=TRUENO_TEST=TRUE MEM_A_CLK_N<1>

NC_LVDS_IG_A_CLKNMAKE_BASE=TRUE

NO_TEST=TRUE

DP_IG_ML0_N<0..3>

ENET_RXCLK_PDMAKE_BASE=TRUE

ENET_MDIO

MAKE_BASE=TRUEMCPCORES0_VO =MCPCOREISNS_N

MAKE_BASE=TRUE

MCPCORES0_ISP_R =MCPCOREISNS_P

=CHGR_ACOK

USB_EXTC_PMAKE_BASE=TRUE

NO_TEST=TRUENC_USB_EXTCP

=MCP_IFPAB_DDC_CLK

LCD_IG_BKLT_EN

=PEG_R2D_C_P<5:4>

=PEG_R2D_C_N<5:4>

USB_MINI_PUSB_SDCARD_NUSB_SDCARD_P

=PEG_D2R_P<5:4>

=PEG_D2R_N<5:4>

ENET_CLKREQ_L

PEG_CLKREQ_L

PEG_CLK100M_P

PEG_CLK100M_N

=MCP_IFPAB_DDC_DATA

LCD_IG_PWR_ENLCD_IG_BKLT_PWM

=MCP_IFPB_TXC_N=MCP_IFPB_TXC_P

NC_PEG_CLK100MPMAKE_BASE=TRUENO_TEST=TRUE

NC_PEG_CLK100MNNO_TEST=TRUE MAKE_BASE=TRUE

NC_PEG_R2DCN<5:4>NO_TEST=TRUE MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREF NO_TEST=TRUEMAKE_BASE=TRUE

CPU_PECI_MCP

MEM_B_A<15>

DP_EXT_ML_N<0..3>MAKE_BASE=TRUE

MAKE_BASE=TRUEDP_EXT_AUX_CH_N

DP_EXT_AUX_CH_C_PMAKE_BASE=TRUEDP_EXT_CA_DETMAKE_BASE=TRUE

ENET_RX_CTRL

9 OF 110

4.4.0

051-8379

9 OF 73

60

59 71

17 67

17 67

58

19

17

15 66

15 66

18 67

67

18 67

67

18 67

18 67

17

17

17 59

17 67 59 71

59 71

59 71

17 67

60

60 61 71

17 67

17 67 60

17 61

17 67 61 71

63

9 17 59

62

17

17

17

17

17

18 68

18 68

15 66

15 66

10 65 14

17

15 66

17 67

54 43

54 43

18 68

17

17

16

16

18 68

18 68

18 68

16

16

16

16

16 67

16 67

17

9 17 59

17

17

17

14

15 66

61 71

60

61 71

61

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

OUT

BI

BI

BI

BI

OUT

IN

IN

A6*

BR0*

BPM0*

DBR*

DEFER*

DBSY*

A7*

A15*

A14*

REQ2*

A17*

A18*

PREQ*

IERR*

BPRI*

BNR*A4*

TRST*

LINT1

TEST2

TEST4

A16*

A20M*

A3*

A30*

A31*

A32*

A34*

A35*

A5*

A8*

ADSTB0*

ADSTB1*

BCLK1

BPM2*

BPM3*

FERR*

HIT*

HITM*

IGNNE*

LINT0

RSVD7

RSVD9

RSVD10

RSVD11

RSVD12

RSVD13

RSVD14

TEST1

TEST3

TEST5

TEST6

PROCHOT*

REQ0*

REQ1*

REQ3*

REQ4*

SMI*

TCK

TDO

THERMTRIP*

THRMDA

THRMDC

TMS

PRDY*

BPM1*

RS2*

RS1*

RS0*

RESET*

DRDY*

ADS*

A19*

A20*

A21*

A23*

A22*

A24*

A25*

A26*

A27*

A28*

A29*

A33*

STPCLK*

A13*

A12*

A11*

BCLK0

TDI

TRDY*

LOCK*

INIT*

A10*

A9*

(1 OF 8)

XDP/ITP SIGNALS

ADDR GROUP0

ADDR GROUP1

THERMAL

H CLKICH

CONTROL

D11*

D7*

D6*

D5*

D4*

D3*

D17*

D16*

DINV0*

DSTBP0*

DSTBN0*

D10*

D2*

SLP*

PWRGOOD

PSI*

GTLREF

DSTBP3*

DSTBP2*

DSTBN3*

DSTBN2*

DSTBN1*

DPWR*

DPSLP*

DPRSTP*

DINV3*

DINV2*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D53*

D52*

D51*

D50*

D49*

D48*

D47*

D46*

D45*

D44*

D43*

D42*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

D31*

D30*

D26*

D25*

D24*

D23*

D22*

D21*

D20*

D13*

D12*

D1*

D0*

COMP3

COMP2

COMP1

COMP0

BSEL2

BSEL1

BSEL0

D27*

D29*

D8*

DINV1*

DSTBP1*

D28*

D14*

D15*

D9*

D19*

D18*

D41*

(2 OF 8)

DATA GRP 3

DATA GRP1

MISC

DATA GRP 0

DATA GRP 2




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PLACE_NEARs:

C1014.1:R1006.1:R1005.2:

PLACE_NEARs:

R1020.1:R1021.1:R1022.1:R1023.1:

CPU JTAG Support

2

1R100054.9

1%

201

1/20WMF

2

1R1002685%

201

1/20WMF

2

1R1005

U1000.AW43:12.7 mm

1%1K

201

1/20WMF

2

1R10061%

U1000.AW43:12.7 mm

2K

201

1/20WMF

2

1R102354.9

1%

U1000.AF2:12.7 mm

201

1/20WMF

2

1R102227.41%

U1000.AE1:12.7 mm

201

1/20WMF

2

1R102154.9

1%

U1000.AD44:12.7 mm

201

1/20WMF

2

1R102027.41%

U1000.AE43:12.7 mm

201

1/20WMF

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

14 53 65

14 65

14 65

14 65

13 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

9 65

9 65

9 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

7 14 65

14 65

14 65

14 65

14 65

14 65

14 65

7 14 65

7 14 65

7 14 65

13 65

13 65

13 65

13 65

13 65

13 65

10 13 65

14 39 65

44 71

14 39 65

14 65

13 14 65

14 65

14 65

14 65

14 65

10 13 65

10 13 65

10 13 65

10 13 65

44 71

14 65

14 65

14 65

14 65

14 65

14 65

14 65

21

R1010NO STUFF

5%

0

201

1/20WMF

2

1R1011NO STUFF

1K5%

201

1/20WMF

2

1R100154.9

1%

201

1/20WMF

21

R1090

1%

54.9

201

1/20WMF

21

R1091

1%

54.9

201

1/20WMF

21

R1093

1%

54.9

201

1/20WMF

7 14 65

7 14 65

7 14 65

7 14 65

21

R1094

MF

54.9

1%

201

1/20W

2

1R1012NO STUFF

1K5%

201

1/20WMF

2

1C1014

U1000.AE41:12.7 mm

NO STUFF

X5R

10%0.1UF

201

6.3V

21

R1092

1/20W1%

54.9

PLACE_NEAR=J1300.52:12.7 mm

201MF

13 25

14 65

14 65

AV8

L1

AW5

BD34

BB34

B10

AC43

AY10

AE41

C43

D40

E37

AU1

AW7

AV4

F8

E5

F4

J9

AL5

AG5

Y2

V2

H8

K4

H4

K2

G5

W5

P4

U1

R5

R1

D38

AV2

AV10

N1

C5

C9

D8

F10

B40

F2

H2

D4

F38

N5

J1

J7

M2

L5

AY2

BA5

BA7

AY8

J5

C35

A35

AN5

Y4

M4

T2

AB4

AA1

T4

W1

V4

AR1

AP2

AU5

AM2

AL1

AJ1

P2

AR5

AP4

AM4

AH4

AJ5

AF4

AH2

AT2

AK2

C7

AT4

AG1

AK4

AN1

AC1

AB2

AE5

AA5

AD4

AD2

AC5

U1000

NEED_TP=TRUE

NEED_TP=TRUE

OMIT_TABLE

BGA

PENRYN-SFF

CDC-QKWH-QS-1.2-10W-800-R0-1M

D10

E7

BD10

AW43

AY38

AL43

W43

J41

AY40

AK44

U43

K40

C41

B8

G7

BC37

AJ41

R43

P40

K44

L41

E41

AU43

BA35

BB40

BA41

G39

BC39

BC35

AT40

AY36

BB38

BA37

AR41

AW41

AU41

AV40

H44

AT44

AV38

AL41

AN41

AP40

AG43

AK40

AM40

AN43

AM44

H40

AH44

AF44

AG41

AJ43

AF40

AH40

AR43

AP44

T44

Y44

J43

Y40

AA43

AC41

AD40

AB40

AA41

U41

N43

W41

R41

E43

AB44

V44

V40

P44

L43

M44

G41

M40

T40

N41

G43

F40

AF2

AE1

AD44

AE43

B38

C37

A37

U1000OMIT_TABLE


BGA

PENRYN-SFF


CPU FSB

TP_CPU_TEST3

TP_CPU_TEST6TP_CPU_TEST5

CPU_TEST2CPU_TEST1

CPU_TEST4

XDP_DBRESET_L

TP_CPU_RSVD_H8

FSB_A_L<31>

FSB_A_L<24>

FSB_A_L<5>FSB_A_L<6>

FSB_A_L<18>

XDP_TCK

XDP_TRST_L

XDP_TMS

CPU_THERMD_P

XDP_TRST_L

XDP_BPM_L<3>

FSB_HIT_LFSB_HITM_L

CPU_TEST4

FSB_LOCK_L

FSB_RS_L<0>

CPU_GTLREF

TP_CPU_RSVD_AL5

XDP_TDI

XDP_TDO

=PP1V05_S0_CPU

CPU_BSEL<0>

CPU_TEST2

CPU_BSEL<1>

FSB_A_L<3>

FSB_REQ_L<0>

FSB_A_L<10>

CPU_COMP<2>CPU_COMP<3>

FSB_D_L<16>

FSB_DINV_L<0>

FSB_A_L<22>


FSB_A_L<14>


FSB_A_L<13>

FSB_A_L<35>


FSB_A_L<21>FSB_A_L<20>FSB_A_L<19>


FSB_A_L<4>

CPU_SMI_LCPU_NMI

FSB_A_L<28>

FSB_A_L<11>


FSB_A_L<27>

FSB_ADSTB_L<0>

FSB_A_L<12>

FSB_A_L<17>

CPU_STPCLK_L

FSB_REQ_L<1>

CPU_IGNNE_L

FSB_ADSTB_L<1>

FSB_A_L<34>

CPU_A20M_L

FSB_REQ_L<2>

FSB_D_L<9>

FSB_D_L<15>FSB_D_L<14>

FSB_D_L<28>

FSB_DSTB_L_P<1>FSB_DINV_L<1>

FSB_D_L<8>

FSB_D_L<29>

FSB_D_L<27>

CPU_BSEL<2>

CPU_COMP<1>



FSB_D_L<20>FSB_D_L<21>FSB_D_L<22>FSB_D_L<23>FSB_D_L<24>FSB_D_L<25>FSB_D_L<26>

FSB_D_L<30>FSB_D_L<31>FSB_DSTB_L_N<1>

FSB_D_L<2>

FSB_D_L<10>

FSB_DSTB_L_N<0>FSB_DSTB_L_P<0>

FSB_D_L<17>

FSB_D_L<3>FSB_D_L<4>FSB_D_L<5>FSB_D_L<6>FSB_D_L<7>

FSB_D_L<11>

CPU_FERR_L


CPU_TEST1

TP_CPU_RSVD_AG5TP_CPU_RSVD_Y2TP_CPU_RSVD_V2

TP_CPU_RSVD_F4TP_CPU_RSVD_J9

FSB_BPRI_L

CPU_INIT_L

FSB_CPURST_L

XDP_TCK

XDP_TDO

FSB_CLK_CPU_PFSB_CLK_CPU_N

FSB_D_L<32>FSB_D_L<33>FSB_D_L<34>FSB_D_L<35>FSB_D_L<36>FSB_D_L<37>FSB_D_L<38>FSB_D_L<39>FSB_D_L<40>FSB_D_L<41>FSB_D_L<42>FSB_D_L<43>FSB_D_L<44>FSB_D_L<45>FSB_D_L<46>FSB_D_L<47>FSB_DSTB_L_N<2>FSB_DSTB_L_P<2>FSB_DINV_L<2>

FSB_D_L<48>FSB_D_L<49>FSB_D_L<50>FSB_D_L<51>FSB_D_L<52>FSB_D_L<53>FSB_D_L<54>FSB_D_L<55>FSB_D_L<56>FSB_D_L<57>FSB_D_L<58>FSB_D_L<59>FSB_D_L<60>FSB_D_L<61>FSB_D_L<62>FSB_D_L<63>FSB_DSTB_L_N<3>FSB_DSTB_L_P<3>FSB_DINV_L<3>

CPU_DPRSTP_L

TP_CPU_PSI_L

FSB_BNR_LFSB_ADS_L

FSB_DEFER_LFSB_DRDY_LFSB_DBSY_L

XDP_BPM_L<5>

CPU_PROCHOT_L

PM_THRMTRIP_L

CPU_THERMD_N

XDP_TDI

XDP_BPM_L<4>

XDP_BPM_L<2>

FSB_TRDY_LFSB_RS_L<2>FSB_RS_L<1>

CPU_IERR_L

FSB_BREQ0_L

XDP_BPM_L<0>XDP_BPM_L<1>

CPU_INTR

FSB_REQ_L<4>FSB_REQ_L<3>

FSB_A_L<7>

FSB_A_L<23>

XDP_TMS

CPU_COMP<0>

FSB_CPUSLP_LCPU_PWRGDFSB_DPWR_LCPU_DPSLP_L

10 OF 110

4.4.0

051-8379

10 OF 73

10

10

10

10 13 65

10 13 65

10 13 65

10

33 65

10 13 65

10 13 65

8 11 12

10 65

65

65 10

65

65

VCCA

VID

VCC

VCC

VCCP

(3 OF 8)

VSSSENSE

VCCSENSE

VCC VCC

(7 OF 8)

VCCP VCCP

(8 OF 8)

VSS VSS

(6 OF 8)

VSSVSS

(4 OF 8)

VSSVSS

(5 OF 8)

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(CPU IO POWER 1.05V)

130 mA

(CPU CORE POWER)

18 A (CULV Design Target)17.6 A (CULV ICC_Max)

4500 mA (before VCC stable)2500 mA (after VCC stable)

(CPU INTERNAL PLL POWER 1.5V)

BC13

AY4

BB4

BC5

BB8

BB10

BC7

BD8

BD12

AC37

P38

R37

U37

V38

W37

J37

K38

AF38

AG37

AJ37

AK38

AA37

AB38

L37

N37

D34

B34

BD28

BB26

BD26

AT30

AT28

AV30

AV28

AY30

AY28

AT26

V32

AV26

AY26

AM30

AM28

AP30

AP28

AM26

AP26

AF30

AF28

W33

AH30

AH28

AK30

AK28

AF26

AH26

AK26

Y30

Y28

AB30

J33

AB28

AD30

AD28

Y26

AB26

AD26

P30

P28

T30

T28

K32

V30

V28

P26

T26

V26

K30

K28

M30

M28

K26

L33

M26

D28

D30

F30

F28

H30

H28

D26

F26

H26

M32

B28

B30

B26

BB32

BD32

AT34

AT32

AU33

AV32

AY32

N33

AL33

AM32

AN33

AP32

AR33

AE33

AF32

AG33

AH32

AJ33

F32

AK32

Y32

AA33

AB32

AC33

AD32

P32

R33

T32

U33

G33

H32

U1000


PENRYN-SFF

BGA

OMIT_TABLE

BB14

BD14

AT14

AV14

AY14

AM14

AP14

BB18

BB16

BD18

BD16

BB20

BD20

AT18

AT16

AV18

AV16

AY18

AY16

AT20

AV20

AY20

AM18

AM16

AP18

AP16

AM20

AP20

AF18

AF16

AH18

AH16

AF20

AH20

AK18

AK16

AK20

Y18

Y16

AB18

AB16

AD18

AD16

Y20

AB20

AD20

P18

P16

T18

T16

V18

V16

P20

T20

V20

K18

K16

M18

M16

K20

M20

D16

D18

F18

F16

H18

H16

D20

F20

H20

B16

B18

B20

BB24

BB22

BD24

BD22

AT24

AT22

AV24

AV22

AY24

AY22

AM24

AM22

AP24

AP22

AF24

AF22

AH24

AH22

AK24

AK22

Y24

Y22

AB24

AB22

AD24

AD22

P24

P22

T24

T22

V24

V22

K24

K22

M24

M22

D22

D24

F24

F22

H24

H22

B22

B24

BB30

BB28

BD30

U1000


PENRYN-SFF

BGA

OMIT_TABLE

AJ13

AJ11

AK14

AK12

AF10

AK10

Y14

AA13

AA11

AB14

AB12

AC13

AC11

AD14

AB10

P14

P12

R13

R11

T14

U13

U11

V14

V12

W13

W11

P10

V10

J13

J11

K14

K12

L13

L11

M14

N13

N11

K10

D12

D14

E13

E11

F14

F12

G13

G11

H14

H12

B12

B14

C13

AL35

AN35

AP36

AE35

AG35

AJ35

AF36

AK36

AA35

AC35

AB36

R35

U35

P36

V36

W35

J35

L35

N35

K36

D32

E35

E33

F34

G35

F36

H36

B32

C33

AL37

AN37

AP38

AE37

A13

A33

AL9

AL7

AN9

AN7

AR9

AR7

AE9

AE7

AG9

AG7

AJ9

AJ7

AA9

AA7

AC9

AC7

R9

R7

U9

U7

W9

W7

L9

L7

N9

N7

AU13

AU11

AL13

AL11

AN13

AN11

AP12

AR13

AR11

AP10

AE13

AE11

AF14

AF12

AG13

AG11

AH14

U1000


PENRYN-SFF

BGA

OMIT_TABLE

A7

A5

A9

A11

A15

A19

A17

A25

A23

A21

A29

A27

A31

A41

A39

BA1

AW1

E1

G1

BA3

BB2

BC3

BD4

AU3

AW3

AL3

AN3

AR3

AE3

AG3

AJ3

AA3

AC3

R3

U3

W3

J3

L3

N3

D2

E3

G3

B4

C3

BA9

BB6

BC9

BD6

AT8

AT6

AU9

AV6

AU7

AW9

AY6

AM8

AM6

AP8

AP6

AF8

AF6

AH8

AH6

AK8

AK6

Y8

Y6

U1000


PENRYN-SFF

BGA

OMIT_TABLE

G27

E31

G31

C27

C29

C31

BA33

BC33

BB36

BD36T42

AU35

AV34

AW35

AW33

AY34

AT36

AV36

AM34

AP34

AM36

V42

AR35

AF34

AH34

AH36

AK34

Y34

AB34

AD34

Y36

AD36

K42

P34

T34

V34

T36

K34

M34

M36

H34

D36

B36

M42

BA39

BC41

BD40

BD38

AT38

AU39

AU37

AW39

AW37

AL39

F44

AM38

AN39

AR39

AR37

AE39

AG39

AH38

AJ39

Y38

AA39

D44

AC39

AD38

R39

T38

U39

W39

J39

L39

M38

N39

D42

E39

G37

H38

C39

BA43

BB42

AY44

AV44

AT42

AV42

F42

AY42

AM42

AP42

G25

G23

G21

AF42

C21

C23

C25

BA29

BA27

BC29

BC27

BA31

BC31

AU29

AH42

AU27

AW29

AW27

AU31

AW31

AL29

AL27

AN29

AN27

AL31

AK42

AN31

AR29

AR27

AR31

AE29

AE27

AG29

AG27

AJ29

AJ27

Y42

AE31

AG31

AJ31

AA29

AA27

AC29

AC27

AA31

AC31

R29

AB42

R27

U29

U27

R31

U31

W29

W27

W31

J29

J27

AD42

L29

L27

N29

N27

J31

L31

N31

E29

E27

G29

P42

H42

B42

U1000BGA


PENRYN-SFF

OMIT_TABLE

AB8

AB6

AD8

AD6

P8

P6

T8

T6

V8

V6

U5

K8

K6

M8

M6

D6

E9

F6

G9

H6

B6

BA13

BA11

BB12

BC11

BA15

BC15

AT12

AV12

AW13

AW11

AY12

AU15

AW15

AT10

AM12

AL15

AN15

AR15

AM10

AH12

AE15

AG15

AJ15

AH10

Y12

AD12

AA15

AC15

Y10

AD10

T12

R15

U15

W15

T10

M12

J15

L15

N15

M10

E15

G15

H10

C11

C15

BA19

BA17

BC19

BC17

AU19

AU17

AW19

AW17

AL19

AL17

AN19

AN17

AR19

AR17

AE19

AE17

AG19

AG17

AJ19

AJ17

AA19

AA17

AC19

AC17

R19

R17

U19

U17

W19

W17

J19

J17

L19

L17

N19

N17

E19

E17

G19

G17

C17

C19

BA25

BA23

BA21

BC25

BC23

BC21

AU25

AU23

AU21

AW25

AW23

AW21

AL25

AL23

AL21

AN25

AN23

AN21

AR25

AR23

AR21

AE25

AE23

AE21

AG25

AG23

AG21

AJ25

AJ23

AJ21

AA25

AA23

AA21

AC25

AC23

AC21

R25

R23

R21

U25

U23

U21

W25

W23

W21

J25

J23

J21

L25

L23

L21

N25

N23

N21

E25

E23

E21

U1000BGA

PENRYN-SFF


OMIT_TABLE

53 65

2

1R1100

PLACE_NEAR=U1000.BD12:25.4 mm

1001%1/20WMF201

2

1R1101PLACE_NEAR=U1000.BC13:25.4 mm

1001%1/20WMF201

53 65

12 53 65

12 53 65

12 53 65

12 53 65

12 53 65

12 53 65

12 53 65


CPU Power & Ground

CPU_VID<0>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU

CPU_VID<4>

=PPVCORE_S0_CPU

CPU_VID<3>

CPU_VID<5>CPU_VID<6>


=PPVCORE_S0_CPU

11 OF 110

4.4.0

051-8379

11 OF 73

8 10 11 12

8 10 11 12

8 12

8 11 12 64

8 11 12 64

IN OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PLACE ON OPPOSITE SIDE OF CPU


CPU VCORE VID CONNECTIONS

VCCA (CPU AVdd) DECOUPLING

LAYOUT NOTE:

PLACE C1281 NEAR PIN B34 OF U1000

PLACE C1291-C1296 CLOSE TO FSB DATA PINSPLACE C1283-C1288 CLOSE TO FSB ADDRESS PINSPLACE C1290 CLOSE TO CPU

1x 270uF, 12x 2.2uF

VCCP (CPU I/O) DECOUPLING

1x 10uF, 1x 0.01uF

LAYOUT NOTE:

4x 270uF. 32x 10uF 0603, 28x 2.2uF 0402 + 40x 2.2uF 0402CPU VCORE HF AND BULK DECOUPLING

LAYOUT NOTE:


PLACE ON SAME SIDE AS CPU

LAYOUT NOTE:

LAYOUT NOTE:


LAYOUT NOTE:

LAYOUT NOTE:

LAYOUT NOTE:




LAYOUT NOTE:

LAYOUT NOTE:

2

1 C1210

CRITICALOMIT_TABLE

10UF

603X5R6.3V20%

2

1 C1216NOSTUFF

20%6.3VX5R603

10UF

CRITICAL

2

1 C1201NOSTUFF

10UF

603X5R6.3V20%

CRITICAL

2

1 C1202NOSTUFF

20%6.3VX5R603

10UF

CRITICAL

2

1 C1203NOSTUFF

10UF

603X5R6.3V20%

CRITICAL

2

1 C1204NOSTUFF

X5R

20%6.3V

603

10UF

CRITICAL

2

1 C1205NOSTUFF

10UF

603X5R6.3V20%

CRITICAL

2

1 C1206NOSTUFF

20%6.3VX5R603

10UF

CRITICAL

2

1 C1207NOSTUFF

10UF

603X5R6.3V20%

CRITICAL

2

1 C1208NOSTUFF

20%6.3VX5R603

10UF

CRITICAL

2

1 C1209NOSTUFF

20%6.3VX5R603

10UF

CRITICAL

2

1 C1229NOSTUFF

10UF

603X5R6.3V20%

CRITICAL

2

1 C1228NOSTUFF

20%6.3VX5R603

10UF

CRITICAL

2

1 C122710UF

603X5R6.3V20%

CRITICALOMIT_TABLE

2

1 C122620%6.3VX5R603

10UF

CRITICALOMIT_TABLE

2

1 C1225NOSTUFF

10UF

603X5R6.3V20%

CRITICAL

2

1 C1224NOSTUFF

20%6.3VX5R603

10UF

CRITICAL

2

1 C1223

CRITICALOMIT_TABLE

10UF

603X5R6.3V20%

2

1 C121420%6.3VX5R603

10UF

CRITICALOMIT_TABLE

2

1 C1222NOSTUFF

603

20%6.3VX5R

10UF

CRITICAL

2

1 C1221NOSTUFFCRITICAL

10UF

603X5R6.3V20%

2


10UF

603X5R6.3V20%

2


10UF

603X5R6.3V20%

2

1 C123010UF

603X5R6.3V20%

OMIT_TABLECRITICAL

2

1 C12492.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C12592.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C124820%6.3VCERM402-LF

2.2UF

CRITICALOMIT_TABLE

2

1 C125820%6.3VCERM402-LF

2.2UF

CRITICALOMIT_TABLE

2

1 C12472.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C124620%6.3VCERM402-LF

2.2UF

CRITICALOMIT_TABLE

2

1 C12572.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C125620%6.3VCERM402-LF

2.2UF

CRITICALOMIT_TABLE

2

1 C12452.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C124420%6.3VCERM402-LF

2.2UF

CRITICALOMIT_TABLE

2

1 C12552.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C125420%6.3VCERM402-LF

2.2UF

CRITICALOMIT_TABLE

2

1 C1243OMIT_TABLECRITICAL

2.2UF

402-LFCERM6.3V20%

2

1 C12532.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C124220%6.3VCERM402-LF

2.2UF

CRITICALOMIT_TABLE

2

1 C12412.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C125220%6.3VCERM402-LF

2.2UF

CRITICALOMIT_TABLE

2

1 C12512.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C12402.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C12502.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C12672.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C126620%6.3VCERM402-LF

2.2UF

CRITICALOMIT_TABLE

2

1 C12652.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C1264

CRITICAL

20%6.3VCERM402-LF

2.2UF

OMIT_TABLE

2

1 C12632.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C126220%6.3VCERM402-LF

2.2UF

CRITICALOMIT_TABLE

2

1 C12612.2UF

402-LFCERM6.3V20%

CRITICALOMIT_TABLE

2

1 C12602.2UF6.3V

402-LF

CRITICAL

CERM

20%

OMIT_TABLE

2

1 C12912.2UF

402-LFCERM6.3V20%

OMIT_TABLE

2

1 C12922.2UF

402-LFCERM6.3V20%

OMIT_TABLE

2

1 C12932.2UF

402-LFCERM6.3V20%

OMIT_TABLE

2

1 C1294OMIT_TABLE

2.2UF

402-LFCERM6.3V20%

2

1 C129520%6.3VCERM402-LF

2.2UF

OMIT_TABLE

2

1 C1296OMIT_TABLE

2.2UF

402-LFCERM6.3V20%

2

1 C1283OMIT_TABLE

20%6.3VCERM402-LF

2.2UF

2

1 C128820%6.3VCERM402-LF

2.2UF

OMIT_TABLE

2

1 C1287OMIT_TABLE

2.2UF

402-LFCERM6.3V20%

2

1 C128620%6.3VCERM402-LF

2.2UF

OMIT_TABLE

2

1 C1285OMIT_TABLE

20%6.3VCERM402-LF

2.2UF

2

1 C1284OMIT_TABLE

2.2UF

402-LFCERM6.3V20%

2

1C1270CRITICAL

270UF

TANTCASE-B4-SM

20%2V 2

1C1272CRITICAL

270UF

TANTCASE-B4-SM

20%2V2

1C1271

CASE-B4-SM

CRITICAL

2V20%

TANT

270UF

2

1C1290CRITICAL

270UF

TANTCASE-B4-SM

20%2V

11 53 65 65

2

1 C1213NOSTUFF

10UF

603X5R6.3V20%

CRITICAL

2

1 C1212NOSTUFF

20%6.3VX5R603

10UF

CRITICAL

2

1 C1211NOSTUFF

X5R

10UF

603

6.3V20%

CRITICAL

2

1 C1219NOSTUFF

10UF

603X5R6.3V20%

CRITICAL

2

1 C1200NOSTUFF

20%6.3VX5R603

10UF

CRITICAL

2

1 C1215NOSTUFF

10UF

603X5R6.3V20%

CRITICAL

2

1 C121710UF

603X5R6.3V20%

CRITICALOMIT_TABLE

2

1 C121820%6.3VX5R603

10UF

CRITICALOMIT_TABLE

2

1 C128110%10VX5R201

0.01UF

2

1C1280OMIT_TABLE

20%6.3VX5R603

10uF


CPU Decoupling & VID

CPU_VID<0..6>MAKE_BASE=TRUE

IMVP6_VID<0..6>

=PP1V05_S0_CPU

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

12 OF 110

4.4.0

051-8379

12 OF 73

8 10 11

8 11

8 11 64

IN

BI

BI

BI

BI

OUT

IN

BI

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

NC

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

OBSDATA_B3 OBSDATA_D3

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

TDI

OBSDATA_A3

SCL

VCC_OBS_AB

OBSDATA_B1OBSDATA_B0

OBSFN_B1

OBSDATA_A2

OBSFN_B0

PWRGD/HOOK0

HOOK3

SDA

OBSDATA_A0

518S0774

OBSFN_C1

NOTE: This is not the standard XDP pinout.

OBSDATA_B2

OBSDATA_A1

Direction of XDP adapter flexPlease place J1300 within 1" ofboard edge with odd-numbered pinsfacing edge. Avoid any tallcomponents between J1300 and edge.

TCK0

HOOK1

HOOK2

OBSDATA_C0

OBSFN_C0

OBSFN_D1

OBSDATA_D1

ITPCLK/HOOK4

VCC_OBS_CDITPCLK#/HOOK5

TMS

Use with 920-0782 Adapter Flex to support chipset debug.

TRSTnTCK1

RESET#/HOOK6

OBSDATA_C3

TDO

OBSDATA_C1

OBSDATA_C2

OBSDATA_D0

OBSDATA_D2

OBSFN_A1OBSFN_A0

XDP_PRESENT#

DBR#/HOOK7

OBSFN_D0

Micro2-XDP Connector

10 14 65 21

R13991K

XDP

1/20WMF201

5%

41

41

2

1R13151%

XDP

54.9

201

1/20WMF

2

1C1300XDP

10%

X5R

0.1UF

201

6.3V 2

1 C1301

201

6.3V

0.1UF

XDP

X5R

10%

10 65

10 65

10 65

10 14 65 21

R1303

PLACEMENT_NOTE=Place close to CPU to minimize stub.5%

1K

XDP

1/20WMF201

10 65

10 65

10 65

10 65

14 65

14 65

10 65

10 65

10 65

10 25

19

10 65

19

9

87

60

6

59

5857

5655

5453

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J1300F-ST-SM-HF

XDP_CONNCRITICAL

DF40C-60DS-0.4V

eXtended Debug Port (Micro-XDP)


=PP3V3_S0_XDP

JTAG_MCP_TRST_L

JTAG_MCP_TDI

FSB_CLK_ITP_N

XDP_CPURST_LXDP_DBRESET_L

XDP_TDO

XDP_TDIXDP_TMS

FSB_CLK_ITP_P

FSB_CPURST_L

TP_XDP_OBSFN_B0

TP_XDP_OBSDATA_B0


=PP1V05_S0_XDP

XDP_OBS20

TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B3

JTAG_MCP_TMS

XDP_TRST_L

JTAG_MCP_TDO

TP_XDP_OBSDATA_C0TP_XDP_OBSDATA_C1

TP_XDP_OBSDATA_C2TP_XDP_OBSDATA_C3

TP_XDP_OBSDATA_D0TP_XDP_OBSDATA_D1

TP_XDP_OBSDATA_D2TP_XDP_OBSDATA_D3



TP_XDP_OBSDATA_B2

TP_XDP_OBSDATA_B1

XDP_TCK

PM_LATRIGGER_LJTAG_MCP_TCK

XDP_PWRGDCPU_PWRGD

=I2C_XDP_SDA=I2C_XDP_SCL

13 OF 110

4.4.0

051-8379

13 OF 73

8

19

19

65

8

19

19

IN

IN

IN

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

BI

OUT

IN

IN

IN

IN

IN

IN

IN

CPU_A8*

CPU_DSTBN0*

CPU_DSTBP1*

CPU_D6*

CPU_D3*

CPU_D5*

CPU_D2*

CPU_D1*

CPU_DSTBP2*

CPU_DSTBN2*

CPU_DBI2*

CPU_D4*

CPU_DBI0*

CPU_DSTBP0*

CPU_DSTBN1*

CPU_DBI1*

CPU_DSTBP3*

CPU_DSTBN3*

CPU_DBI3*

CPU_A4*

CPU_A5*

CPU_A7*

CPU_A6*

CPU_A9*

CPU_A10*

CPU_A11*

CPU_A12*

CPU_A14*

CPU_A15*

CPU_A16*

CPU_A17*

CPU_A18*

CPU_A19*

CPU_A22*

CPU_A25*

CPU_A24*

CPU_A23*

CPU_A26*

CPU_A27*

CPU_A28*

CPU_A29*

CPU_A30*

CPU_A33*

CPU_A32*

CPU_A31*

CPU_A34*

CPU_A35*

CPU_A3*

CPU_ADSTB0*

CPU_ADSTB1*

CPU_REQ1*

CPU_REQ0*

CPU_REQ2*

CPU_REQ3*

CPU_REQ4*

CPU_ADS*

CPU_BNR*

CPU_DBSY*

CPU_BR0*

CPU_HITM*

CPU_HIT*

CPU_DRDY*

CPU_TRDY*

CPU_LOCK*

CPU_PROCHOT*

CPU_THERMTRIP*

CPU_FERR*

CPU_BSEL0

CPU_RS0*

CPU_RS1*

CPU_RS2*

BCLK_VML_COMP_GND

BCLK_VML_COMP_VDD

CPU_PECI

CPU_BSEL2

CPU_BSEL1

CPU_COMP_VCC

CPU_COMP_GND

CPU_D16*

CPU_D0*

CPU_D54*

CPU_D60*

CPU_D61*

CPU_D40*

CPU_D27*

CPU_D26*

CPU_D25*

CPU_D24*

CPU_D22*

CPU_D20*

CPU_D21*

CPU_D7*

CPU_D8*

CPU_D9*

CPU_D10*

CPU_D11*

CPU_D12*

CPU_D13*

CPU_D14*

CPU_D15*

CPU_D17*

CPU_D18*

CPU_D19*

CPU_D23*

CPU_D28*

CPU_D29*

CPU_D30*

CPU_D31*

CPU_D32*

CPU_D33*

CPU_D34*

CPU_D35*

CPU_D36*

CPU_D37*

CPU_D38*

CPU_D39*

CPU_D41*

CPU_D42*

CPU_D43*

CPU_D44*

CPU_D45*

CPU_D46*

CPU_D47*

CPU_D48*

CPU_D49*

CPU_D50*

CPU_D51*

CPU_D52*

CPU_D53*

CPU_D55*

CPU_D56*

CPU_D57*

CPU_D58*

CPU_D59*

BCLK_IN_P

BCLK_OUT_ITP_P

CPU_DEFER*

CPU_BPRI*

BCLK_OUT_CPU_P

BCLK_OUT_CPU_N

BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_OUT_NB_N

BCLK_IN_N

CPU_IGNNE*

CPU_A20M*

CPU_INIT*

CPU_INTR

CPU_NMI

CPU_SMI*

CPU_DPRSLPVR

CPU_DPRSTP*

CPU_STPCLK*

CPU_DPSLP*

CPU_DPWR*

CPU_SLP*

CPU_RESET*

CPU_PWRGD

CPU_A21*

CPU_D63*

CPU_D62*

CPU_A20*

CPU_A13*

SYMBOL 1 OF 11

FSB




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Loop-back clock for delay matching.

9

9

9

10 65

10 13 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

7 10 65

10 65

10 65

10 65

10 65

10 65

10 65

13 65

13 65

10 65

10 65

10 65

10 65

10 65

10 65

10 65

10 65

10 13 65

10 65

10 65

10 65

10 65

10 53 65

9

10 39 65

10 39 65

7 10 65

7 10 65

2

1R143649.9

MF1/20W

201

1%

2

1R1431

MF1/20W

201

1%49.9

2

1R1430

MF1/20W

201

49.91%

2

1R1435

MF1/20W

201

49.91%

2

1R1415

MF1/20W

201

625%

2

1R1410

MF1/20W

201

54.91%

2

1R1440

MF1/20W

201

150

NO STUFF

5%

53 65

7 10 65

7 10 65

10 65

10 65

10 65

10 65

7 10 65

AG32

V35

Y34

AC35

V34

AF34AD33AF33

AC34

V36U37V38U39U40

AA32

V32AG36

AA35

AG37

Y35Y33V33

AD32AD34

AC33

C37

J37

R34

J38

C38

J36

R35

J39

U32

U33Y32

AA34

D2

AG35

AF35

B35

L35

U36

F39

L37H40P40

D38A36D36B37

M40

A35C35E37B38C36A37E38C39E40D40

L40

E36D39J35H37F37M34L36H34H35J34

L39

M32M36M33L34M35L33F36H36R39R32

L38

P32P33P36P38P37P34R40U34R33R38

P39

P35R37R36U35J40H39M38H38F40F38

M39M37

AK38AK37

D35E35F35

AG34

AF32

AD35

AF38Y37

AG33

V39Y40Y39V40Y36V37

AG38AG40AJ40AF37AD36AD39

U38

AG39AF40AF36AC39AD40AC37AC40AJ39AD37

AA33

AJ38AC38AD38AF39AA38AA40AC36Y38

AA37AA36AA39

AK39AK40

AJ35AJ34

AK32AK33

AJ37AJ36

AJ33AJ32

U1400BGA

MCP89U-A01

OMIT_TABLE

SYNC_MASTER=K16_MLB

MCP CPU InterfaceSYNC_DATE=07/07/2010





FSB_DSTB_L_P<2>

FSB_DINV_L<2>

FSB_DSTB_L_P<3>FSB_DSTB_L_N<3>

FSB_DSTB_L_P<0>FSB_DSTB_L_N<0>

FSB_A_L<14>

FSB_A_L<18>

FSB_A_L<4>

FSB_DINV_L<1>

FSB_D_L<12>

FSB_A_L<3>

FSB_DINV_L<3>

FSB_CLK_MCP_NFSB_CLK_MCP_P

FSB_DEFER_L

CPU_A20M_L

FSB_D_L<52>

FSB_CLK_ITP_N

MCP_CPU_COMP_GNDMCP_CPU_COMP_VCC

MCP_BCLK_VML_COMP_GND

FSB_ADSTB_L<0>

FSB_A_L<32>

FSB_ADSTB_L<1>


FSB_REQ_L<1>

FSB_A_L<35>

FSB_REQ_L<0>

FSB_BREQ0_L

CPU_PWRGD

FSB_CPUSLP_L

CPU_DPRSTP_L

FSB_BNR_L


FSB_D_L<41>

=PP1V05_S0_MCP_FSB

=PP1V05_S0_MCP_FSBFSB_D_L<62>FSB_D_L<63>

FSB_DPWR_LCPU_DPSLP_L

CPU_STPCLK_L

PM_DPRSLPVR

CPU_NMICPU_INTRCPU_INIT_L

FSB_D_L<57>

FSB_D_L<55>

FSB_D_L<53>

FSB_D_L<50>




FSB_D_L<30>FSB_D_L<29>FSB_D_L<28>

FSB_D_L<23>





FSB_D_L<22>

FSB_D_L<24>FSB_D_L<25>FSB_D_L<26>FSB_D_L<27>

FSB_D_L<60>

FSB_D_L<54>

FSB_D_L<0>

FSB_D_L<16>

=MCP_BSEL<1>=MCP_BSEL<2>

CPU_PECI_MCP

MCP_BCLK_VML_COMP_VDD

FSB_RS_L<2>FSB_RS_L<1>FSB_RS_L<0>

=MCP_BSEL<0>

PM_THRMTRIP_LCPU_PROCHOT_L

FSB_LOCK_LFSB_TRDY_L

FSB_DRDY_LFSB_HIT_LFSB_HITM_L

FSB_ADS_L

FSB_REQ_L<4>FSB_REQ_L<3>FSB_REQ_L<2>

FSB_A_L<28>

FSB_A_L<26>

FSB_A_L<19>


FSB_DSTB_L_N<1>FSB_D_L<4>

FSB_DSTB_L_N<2>


FSB_D_L<5>

FSB_D_L<3>

FSB_D_L<6>

FSB_DSTB_L_P<1>

FSB_DINV_L<0>

FSB_D_L<40>

FSB_D_L<42>

FSB_D_L<49>

FSB_D_L<56>


FSB_CLK_ITP_P

FSB_CLK_CPU_NFSB_CLK_CPU_P

FSB_A_L<34>

FSB_BPRI_L

FSB_D_L<51>

FSB_D_L<48>

FSB_D_L<45>

CPU_IGNNE_L

CPU_SMI_L

FSB_CPURST_L

FSB_D_L<37>

FSB_D_L<61>

CPU_FERR_L

FSB_DBSY_L

FSB_A_L<33>

FSB_A_L<24>

FSB_A_L<27>

FSB_A_L<25>

FSB_A_L<23>FSB_A_L<22>FSB_A_L<21>FSB_A_L<20>

FSB_D_L<31>

FSB_A_L<17>

14 OF 110

4.4.0

051-8379

14 OF 73

65

65

65

65

65

8 14 20 23

8 14 20 23

65

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

MCKE0A_0

MCKE0A_1

MCS0A_0*

MCS0A_1*

+VIO_PLL_CPU

+VIO_PLL_CPU

+VIO_PLL_CPU

+VIO_PLL_FSB

+VIO_PLL_FSB

+VIO_PLL_FSB

+VIO_PLL_MEM

+VIO_PLL_MEM

+VIO_M2CLK_DLL

+VIO_M2CLK_DLL

+VIO_M2CLK_DLL

MA0_0

MA0_8

MA0_9

MA0_10

MCAS0*

MBA0_0

MA0_15

MA0_14

MBA0_2

MBA0_1

MWE0*

MRAS0*

MDQS0_0_N

MDQS0_0_P

MDQS0_1_N

MDQS0_1_P

MDQS0_2_N

MDQS0_2_P

+VIO_PLL_MEM

MCLK0A_1_P

MCLK0A_1_N

MODT0A_1

MODT0A_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_7

MA0_11

MA0_12

MA0_13

MDQS0_3_N

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_4_P

MDQS0_7_N

MDQS0_7_P

MDQS0_6_P

MDQM0_5

MDQM0_6

MDQM0_7

MDQ0_60

MDQ0_55

MDQ0_56

MDQ0_52

MDQ0_51

MDQ0_15

MDQ0_48

MDQ0_40

MDQ0_39

MDQM0_2

MDQM0_3

MDQM0_1

MDQM0_0

MDQM0_4

MDQ0_0

MDQ0_1

MDQ0_2

MDQ0_3

MDQ0_4

MDQ0_5

MDQ0_6

MDQ0_10

MDQ0_9

MDQ0_7

MDQ0_8

MDQ0_11

MDQ0_14

MDQ0_13

MDQ0_12

MDQ0_16

MDQ0_21

MDQ0_20

MDQ0_19

MDQ0_18

MDQ0_17

MDQ0_26

MDQ0_25

MDQ0_23

MDQ0_22

MDQ0_31

MDQ0_30

MDQ0_29

MDQ0_28

MDQ0_27

MDQ0_36

MDQ0_35

MDQ0_34

MDQ0_33

MDQ0_32

MDQ0_41

MDQ0_38

MDQ0_37

MDQ0_46

MDQ0_45

MDQ0_44

MDQ0_43

MDQ0_42

MDQ0_47

MDQ0_50

MDQ0_49

MDQ0_54

MDQ0_53

MDQ0_57

MDQ0_59

MDQ0_58

MDQ0_24

MDQ0_61

MDQ0_62

MDQ0_63

MDQS0_6_N

MCLK0A_0_N

MCLK0A_0_P

MEMORY PARTITION 0

SYMBOL 2 OF 11

MRESET0*

MDQM1_0

MDQM1_1

MDQM1_2

MDQM1_3

MDQM1_4

MDQM1_5

MDQM1_6

MDQM1_7

MDQ1_59

MDQ1_61

MDQ1_60

MDQS1_1_P

MDQS1_1_N

MDQS1_0_P

MRAS1*

MDQ1_47

MDQ1_43

MDQ1_58

MDQS1_0_N

MDQS1_2_P

MDQS1_3_N

MDQ1_0

MDQ1_3

MDQ1_2

MDQ1_1

MDQ1_11

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_16

MDQ1_17

MDQ1_18

MDQ1_19

MDQ1_20

MDQ1_21

MDQ1_22

MDQ1_23

MDQ1_24

MDQ1_25

MDQ1_26

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_30

MDQ1_31

MDQ1_33

MDQ1_34

MDQ1_35

MDQ1_36

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_40

MDQ1_41

MDQ1_42

MDQ1_44

MDQ1_45

MDQ1_46

MDQ1_48

MDQ1_49

MDQ1_50

MDQ1_51

MDQ1_52

MDQ1_53

MDQ1_54

MDQ1_55

MDQ1_56

MDQ1_57

MDQ1_62

MDQ1_63

MA1_14

MA1_15

MDQS1_7_P

MDQS1_7_N

MDQS1_6_P

MDQS1_6_N

MDQS1_5_P

MDQS1_5_N

MDQS1_4_P

MDQS1_4_N

MDQS1_3_P

MDQS1_2_N

MDQ1_32

MEM_COMP_GND

MEM_COMP_VDD

MA1_13

MA1_12

MA1_11

MA1_10

MA1_9

MA1_8

MA1_7

MA1_6

MA1_5

MA1_4

MA1_3

MA1_2

MA1_1

MA1_0

MDQ1_4

MDQ1_5

MDQ1_6

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_10

MCLK1A_1_P

MCLK1A_1_N

MCLK1A_0_P

MCLK1A_0_N

MCS1A_0*

MCS1A_1*

MODT1A_0

MODT1A_1

MCKE1A_0

MCKE1A_1

MWE1*

MCAS1*

MBA1_1

MBA1_2

MBA1_0

SYMBOL 3 OF 11

MEMORY PARITION 1




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

550 mA

25 mA

25 mA

20 mA 70 mA

27 66

27 66

27 66

27 66

26 66

26 66

26 66

26 66

26 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

9 66

9 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

26 27 32 66

21 26 27 32 66

21 26 27 32 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

27 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

26 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

28 66

29 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

28 29 32 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

29 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

28 66

29 66

28 66

29 66

29 66

29 66

28 66

28 66

28 66

28 66

9 66 9 66

21 28 29 32 66

21 28 29 32 66

9 66

9 66

28 29 32 66

28 29 32 66

26 27 28 29

2

1R1520

MF1/20W

201

1K5%

2

1R1511

MF1/20W

201

40.21%

2

1R1510

MF1/20W

201

1%40.2

AJ31AH30AH29

AF31AF30AF29

AG31AG30AG29

AK31AK30AJ30

AM18

AR17

AP14AN17

AR4AR5AT6AU6AN11AM11AT12AR12AR29AP29AR32AP32AV36AU36AN35AN34

AN5AM9AR9

AM14AT29AN32AT36AN37

AV37AU38AR35

AN6AN4AT4AU3

AN36

AM7AN7AT5AT3AU5AV5AR6AN9AV3AV4

AM35

AM8AN8AP8AP9

AN12AT11AT8AR8AT9

AM12

AM34

AP12AN14AT14AR14AR11AP11AM15AN15AR27AT27

AR36

AM30AN30AN27AP27AN29AM29AT30AT32AP33AR33

AR37

AP30AR30AM33AN33AU35AV35AT37AT38AT33AT35

AM36AM37

AP15AN18

AM21AN21

AM20AN20

AM27AM26

AM17

AR26AR18AP17

AP24AN24AR23AM23AM24AN23AR21AP20

AN26AP26AR15AR24AP23AP18

AP21AR20

U1400BGAMCP89U-A01

OMIT_TABLE

AY18

AM6

AW18

AT17AW17

AL24AL23

AN2AN3AY5AY4AV11AW11AV14AW14AW27AY27AV32AW32AY37AY36AN38AN39

AR3AY6AV9

AY14AV27AU30AW37AR38

AW38AV38AR40

AM1AN1AT1AU1

AR39

AM3AM2AR2AR1AW3AW4AU8AV8AU2AV2

AM39

AW6AV6AY9AW9

AY11AY12AW8AY8AU9

AU11

AM38

AU12AU14AV15AU15AW12AV12AY15AW15AW26AY26

AT40

AV29AW29AU26AV26AU27AU29AW30AV30AY33AW33

AU40

AY29AY30AU32AY32AW35AY35AV39AU39AV33AU33

AN40AM40

AT15AY17

AV20AW20

AT20AU20

AT24AT26

AV17

AW24AT18AV18

AY23AU23AV23AT21AT23AU21AV21AY21

AU24AV24AU17AY24AW23AU18

AW21AY20

U1400BGA

MCP89U-A01

OMIT_TABLE


MCP Memory Interface

=PP1V5R1V35_S3_MCP_MEM

=PP1V5R1V35_SW_MCP_MEM

MEM_A_DQS_N<6>

MEM_A_DQ<63>MEM_A_DQ<62>MEM_A_DQ<61>

MEM_A_DQ<24>

MEM_A_DQ<58>MEM_A_DQ<59>

MEM_A_DQ<57>



MEM_A_DQ<47>

MEM_A_DQ<42>MEM_A_DQ<43>MEM_A_DQ<44>MEM_A_DQ<45>MEM_A_DQ<46>


MEM_A_DQ<41>






MEM_A_DQ<16>

MEM_A_DQ<12>MEM_A_DQ<13>MEM_A_DQ<14>

MEM_A_DQ<11>



MEM_A_DQ<6>MEM_A_DQ<5>MEM_A_DQ<4>MEM_A_DQ<3>MEM_A_DQ<2>MEM_A_DQ<1>MEM_A_DQ<0>

MEM_A_DM<4>

MEM_A_DM<0>MEM_A_DM<1>

MEM_A_DM<3>MEM_A_DM<2>


MEM_A_DQ<48>

MEM_A_DQ<15>



MEM_A_DQ<60>

MEM_A_DM<7>MEM_A_DM<6>MEM_A_DM<5>

MEM_A_DQS_P<6>

MEM_A_DQS_P<7>MEM_A_DQS_N<7>

MEM_A_DQS_P<4>

MEM_A_DQS_P<5>MEM_A_DQS_N<5>

MEM_A_DQS_N<4>MEM_A_DQS_P<3>MEM_A_DQS_N<3>

MEM_A_A<13>MEM_A_A<12>MEM_A_A<11>

MEM_A_A<7>MEM_A_A<6>MEM_A_A<5>MEM_A_A<4>MEM_A_A<3>MEM_A_A<2>MEM_A_A<1>

MEM_A_ODT<0>MEM_A_ODT<1>

MEM_A_DQS_P<2>MEM_A_DQS_N<2>MEM_A_DQS_P<1>MEM_A_DQS_N<1>MEM_A_DQS_P<0>MEM_A_DQS_N<0>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_BA<1>MEM_A_BA<2>

MEM_A_A<14>MEM_A_A<15>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_A<10>MEM_A_A<9>MEM_A_A<8>

MEM_A_A<0>

=PP1V05_S0_MCP_M2CLK_DLL

MEM_A_CS_L<1>MEM_A_CS_L<0>

MEM_A_CKE<1>MEM_A_CKE<0>

MEM_B_BA<0>

MEM_B_BA<2>MEM_B_BA<1>

MEM_B_CAS_LMEM_B_WE_L

MEM_B_CKE<1>MEM_B_CKE<0>

MEM_B_ODT<1>MEM_B_ODT<0>

MEM_B_CS_L<1>MEM_B_CS_L<0>

MEM_B_CLK_N<0>MEM_B_CLK_P<0>

MEM_B_CLK_N<1>MEM_B_CLK_P<1>

MEM_B_DQ<7>MEM_B_DQ<6>MEM_B_DQ<5>MEM_B_DQ<4>

MEM_B_A<0>MEM_B_A<1>MEM_B_A<2>MEM_B_A<3>MEM_B_A<4>MEM_B_A<5>MEM_B_A<6>MEM_B_A<7>MEM_B_A<8>MEM_B_A<9>MEM_B_A<10>MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>

MCP_MEM_COMP_VDDMCP_MEM_COMP_GND

MEM_B_DQ<32>

MEM_B_DQS_N<2>

MEM_B_DQS_P<3>MEM_B_DQS_N<4>MEM_B_DQS_P<4>MEM_B_DQS_N<5>MEM_B_DQS_P<5>MEM_B_DQS_N<6>MEM_B_DQS_P<6>MEM_B_DQS_N<7>MEM_B_DQS_P<7>

MEM_B_A<15>MEM_B_A<14>

MEM_B_DQ<63>MEM_B_DQ<62>

MEM_B_DQ<57>MEM_B_DQ<56>MEM_B_DQ<55>MEM_B_DQ<54>MEM_B_DQ<53>MEM_B_DQ<52>MEM_B_DQ<51>MEM_B_DQ<50>MEM_B_DQ<49>MEM_B_DQ<48>

MEM_B_DQ<46>MEM_B_DQ<45>MEM_B_DQ<44>

MEM_B_DQ<42>MEM_B_DQ<41>MEM_B_DQ<40>MEM_B_DQ<39>MEM_B_DQ<38>MEM_B_DQ<37>MEM_B_DQ<36>MEM_B_DQ<35>MEM_B_DQ<34>MEM_B_DQ<33>

MEM_B_DQ<31>MEM_B_DQ<30>MEM_B_DQ<29>MEM_B_DQ<28>MEM_B_DQ<27>MEM_B_DQ<26>MEM_B_DQ<25>MEM_B_DQ<24>MEM_B_DQ<23>MEM_B_DQ<22>MEM_B_DQ<21>MEM_B_DQ<20>MEM_B_DQ<19>MEM_B_DQ<18>MEM_B_DQ<17>

MEM_B_DQ<15>MEM_B_DQ<14>MEM_B_DQ<13>MEM_B_DQ<12>MEM_B_DQ<11>


MEM_B_DQ<0>

MEM_B_DQS_N<3>MEM_B_DQS_P<2>

MEM_B_DQS_N<0>

MEM_B_DQ<58>

MEM_B_DQ<43>

MEM_B_DQ<47>

MEM_B_RAS_L

MEM_B_DQS_P<0>MEM_B_DQS_N<1>MEM_B_DQS_P<1>


MEM_B_DQ<59>

MEM_B_DM<7>MEM_B_DM<6>MEM_B_DM<5>MEM_B_DM<4>MEM_B_DM<3>MEM_B_DM<2>MEM_B_DM<1>MEM_B_DM<0>

MEM_RESET_L


MEM_A_CLK_P<0>MEM_A_CLK_N<0>

MEM_B_DQ<16>

MEM_A_CLK_N<1>

PP1V05_S0_MCP_PLL_FSBMEM

MEM_A_CLK_P<1>

15 OF 110

4.4.0

051-8379

15 OF 73

8

20 21 23

8 23

66

66

23

IN

IN

IN

IN

IN

IN

IN

IN OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

PEC_CLKREQ*/GPIO_51

PE2_REFCLK_P

PE2_REFCLK_N

PEA_CLKREQ*/GPIO_49

PEB_CLKREQ*/GPIO_50

PE0_REFCLK_P

PE0_REFCLK_N

PE1_REFCLK_P

PE1_REFCLK_N

PE_WAKE*

PE0_TX4_P

PE0_TX4_N

PE0_TX5_P

PE0_TX5_N

PE1_TX0_P

PE1_TX0_N

PE1_TX1_P

PE1_TX1_N

PEX_RST*

PEX0_TERM_P

PE0_RX4_P

PE0_RX4_N

PE0_RX5_N

PE0_RX5_P

PE1_RX0_P

PE1_RX0_N

PE1_RX1_P

PE1_RX1_N

+3.3V_PLL_HVDD

+VIO_PLL_PE

+VIO_PLL_PE

+VIO_PLL_PE

+VIO_PLL_XREF_XS

+VIO_PLL_XREF_XS

+VIO_PLL_XREF_XS

+VIO_PLL_SATA

+VIO_PLL_SATA

+VIO_PLL_SATA

+VIO_PLL_H

+VIO_PLL_H

PCI EXPRESS

SYMBOL 4 OF 11

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1PE1 ports are Gen1-only. 2 RCs: x1, x1

+VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GNDIf PE0[3:0] are not used,

+VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GNDIf PE0[4:5] and PE1[0:1] are not used,

2

1R1610

1/20WMF

201

2.49K1%

PLACE_NEAR=U1400.U5:12.7 mm

7 34

34

9

9

9

9

7 34 67

7 34 67 34 67

34 67

25

7 34 67

7 34 67

9 67

9 67

9

9

9

9

9

2

1R1600

MF1/20W

201

5%22K

U6

U5

U4

U1

V1

U7U3U2

Y8Y9

AA2AA3

Y7Y6

AA4AA5

V2V3

AA7AA6

Y3Y2

AA9AA8

Y4Y5

V5V4

AH12AH11AH10

AF12AE11AE10

AG12AG11AG10

AF11AF10

W10

U1400MCP89U-A01

BGA

OMIT_TABLE

9

MCP PCIe InterfacesSYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

PEG_CLK100M_N

ENET_CLKREQ_L

AP_CLKREQ_L

PEG_CLKREQ_L

=PEG_D2R_N<4>

PCIE_AP_D2R_N

PP1V05_S0_MCP_PLL_PEXSATA

=PEG_D2R_N<5>

TP_PCIE_PE4_R2D_CNTP_PCIE_PE4_R2D_CP

=PEG_R2D_C_P<4>=PEG_R2D_C_N<4>

TP_PCIE_PE1_D2RN

PCIE_AP_D2R_P

PP3V3_S0_MCP_PLL_HVDD

=PEG_D2R_P<5>

=PEG_D2R_P<4>

TP_PCIE_PE1_D2RP

TP_PCIE_CLK100M_PE2NTP_PCIE_CLK100M_PE2P

PCIE_RESET_L

PEG_CLK100M_P

PCIE_CLK100M_AP_P

PCIE_WAKE_L

=PEG_R2D_C_P<5>=PEG_R2D_C_N<5>

PCIE_CLK100M_AP_N

MCP_PEX0_TERMP

PCIE_AP_R2D_C_NPCIE_AP_R2D_C_P

16 OF 110

4.4.0

051-8379

16 OF 73

23

23

67

OUT

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IFPA_TXD0_N

IFPA_TXD0_P

DDC_DATA0/GPIO_39

DDC_CLK0/GPIO_38

RGB_DAC_VREF

+3.3V_RGBDAC

IFPA_TXD1_P

IFPA_TXD1_N

DDC_CLK1/GPIO_40

IFPB_TXC_P

IFPB_TXC_N

IFPB_TXD4_P

IFPB_TXD4_N

IFPB_TXD5_P

IFPB_TXD5_N

IFPB_TXD6_P

IFPB_TXD6_N

IFPB_TXD7_N

IFPB_TXD7_P

IFPA_TXC_P

IFPA_TXC_N

IFPA_TXD2_P

IFPA_TXD2_N

IFPA_TXD3_P

IFPA_TXD3_N

DP1_0_P/TMDS0_TX5_P

DP1_0_N/TMDS0_TX5_N

DP1_1_N/TMDS0_TX4_N

DP1_2_N/TMDS0_TX3_N

DP1_1_P/TMDS0_TX4_P

DP0_3_P/TMDS0_TXC_P

DDC_DATA1/GPIO_41

DP1_2_P/TMDS0_TX3_P

DP1_3_N/TMDS0B_TXC_N

DP1_3_P/TMDS0B_TXC_P

DP0_0_N/TMDS0_TX2_N

DP0_0_P/TMDS0_TX2_P

DP0_1_N/TMDS0_TX1_N

DP0_1_P/TMDS0_TX1_P

DP0_2_N/TMDS0_TX0_N

DP0_2_P/TMDS0_TX0_P

DP0_3_N/TMDS0_TXC_N

HPLUG_DET0/GPIO_20

HPLUG_DET1/GPIO_21

HPLUG_DET2/GPIO_22

DDC_DATA2/DP_AUX_CH0_N

DDC_CLK2/DP_AUX_CH0_P

DDC_DATA3/DP_AUX_CH1_N

DDC_CLK3/DP_AUX_CH1_P

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

LCD_PANEL_PWR/GPIO_58

IFPAB_VPROBE

IFPAB_RSET

TMDS0_VPROBE

TMDS0_RSET

+3.3V_PLL_DP0

+3.3V_PLL_DP0

+3.3V_PLL_USB

+3.3V_PLL_USB

+VIO_PLL_IFPAB

+VIO_PLL_IFPAB

+VIO_PLL_CORE_LEG

+VIO_PLL_CORE_LEG

+VIO_PLL_SPPLL0

+VIO_PLL_V

+VIO_PLL_SPPLL0

+VIO_PLL_V

+VIO_PLL_NV

+VIO_PLL_NV

+VDD_IFPA

+VDD_IFPB

+VIO_DP0

+VIO_DP0

+VIO_DP0

FLAT PANEL

RGB

SYMBOL 5 OF 11




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

=MCP_IFPB_TXD_P/N<0>

=MCP_IFPAB_DDC_CLK

GPIO Pull-Ups

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

NOTE: DP_AUX_CH1 also requires pull-downs if used for dual-mode DisplayPort (DP++). If unused no pulls are necessary, if used for TMDS/HDMI only then

210 mA

Okay to float all RGB_DAC signals.DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs).

NOTE: No Composite/S-Video/Component Video support on MCP89

TMDS/HDMI

TMDS_IG_TXC_P/NTMDS_IG_TXD_P/N<0>TMDS_IG_TXD_P/N<1>

LVDS_IG_A_CLK_P/N

LVDS

Interface Mode

LVDS_IG_A_DATA_P/N<0>LVDS_IG_A_DATA_P/N<1>

60 mA

40 mA160 mA

140 mA

180 mA

30 mA

180 mA

(GMUX_INT)

LVDS_IG_A_DATA_P/N<2>LVDS_IG_A_DATA_P/N<3>LVDS_IG_B_CLK_P/NLVDS_IG_B_DATA_P/N<0>LVDS_IG_B_DATA_P/N<1>LVDS_IG_B_DATA_P/N<2>LVDS_IG_B_DATA_P/N<3>

LVDS_IG_DDC_DATALVDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<5>

TMDS_IG_DDC_DATATMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<4>

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<3>

RGB DAC Disable:

Connect +3.3V_RGBDAC pin to GND.

(UNUSED)

(UNUSED)(UNUSED)

LVDS: Power +VDD_IFPx at 1.8V

=MCP_IFPA_TXD_P/N<3>=MCP_IFPA_TXD_P/N<2>=MCP_IFPA_TXD_P/N<1>=MCP_IFPA_TXD_P/N<0>

TMDS: Power +VDD_IFPx at 3.3V

=MCP_IFPB_TXD_P/N<1>=MCP_IFPB_TXD_P/N<2>=MCP_IFPB_TXD_P/N<3>

=MCP_IFPAB_DDC_DATA

=MCP_IFPA_TXC_P/N

=MCP_IFPB_TXC_P/N

MCP Signal

only pull-ups are necessary.

DDC Mode Pull-downs160 mA

60 mA

20 mA

NOTE: 100K pull-downs required if HPLUG_DET0/HPLUG_DET1 are not used.

40 mA

17

9

9

9 17 67

9 67

9 67

9 67

9 67

9 67

9 67

9 67

9 67

24 67

24 67

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9 59

24 67

24 67

9

9

9

9

9 67

9 67

9 67

9 67

9 17 67

9 17 67

9 17 67

9

9

9

9

9

9

9

9

9

9

7 17 37

17

21R1782 10K5% 1/20W MF 201

21R1781 10K5% 1/20W MF 201

21R1780 10K5% 1/20W MF 201

21R17115%

100K1/20W MF 201

21R17105%

100K1/20W MF 201

H29

K27

J29

M28L28

M27L27

M24L24

M25L25

M26L26

A26A27B26

A24A23

K30

M22L22

M23L23

A30C30B30

J26K26

C24B24

E24D24

G24F24

J24H24

C21

B21

H23J23

F23G23

D23E23

B23C23

K24K23

E30D30C29

F27G27

E27D27

C27B27

A29B29

H27J27

D26C26

F26E26

H26G26

F29

D29 H30

F30

G29

E29 J30

G30

U1400

CKPLUS_WAIVE=PwrTerm2Gnd

CKPLUS_WAIVE=PwrTerm2Gnd

BGAMCP89U-A01

OMIT_TABLE

21R17125%

100K1/20W MF 20121R1713

5%100K

1/20W MF 201

MCP GraphicsSYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

DP_IG_AUX_CH1_P

PP3V3_S0_MCP_PLL_DP_USBDP_IG_AUX_CH1_N

PP1V05_S0_MCP_PLL_CORE

=PP1V05_S0_MCP_PLL_IFP

=MCP_IFPB_TXD_N<2>

=MCP_IFPB_TXD_P<3>

DP_IG_AUX_CH0_PDP_IG_AUX_CH0_N

DP_IG_AUX_CH1_P

MCP_TMDS0_RSET

MCP_TMDS0_VPROBE

MCP_IFPAB_RSET

MCP_IFPAB_VPROBE

LCD_IG_PWR_ENLCD_IG_BKLT_ENLCD_IG_BKLT_PWM

=MCP_IFPAB_DDC_DATA=MCP_IFPAB_DDC_CLK

=MCP_IFPB_TXD_N<3>

=MCP_IFPB_TXD_P<2>

=MCP_IFPB_TXD_N<1>=MCP_IFPB_TXD_P<1>

=MCP_IFPB_TXD_N<0>=MCP_IFPB_TXD_P<0>

=MCP_IFPB_TXC_P=MCP_IFPB_TXC_N

=MCP_IFPA_TXD_N<3>=MCP_IFPA_TXD_P<3>




=MCP_IFPA_TXC_N=MCP_IFPA_TXC_P


DP_IG_AUX_CH0_PDP_IG_AUX_CH0_N

SATARDRVR_A_ENDP_IG_HPD1DP_IG_HPD0

DP_IG_ML1_N<0>DP_IG_ML1_P<0>

DP_IG_ML1_P<1>DP_IG_ML1_N<1>




DP_IG_ML0_P<1>

TP_MCP_RGB_DAC_VREF

PP3V3_S0_MCP_DAC

DP_IG_ML0_P<3>DP_IG_ML0_N<3>


DP_IG_ML0_N<1>

=PP3V3R1V8_S0_MCP_IFP_VDD

DP_IG_AUX_CH1_N

AUD_IP_PERIPHERAL_DETMIKEY_MIC_LOAD_DET

=PP3V3_S0_MCP_GPIO

SATARDRVR_A_EN

AUD_IP_PERIPHERAL_DETMIKEY_MIC_LOAD_DET

17 OF 110

4.4.0

051-8379

17 OF 73

23

23

24

9 17 67

9 17 67

9 17 67

8 24

9

24

24

9 17 67

7 17 37

17

8 18 19

17

IN

BI

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

USB0_P

USB0_N

SATA_A1_TX_P

SATA_A1_TX_N

SATA_A1_RX_P

SATA_LED*/GPIO_30

SATA_TERMP

USB1_P

USB1_N

USB2_P

USB2_N

USB3_N

USB6_P

USB7_P

USB7_N

USB4_P

USB4_N

USB5_P

USB5_N

USB_OC0*/GPIO_25

USB_OC1*/GPIO_26

USB_RBIAS_GND

RGMII_RXD0

RGMII_RXD1

RGMII_RXD2

RGMII_RXCTL

RGMII_RXCLK

RGMII_INTR/GPIO_35

+3.3V_PLL_MAC_DUAL

RGMII_COMP_VDD

RGMII_COMP_GND

RGMII_VREF

RGMII_TXD3

RGMII_TXCLK

RGMII_TXCTL

RGMII_MDC

RGMII_MDIO

RGMII_RESET*

RGMII_RXD3

BUF_25MHZ

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

USB3_P

USB6_N

SATA_A0_TX_P

SATA_A0_TX_N

SATA_A0_RX_N

SATA_A0_RX_P

NC

SATA_A1_RX_N

LAN

SYMBOL 6 OF 11

USB

SATA

BI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Bluetooth

Internal 19.5K Pull-Downs on all USB pairs

OHCI1/EHCI1

USB JTAG in S3/S4/S5.

Only USB8-11 support nV

Connect RGMII_RXD<0:3> together to 10K pull-down.Connect RGMII_RXCLK to 10K pull-down.Connect RGMII_RXCTL to 10K pull-down.Connect RGMII_INTR to 10K pull-down (if not used as GPIO).+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail.RGMII_COMP_VDD/_GND must remain connected as shown.Connect RGMII_VREF to 10K pull-down.Connect RGMII_MDIO to 10K pull-down.


20 mA

Internal MAC Disable:

All other pins can be left TP or NC.

AirPort (PCIe Mini-Card)

Camera/External E

External C

External A

EXTERNAL D

SD Card/ExpressCard

OHCI0/EHCI0

Geyser Trackpad/Keyboard

9

9 69

9 69

9 69

9 69

9 69

9 69

9 69

2

1R1810

MF1/20W

201

49.91%

2

1R1811

MF1/20W

201

1%49.9

7 37 68

7 37 68

46 68 71

46 68 71

9 68

9 68

2

1R18508.2K

MF1/20W

201

5%

2

1R1851

201MF

8.2K1/20W5%

7 37 68

7 37 68

9 68

9 68

9 68

9 68

36 68

36 68

2

1R1860

201

1%1/20W

887

MF

9 67

9 67

9 67

9 67

35 67

35 67

35 67

35 67

2

1R1805

MF1/20W

201

2.49K1%

9

2

1R1800

MF1/20W

201

5%100K

L19

G12H14

H20J20

G20F20

H21J21

A20A21

L21K21

E20D20

F21G21

E21D21

AG4

AG5

AF2AF3

AF4AF5

AF1AG1

AG2AG3

B15

D15J17F17F15

C14G14

G15C17H17C15

A15D17

G17

H18E15E17

K15K14

J18

AK36H15AM4V6G5

J14

U1400OMIT_TABLE

BGAMCP89U-A01

7 34 68

7 34 68

MCP SATA, USB & EthernetSYNC_DATE=07/07/2010SYNC_MASTER=K16_MLB

USB_TPAD_P

MCP_USB_RBIAS_GND

USB_BT_N

USB_EXTD_OC_L

ENET_CLK125M_RXCLK

ENET_RXD<0>

ENET_RXD<2>

ENET_ENERGY_DET

ENET_RX_CTRL

MXM_GOOD_L

MCP_MII_COMP_GND

ENET_MDIO

TP_ENET_RESET_L

TP_MCP_CLK25M_BUF0_R

TP_ENET_MDC

TP_ENET_TX_CTRLTP_ENET_CLK125M_TXCLK

TP_ENET_TXD<2>TP_ENET_TXD<3>

TP_ENET_TXD<0>TP_ENET_TXD<1>

USB_EXTD_P

SATA_HDD_D2R_N

SATA_ODD_D2R_NSATA_ODD_D2R_P

USB_EXTD_N

USB_TPAD_N

USB_EXTC_P

USB_MINI_PUSB_MINI_N

USB_EXTA_NUSB_EXTA_P

ENET_RXD<3>

=PP3V3_ENET_MCP_RMGT

MCP_MII_COMP_VDD

PP3V3_ENET_MCP_PLL_MAC

MCP_SATA_TERMP

SATA_ODD_R2D_C_NSATA_ODD_R2D_C_P

SATA_HDD_D2R_P

SATA_HDD_R2D_C_NSATA_HDD_R2D_C_P

ENET_RXD<1>

=PP3V3_S0_MCP_GPIO

MCP_RGMII_VREF

=PP3V3_S5_MCP_GPIO

USB_EXTA_OC_L

USB_CAMERA_PUSB_CAMERA_N

USB_SDCARD_PUSB_SDCARD_N

USB_BT_P

USB_EXTC_N

18 OF 110

4.4.0

051-8379

18 OF 73

68

7 37

69

8 20 23

69

23

67

8 17 19

8 19

36

OUT

OUT

IN OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

BI

OUT

OUT

BI

BI

BI

BI

IN

IN

BI

OUT

OUT

IN

IN

OUT

IN

OUT

OUT

BI

OUTIN

PKG_TEST2

PKG_TEST

TEST_MODE_EN

SUS_CLK/GPIO_34

XTALOUT_RTC

XTALIN_RTC

XTALIN

XTALOUT

JTAG_TCK

JTAG_TRST*

JTAG_TDO

JTAG_TMS

JTAG_TDI

MGPU_PIO3/GPIO_24

MGPU_PIO1/GPIO_7

MGPU_PIO2/GPIO_23

MGPU_PIO0/GPIO_6

INTRUDER*

MEMVTT_EN/GPIO_45

MCP_MEMVDD_EN/GPIO_44

PWRGD

RTC_RST*

PWRGD_SB

RSTBTN*

PWRBTN*

KBRDRSTIN*/GPIO_56

A20GATE/GPIO_55

SIO_PME*/GPIO_31

EXT_SMI*/GPIO_32

SMB_ALERT*/GPIO_64

SMB_DATA1/MSMB_DATA

SMB_CLK1/MSMB_CLK

SMB_DATA0

SMB_CLK0

THERM_DIODE_N

THERM_DIODE_P

SPKR/GPIO_1

SPI_DO/GPIO_09

SPI_DI/GPIO_08

MCP_VID3/GPIO_16

MCP_VID2/GPIO_15

SLP_RMGT*

SLP_S3*

FANRPM1/GPIO_63/MGPIO_3

FANCTL1/GPIO_62

FANCTL0/GPIO_61

FANRPM0/GPIO_60/MGPIO_2

MISC_VDDEN4/GPIO_19

MEM_VDD_SEL/GPIO_46

MISC_VDDEN3/GPIO_18

MISC_VDDEN2/GPIO_17

MISC_VDDEN1/GPIO_48

MISC_VDDEN0/GPIO_47

LPC_DRQ0*/GPIO_43

LPC_AD1

LPC_AD2

LPC_AD3

LPC_CLKRUN*/GPIO_42

LPC_SERIRQLPC_AD0

HDA_PULLDN_COMP

HDA_SYNC

HDA_RESET*

HDA_BITCLK

HDA_SDATA_OUT

HDA_SDATA_IN0

LPC_FRAME*

+VDD_HDA

SLP_S5*

MCP_WAKE_DIS*

MCP_WAKE_REQ* MCP_VID0/GPIO_13

MCP_VID1/GPIO_14

SPI_CLK/GPIO_11

SPI_CS0*/GPIO_10

LPC_RESET*

LPC_CLK0

HDA

LPC

SYMBOL 7 OF 11

MISC

OUTIN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Platform-Specific Connections

behavior of Inte’s SLP_S4# signalNOTE: MCP SLP_S5# signal has the


0 = USER mode (Normal boot mode)

FIXME: AUD_IPHS_SWITCH_EN WAS GPIO_2

internal ~9Kpull-up.

(IPU)

(IPU-S5)

(IPD)

(IPU)

(IPU-S5)

(IPD)

62.5 MHz

42.7 MHz

25.0 MHz

(IPU)

(IPU-S5)

(IPU)

(IPD)

70 mA

(IPD)

(IPU)

(IPU)

(IPU)

1

0

Frequency

24 MHz

14.31818 MHz

0

0

1

1

SPI Frequency Select

1

0

Frequency

BIOS Boot Select

0

LPC_FRAME#

LPC

(IPU)

(IPU)

0

NOTE: MCP89 does not support FWH, only LPC ROMs. So Apple designs will

HDA_SYNC

I/F

SPI_CLK

BUF_SIO_CLK Frequency

1

SPI

not use LPC for BootROM override.

MCP_SPKR:

(IPD)

(IPU)

(IPU-S5)

(IPD)

For EMI Reduction on HDA interface

1

SPI_DO

31.2 MHz

Connects to SMC for automatic recovery.

HDA Output Caps

NOTE: 42 & 62 MHz use FAST_READ command. Straps not provided on this page.

1 = SAFE mode (For ROMSIP recovery)

(IPD)

GPIO43 has

70 mA

has the behavior

signal.

NOTE: MCP SLP_S5# pin

of Intel’s SLP_S4#

GPIO Pull-Ups/Downs

7 38 40 68

19 25 68

7 38 40 25 68

12

R1961

201MF1/20W5%10K

21

R1953

201MF

1/20W

22

5%

7 37 68

21

R1952

201MF

1/20W

22

5%

21

R1951

MF1/20W

201

5%

22

21

R1950

201MF

1/20W

22

5%

7 37 68

7 37 68

7 37 68

2

1R1900

201MF

1/20W1%

49.9 7 37 68

25

25

25

25

38

38

13

25

19 54

19 54

19 54

19 54

44 71

44 71

7 19 38 57

57

7 38 39 57

40 68

19 40 68

40 68

40 68

2

1R1970

201MF1/20W

10K5%

39

2

1R195910K5%1/20WMF201 2

1R19751K1%1/20WMF201

25 68

19 34 57

41 68

41 68

41 68

41 68

2

1R1930

201MF

1/20W5%

10K

2

1R1931

1/20W

201MF

5%100K

13

13

13

13

13

25

38

38

39

2

1R1920

201MF

1/20W

49.9K1%

2

1R1921

201MF1/20W

49.9K1%

2

1 C1951

201

25VNPO

10PF5%

2

1C1950

201

25VNPO

5%10PF

2

1 C1953

201

25VNPO

5%10PF

2

1C1952

201

25VNPO

5%10PF

7 38 40

21

21 57

21

R1960

201MF

1/20W

22

5%

21R1910201MF1/20W

225%

21R1912201MF1/20W5%

2221R1911

201MF1/20W22

5%

21R1913201MF1/20W5%

22

7 38 40 68

7 38 40 68

7 38 40 68

7 38 40 68

38

7 37

7 19 40 47

19 22

7 19 37

19 38

19

19

38 39 57

9

19 39

21R1996 10K5% 1/20W MF 201

21R1980201MF1/20W

10K5%

21R1987201MF1/20W5%

100K

21R1990 10K5% 1/20W MF 201

21R1991201MF1/20W

10K5%

21R1989201MF1/20W5%

10K

21R1981201MF1/20W

10K5%

21R1992201MF1/20W

100K5%21R1993

201MF1/20W5%100K

21R1994201MF1/20W5%

100K21R1995

201MF1/20W100K

5%

21R1986201MF1/20W

100K5%

7 19 40

7 38 40 19 25 68 21

R1965

201MF

1/20W

33

5%

2

1R19665%

MF201

1/20W

10K

NO STUFF

21R19835% 201MF1/20W

10K

21R1998201MF1/20W5%

20K

21R1999201MF1/20W5%

100K

C18

B14

B18

A14

C2D1

A6

H9

E1

E14B9

H10G8

C6

C8B6

C5

D9

B8

A8C9

D14

D18

F12

F18E9

H12

C20B20

J12

G11F11E11F14A11

G9F9E6D5

C11

D11

E18

A9

D6E5E4E3

B11

H5

F5

F3

F2

F1 F4

H4H3H2H1

D3

E12B12C12D12

A12

G18

A4

B3

C3

C4A5

B4

G7

E8F8

D8

J11F6

U1400OMIT_TABLE

MCP89U-A01BGA

2

1R1956470

201MF

1/20W5%

DRAM_CFG1:L

2

1R1957

201MF1/20W5%

DRAM_CFG0:H

10K

2

1R1978

201MF1/20W

10K5%

DRAM_CFG2:H

2

1R19795%10K1/20WMF201

DRAM_CFG2:L

2

1R19765%

10K1/20W

MF201

DRAM_CFG3:H

2

1R19775%

10K1/20W

MF201

DRAM_CFG3:L

2

1R19585%1/20WMF201

10K

DRAM_CFG0:L

38 7 19 38 57


MCP HDA, LPC & MISC

ENET_LOW_PWRSDCARD_RESET

MEM_EVENT_L

LPCPLUS_GPIOMCP_CPU_VTT_EN_L

AUD_IPHS_SWITCH_ENGFXVCORE_PWR_EN

SMC_IG_THROTTLE_L

=PP3V3_S5_MCP_GPIO

=PP3V3_S0_MCP_GPIO=PP3V3_S3_MCP_GPIO

SPI_MISO

AP_PWR_EN

MCP_VID<0>MCP_VID<1>

MCP_CLK25M_XTALOUT

JTAG_MCP_TCK

JTAG_MCP_TDO

SM_INTRUDER_L

MCP_MEM_VDD_EN

HDA_SYNC_R

MLB_RAM_CFG2

MEM_EVENT_L

SDCARD_RESETENET_LOW_PWR

SPI_MOSI_R

MCP_THMDIODE_P

AP_PWR_EN

SMBUS_MCP_1_CLKSMBUS_MCP_1_DATA

LPC_RESET_L

MLB_RAM_CFG3MLB_RAM_CFG2MLB_RAM_CFG1MLB_RAM_CFG0

PM_CLK32K_SUSCLK_R

MLB_RAM_CFG1


HDA_SYNC_R

HDA_BIT_CLK_RHDA_SDOUT_R

LPC_FRAME_L

PP3V3_G3_RTC


LPC_AD<3>

HDA_RST_R_L

LPC_AD<0>

HDA_SYNC

=PP3V3_S0_MCP_GPIO

HDA_BIT_CLK

HDA_RST_L

HDA_SDOUT

LPC_AD<2>LPC_AD<1>

LPC_FRAME_R_L

MCP_SPKR

PM_RSMRST_L

LPC_CLK33M_SMC_R

SPI_CS0_R_LSPI_CLK_R

MCP_WAKE_REQ_L

PM_BATLOW_L

HDA_SDIN0

HDA_SDOUT_R

HDA_BIT_CLK_R

HDA_RST_R_LMCP_HDA_PULLDN_COMP

LPC_AD_R<0> LPC_SERIRQ

PM_CLKRUN_L

LPC_AD_R<3>LPC_AD_R<2>LPC_AD_R<1>

MCP_CPU_VTT_EN_LMLB_RAM_CFG0


MCP_THMDIODE_N

SMBUS_MCP_0_CLKSMBUS_MCP_0_DATA

PM_LATRIGGER_LSMC_WAKE_SCI_L

AUD_I2C_INT_LSMC_RUNTIME_SCI_L

PM_PWRBTN_LPM_SYSRST_DEBOUNCE_L

RTC_RST_L

MCP_PS_PWRGD

MCP_MEM_VTT_EN

SMC_IG_THROTTLE_L

GFXVCORE_PWR_ENAUD_IPHS_SWITCH_EN

SPIROM_USE_MLB

JTAG_MCP_TDI

JTAG_MCP_TMSJTAG_MCP_TRST_L

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALINRTC_CLK32K_XTALOUT

LPCPLUS_GPIOSMC_ADAPTER_EN

MLB_RAM_CFG3

MCP_MEM_VDD_SEL_1V5

MCP_VID<1>

SPI_MISO

PM_SLP_S3_LPM_SLP_RMGT_LPM_SLP_S4_L

MCP_VID<0>

=PP3V3_S3_MCP_GPIO

MCP_TEST_MODE_EN

LPC_RESET_L LPC_PWRDWN_L

PM_SLP_S5_LMAKE_BASE=TRUE

PM_SLP_S4_L

SPIROM_USE_MLB

19 OF 110

4.4.0

051-8379

19 OF 73

19

19

19 38

7 19 40

19

7 19 37

19 22

19 39

8 18

8 17 18 19

8 19

19 40 68

19 34 57

19 54

19 54

19 68

19

19

19

19

19

19

19 54

19 54

19 68

19 68

19 68

8 20 23

8 23

19 68

8 17 18 19

19 68

19 68

19 68 68

19

19

19

8 19

7 19 40 47

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VDD_MEM

+VTT_CPU2

+VTT_CPU2

+VTT_CPU2

+VTT_CPU2

+VTT_CPU2

+VTT_CPU2

+VTT_CPU2

+3.3V_HVDD

+3.3V

+VTT_CPU2

+3.3V

+3.3V

+VDD_DUAL_AUXC

+VDD_DUAL_AUXC

+3.3V_VBAT

+3.3V_DUAL_USB

+3.3V_DUAL_USB

+3.3V_DUAL

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+3.3V_DUAL_RMGT

+3.3V_DUAL_RMGT

+VDD_DUAL_RMGT

+VDD_DUAL_RMGT

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

SYMBOL 8 OF 11

POWER I

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREB

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA_SENSE

GND_COREA_SENSE

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_SATA_AVDD

+VIO_SATA_AVDD

+VIO_SATA_AVDD

+VIO_SATA_AVDD

+VIO_SATA_AVDD

+VIO_SATA_AVDD

+VIO_SATA_AVDD

+VIO_SATA_AVDD

+VIO_SATA_DVDD

+VIO_SATA_DVDD

+VIO_SATA_DVDD

+VIO_SATA_DVDD

+VIO_SATA_DVDD

+VIO_SATA_DVDD

+VIO_SATA_DVDD

+VIO_SATA_DVDD

+VIO_SATA_DVDD

+VIO_SATA_DVDD

+VIO_SATA_DVDD

GND_COREB_SENSE

+VDD_COREB_SENSE

POWER II

SYMBOL 9 OF 11

GND GND

SYMBOL 10 OF 11

GNDGND GND

GND

SYMBOL 11 OF 11




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.

400 MAPE1[1:0])

2000 mA 4300 mA

200 mA


30 mA

250 mA

150 mA

?? uA (G3) 5 mA (S0)

200 mA

40 mA240 mA140 mA

300 mA

regulators.

8450 mA (0.85V)

be used for remote sensing unless

15350 mA (0.85V)

(PE0[5:0]

COREA/COREB are powered by separate

(PE0[5:0], PE1[1:0])

1000 MA

100 mA

300 mA

Instead connect regulator sense point as close to COREB FET as possible.

NOTE: VDD_COREx_SENSE signals should NOT

N30T30L31

AA30E32

K31N29W30W29Y29Y30V29

AA29

U29V30R29P29U30L30T29L32P30R30

L29

M30M29A32D33C33

AB29AB30D32A33G32

E33

H32F32J33B32G33B33J32H33F33M31

C32

AC32AD31AC31AB31AD30AC30AD29AC29

AK13AJ26

AL30

AK5

AL29AL27AL26AL21AL20AL18AL17AL15AL14AL12

AK15

AL11AJ14AJ13AJ6AK7AJ15AJ16AJ25AJ8AJ7

AJ17

AJ1AK1AJ18AK10AJ20AJ3AJ29AJ5AJ11AK28

AK21

AK9AJ28AK25AK2AK6AK11AJ9AK24AK18AK29

AJ24

AJ4AK27AK8AK22AK14AJ21AJ22AK3AJ2AK23

AJ23

AK17AJ12AJ10AJ27AK20AK26AK4AK12AJ19AK16

AK19

L17K17

K18L18

A18

V9

K20L20

B17A17

J15

K29H11V10

U1400BGA

MCP89U-A01

OMIT_TABLE

AC6AD5AC5AC4AC3AD4AD3AD2

AC2AC1

AD1

AG7AF9AG6AG9AF8AF7AG8AF6

AD11AD7

AC10AC7AD9AC9AC8AD6

AE12AD12AC12AC11AD10

AD8

AA11Y12Y11W12W11V12

AB10U12

AB12AB11AA12

AA10

J9

M12M11AB23

M14M13L14L13

M2

AB20AB19AB18AB17AB22Y22Y21Y20Y19Y18

Y23

Y17AB21V22V21V20V18V19V17V23K4

M7

L6J5L1L2J6K11J3L3L4M5

L7

J7J1J2L5L11M4J4M3L9K5

K2

K8M1K7K10L12M6L10M10M8L8

M9

U9

R3R5N4R8

V11U11

P9

T12T11W24V24U24

AD22AD21AD20AD19AD18

R12

AD17N12

AA24Y24

AD23R11P7

P12P11

AC24

N11

AB24R6P6R7

AD24P5

R10N8R4P2

N2

R1P10N10N5R9P1R2P8P4P3

N7

J8

U8

U1400BGA

MCP89U-A01

OMIT_TABLE

AP36AL22K34AC18E22B34B19B22G10AW19

AB4

AU34AE31AN16AA22AC21AN25AH31AT31U31AL31

AB2

H31D10AU10W4AY38AU25AM32B10E10G13

T37

H13AW7E7

T33AW13AU22AP25AU19

D4AN28

T36

AT7AU7AW5

AU37V31

AH37T4

B39T2

N33

AL25

AY3AE33Y31

AA31AA23AU13K13

AB36W33

AP10

K37

AN19AV1

AE37B13AH7AW2Y10W19L15B7

AE4

G31K39D16G37B2D7

AW16W20AT2N34

AT10

AB5AT16W18AE5

AC20AW34

AE36G36H28D28AV40B28AH34E28AA20

AE8

AL2AL19AU31AP31AN13AP22AC23W37W39W36

G4

D22U23AW31AT25AA18AE39AT34A38AP19AH2

B5

AT13AT19W8AA19AU4B31H25U21P31G34

C40

AL34

U1400BGA

MCP89U-A01

OMIT_TABLE

AM5V8V7H7H6AK35AK34W2U17AP7AL13E13K33T10AA17N31T31AL39W31T7U18AP34AL10AP2W7W5AE7M21M20M19M18M17M15M16T8AE30D31AN22T34AW22K22L16E19AU28AW28AE29N37N36N39AB8AN10AW39AL5AH39AB39G39W17AW10AL33AH5AC17AH36AB7AH4T39D13AL7AE2AB37B36

D37E39C1

AL4AW36G22U20

AB34AU16AL37AN31AC19

T5E2G2

K19H8

H22AC22W23Y1

D19K36E25D34W21AP5

AT39AE34AL28E34K12U19W34U10B25

AB33AP39AW25R31G28AH8A3

H19W22

AP37AA1AL8

AT22AH33H16

AT28AP28U22

AP13G16E31K25G25AP4

AL16D25K28K16

AA21G19

AL36AP16E16B16

U1400MCP89U-A01

BGA

OMIT_TABLE


MCP Power & Ground


=PPVCORE_SW_MCP_GFX

=PP1V05_S0_MCP_PE_DVDD

PP1V05_S0_MCP_PE_AVDD PP1V05_S0_MCP_SATA_AVDD

=PP1V05_S0_MCP_SATA_DVDD

TP_MCP_VDDCOREB_SENSENTP_MCP_VDDCOREB_SENSEP

=PP1V05_S0_MCP_FSB

=PP3V3_S0_MCP_HVDD

=PP3V3_S0_MCP


PP3V3_G3_RTC

=PP3V3_S5_MCP


TP_MCP_VDDCOREA_SENSENTP_MCP_VDDCOREA_SENSEP

=PPVCORE_S0_MCP

=PP1V5R1V35_SW_MCP_MEM=PP1V05_SW_MCP_FSB

20 OF 110

4.4.0

051-8379

20 OF 73

8 23

22 24

8 23

23 23

8 23

8 14 23

8 23

8 23

8 23

8 19 23

8 23

8 18 23

8 23

15 21 23 8 23

NC

NC

OUT

OUTIN

BI

BI

BI

BI

D

G S

IN

VCC

D

DONE

G

GNDTHRM

S

EN

CNFG

PAD

D

G

G

D

S

S

D

G

G

D

S

S

NC

K1

G

S

SENSE

D

KELVIN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NO STUBS on CKE signals!

DIMM CKE Clamps

Q2355/Q2356 chosen for low output capacitance.

CKE must be held low to keep memory in self-refresh.

Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89.Clamps enable before MCP89 MEMVDD rail switched off.

<R1>

Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)

Gated Rail Savings: 120mW

NV Requirements:

NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.

- Min Ramp-Up Time: 20 uS (10% to 90%)

- FET Ron <= 3.8 mOhms

4250 mA

(OR 1.35V)

Q2300

Type

Part

N-Channel

STMFS4854N

- Max Ramp-Up Time: 65 uS (ENABLE to 90%)

Loading

(G driven to VCC)

C2300 helps reduce input raildroop during Q2300 turn-on.

Rds(on) 10 mOhm @3.2V

4.3 A (EDP)

43

43

2

1R2305

MF

560K1%1/20W

201

19 57

2

1 C23050.1UF

402CERM10V20%

2

1C2300CRITICAL

PLACE_NEAR=Q2300.9:2 mm

1206-1CERM-X5R

6.3V20%

100UF

15 28 29 32 66

15 28 29 32 66

15 26 27 32 66

15 26 27 32 66

21

3

Q2350SOD-VESM-HF

SSM3K15FV

19

2

1R23505%

10K

MF1/20W

201

1

9

6

4

7

2

8

5

3

U2305

CRITICAL

TDFNSLG5AP031

1

4

2

5

6

3

Q2355SOT-963

CRITICAL

NTUD3170NZXXG

1

4

2

5

6

3

Q2356SOT-963

CRITICAL

NTUD3170NZXXG

7 321

6

5

4

9

Q2300DFN

CRITICALSTMFS4855NS

MCP89 Memory Rail GatingSYNC_DATE=07/07/2010SYNC_MASTER=K16_MLB

PP1V5R1V35_SW_MCPMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.5VMAKE_BASE=TRUE


MCPMEM_GATE

MCPDDRFET_KELVIN

MCPDDRFET_SENSE

=PP1V5R1V35_S0_MCPDDRFET

MCP_MEM_VDD_EN


MCPMEM_CNFG

TP_MCPMEM_DONE

=PP5V_S3_MCPDDRFET

MCP_MEM_VTT_EN

=PP5V_S3_MCPDDRFET

MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_B_CKE<1>

MEM_B_CKE<0>

MEMVTT_EN_L

23 OF 110

4.4.0

051-8379

21 OF 73

8

8

15 20 23

8 21

8 21

OUT

OUT

S

D

G

IN

CNFG

EN

S

THRMGND

G

DONE

D

VCC

PAD




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

<C1>

Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)

(G driven to VCC)

- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)

Q2400

15.35 A (EDP)

NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.

droop during Q2400 turn-on.C2400 helps reduce input rail

N-Channel

Si4838BDY

3.2 mOhm @2.5V

- Min Ramp-Up Time: 100 uS (10% to 90%)

- FET Ron <= 2.5 mOhms

Gated Rail Savings: 860mW

NV Requirements:

Type

Part

Loading

Rds(on)

21

XW2401

PLACE_NEAR=C2400.2:1 mm

SM

21

XW2400SM


54 71

54 71

321

4

8765

Q2400SO-8SI4838BDY

CRITICAL

19

2

1 C240520%10VCERM402

0.1UF

2

1 C2400100UF


CRITICAL

1206-1CERM-X5R6.3V20%

2

1 C240610%

CERM

820PF

402

50V

1

9

6

4

7

2

8

5

3

U2405SLG5AP033

TDFN

CRITICAL


MCP89 GFX Core Rail Gating

=PPVCORE_SW_MCP_GFX

MCPCORES0_VSEN_N

MCPCORES0_VSEN_P

MCPGFX_GATE

MCPGFX_CNFG

GFXVCORE_PWR_EN

TP_MCPGFX_DONE

=PP5V_S0_MCPFSBFET

=PPVCORE_S0_MCPGFXFET



PPVCORE_SW_MCP_GFX

24 OF 110

4.4.0

051-8379

22 OF 73

20 24

8

8

NC

VOUT

EN

VIN

GND





36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MCP 3.3V DP & USB PLL Power

<Ra>

<Rb>

210 mA


260 mA

MCP CPU FSB (VTT) Power

MCP 3.3V PLL Power

50 mA

140 mA

800 mA

300 mA

555 mA

160 mA

325 mA

70 mA

240 mA

300 mA

5 mA (S0)

70 mA

30 mA550 mA

100 mA200 mA

150 mA

200 mA2000 mA

4300 mA (1.5V)

MCP 1.05V CPU/FSB/MEM PLL Power

MCP 1.05V PCIe/SATA PLL Power

MCP Memory Power

MCP 1.05V PCIE Digital Power

MCP 3.3V AUX/USB Power

MCP 3.3V I/O Power

MCP 3.3V MAC/SMU Power

MCP 0.9V AUX Core Power

250 mA

? uA (G3)

MCP 1.05V Memory DLL Power

MCP 1.05V Core/Misc PLL Power

MCP 0.9V MAC/SMU Power

MCP 1.05V SATA Digital Power

MCP S0 FSB (VTT) Power

MCP 3.3V/1.5V HDA Power

MCP 2.0V-3.3V RTC Power

MCP 1.05V PCIe Analog Power

500 mA

MCP 1.05V SATA Analog Power

8450 mA (0.85V)

MCP 3.3V MAC PLL POWER

20 mA 20 mA

MCP 3.3V PCIe/SATA I/O PLL Power

MCP Non-GFX Core Power

Vout = 0.8V * (Ra + Rb) / Rb, Rb ~ 320kOhms

2

1C259020%

4.7UF

603

6.3VCERM

2

1 C250320%

X5R

0.22UF6.3V

2012

1 C250220%

X5R0201

6.3V

1.0UF

2

1 C2507

X5R6.3V

201

10%0.1UF

2

1 C2506

X5R

0.1UF6.3V

201

10%2

1 C2505

X5R

0.1UF6.3V

201

10%2

1 C2504

X5R

0.1UF6.3V

201

10%2

1 C2508

X5R

0.1UF6.3V

201

10%

2

1 C253220%

X5R6.3V

1.0UF

02012

1 C253120%

X5R0201

1.0UF6.3V2

1C253020%

4.7UF

402X5R-1

4V 2

1C253620%

4.7UF

402X5R-1

4V

2

1 C2519

X5R6.3V

201

0.1UF10%

2

1 C2518

X5R201

6.3V10%0.1UF

2

1 C2517

X5R6.3V

201

10%0.1UF

2

1 C2516

X5R

10%6.3V

201

0.1UF

2

1 C2515

X5R

0.1UF6.3V

201

10%2

1 C2514

X5R6.3V

201

10%0.1UF

2

1 C2513

X5R

0.1UF6.3V

201

10%2

1 C2512

X5R

0.1UF6.3V

201

10%2

1 C2511

X5R

0.1UF6.3V

201

10%2

1C251020%

4.7UF

402X5R-1

4V

21

L2560

0603

30-OHM-5A

21

L256730-OHM-5A

0603

2

1C250020%

X5R

OMIT_TABLE

10UF

603-1

6.3V 2

1 C250120%4.7UF

402X5R-14V

2

1 C2527

X5R6.3V

201

0.1UF10%

2

1 C2526

X5R6.3V

201

0.1UF10%

2

1 C259120%

402

10VCERM

0.1UF

2

1 C2537

X5R6.3V

201

0.1UF10%

2

1 C2533

X5R

0.1UF10%

201

6.3V 2

1 C2534

X5R

10%0.1UF

201

6.3V

2

1 C2529

X5R

0.1UF10%6.3V

2012

1C252820%

4.7UF

402X5R-1

4V

2

1 C2549

X5R

0.1UF10%6.3V

2012

1C254820%

4.7UF

603

6.3VCERM

2

1 C2535

X5R6.3V

201

0.1UF10%

2

1 C255420%

402

10VCERM

0.1uF

2

1C255320%

4.7uF

603

6.3VCERM

2

1 C255120%

402

0.1uF

CERM10V2

1C255020%

4.7uF

603

6.3VCERM

2

1C254320%

4.7uF

603

6.3VCERM 2

1 C254420%

402

0.1uF

CERM10V 2

1 C254520%

402

0.1uF

CERM10V 2

1 C254620%

402CERM10V

0.1uF

2

1 C254720%

402

10V

0.1uF

CERM

2

1C252020%

X5R603-1

OMIT_TABLE

10UF6.3V 2

1 C252120%4.7UF

402X5R-14V 2

1 C252220%

X5R6.3V

0201

1.0UF

2

1 C252320%

X5R6.3V

0201

1.0UF

2

1 C252520%

X5R6.3V

0201

1.0UF

2

1C252420%

4.7UF

402X5R-1

4V

2

1C256020%

X5R

OMIT_TABLE

10UF6.3V

603-12

1 C256120%4.7UF

402X5R-14V 2

1 C256220%

X5R

1.0UF

0201

6.3V 2

1 C256320%

X5R6.3V

0201

1.0UF

2

1 C2564

X5R

0.1UF10%

201

6.3V

2

1C256720%

X5R

OMIT_TABLE

10UF

603-1

6.3V 2

1 C256820%4.7UF

402X5R-14V 2

1 C2569

X5R

10%

201

6.3V

0.1UF

2

1 C2565

X5R

0.1UF10%

201

6.3V 2

1 C2566

X5R

0.1UF6.3V

201

10%

2

1C254020%

4.7UF

402X5R-1

4V

2

1C259520%

4.7UF

PLACE_NEAR=R2595.1:50 mil CERM6.3V

6032

1 C259620%

402

0.1UF

CERM10V 2

1 C259720%

402

10VCERM

0.1uF

21

R2595

MF

0.33

5%1/16W

0402

2

1 C254220%

402CERM

0.1uF10V2

1C254120%

4.7UF

CERM603

6.3V

2

1 C2572

X5R6.3V

201

0.1UF10%

2

1 C2571

X5R

0.1UF6.3V

201

10%2

1C257020%

4.7UF

402X5R-1

4VPLACE_NEAR=R2570.1:50 mil

21

R2570

MF1/16W

0402

0.33

5%

2

1 C2573

X5R

0.1UF6.3V

201

10%

2

1 C2578

X5R

0.1UF6.3V

201

10%2

1 C2577

X5R6.3V

201

0.1UF10%

2

1 C2576

X5R201

0.1UF6.3V10%

2

1C257520%

4.7UF

402X5R-1

4V

2

1 C2583

X5R

0.1UF6.3V

201

10%2

1 C2582

X5R6.3V

201

0.1UF10%

2

1 C2581

X5R6.3V

201

10%0.1UF

2

1C258020%

4.7UF

402X5R-1

4V

2

1 C2579

X5R

0.1UF6.3V

201

10%

2

1 C2584

X5R

0.1UF6.3V

201

10%

2

1C255220%

4.7UF

603

6.3VCERM

21

L2570CRITICAL

0603

220-OHM-2.2A

21

L2580220-OHM-2.2A

0603

CRITICAL

21

L2575220-OHM-2.2A

0603

CRITICAL

21

L2595220-OHM-2.2A

CRITICAL

0603

21

L2590CRITICAL

FERR-240-OHM-200MA

0402

MCPHVDD:P3V3

2

1C255620%

402

0.1UF

CERM10V2

1C255520%

4.7UF

603CERM6.3V

21

L2555

0402

FERR-240-OHM-200MA

CRITICAL

2

1C255920%4.7UF

402X5R-14V

2

1C253820%

4.7UF

402X5R-1

4V

51

2

3

U2590SC70

CRITICALOMIT_TABLE

MIC5365-2.5V

2

1R259010K

201

5%1/20W

MF

MCPHVDD:P2V5

2

1C259220%

X5R

MCPHVDD:P2V5

1.0UF

0201

6.3V

2

1R2591

201

1%665K1/20W

MF

HVDDLDO:ADJ

2

1R2592HVDDLDO:ADJ

201

1%316K1/20W

MF

SYNC_DATE=07/07/2010

MCP Standard DecouplingSYNC_MASTER=K16_MLB

353S2979 IC,LDO,TPS717,ADJ,150MA,3%,SC70,HF1 CRITICAL HVDDLDO:ADJU2590

353S2988 IC,MIC5366,LDO REG,2.5V,150MA,SC701 CRITICALU2590 HVDDLDO:FIXED

=PPVCORE_S0_MCP



=PP1V05_S0_MCP_PE_DVDDMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_CORE

=PP3V3_S0_MCP_HVDD


MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

PP3V3_ENET_MCP_PLL_MAC=PP3V3_ENET_MCP_PLL_MAC

=PP1V05_S0_MCP_AVDD_UF

PP3V3_G3_RTC


=PP3V3_S5_MCP

=PP1V05_S0_MCP_FSB

=PP1V05_S0_MCP_SATA_DVDD


=PP1V05_S0_MCP_M2CLK_DLL

PP1V05_S0_MCP_PLL_FSBMEM

VOLTAGE=1.05V


VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V05_S0_MCP_PLL_PEXSATA

=PP3V3_S0_MCP


GND_MCP_PLL_FSBMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.25 MMVOLTAGE=0V


VOLTAGE=0VMIN_NECK_WIDTH=0.25 MM

GND_MCP_PLL_DP_USB

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V05_S0_MCP_SATA_AVDD

VOLTAGE=1.05V


PP1V05_S0_MCP_PE_AVDD

=PP1V05_SW_MCP_FSB


P2V8HVDD_EN

PP3V3_S0_MCP_PLL_HVDDMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

P2V8HVDD_FB

PP3V3_S0_MCP_PLL_DP_USBMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

25 OF 110

4.4.0

051-8379

23 OF 73

4

8 20

15 20 21

8 20

8 20 17

8 20

8

18 8

8

8 19 20

8 19

8 20

8 14 20

8 20

8 18 20

8 15

15

16

8 20

8 20

20

20

8 20

8 16

17




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

15350 mA (0.85V)

MCP GFX Core Power

140 mA

MCP 3.3V RGBDAC Power

If RGBDAC is used, requires ferrite (155S0382)

If RGBDAC is not used, tie to GND.

plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap.

160 mA

MCP 1.05V DisplayPort Power


2

1C2650

X5R6.3V

201

10%0.1UF

NO STUFF

2

1R2655

MF1/20W

201

1K1%

NO STUFF

2

1C2655

X5R6.3V

201

10%0.1UF

NO STUFF

2

1C264020%

4.7UF

402X5R-1

4V

2

1R2670

1/20W

05%

201MF

2

1C260020%

X5R

OMIT_TABLE

6.3V

10UF

603-12

1 C260120%4.7UF

402X5R-14V 2

1 C260220%

X5R6.3V

0201

1.0UF

2

1 C260320%

X5R

1.0UF6.3V

02012

1 C260420%

X5R201

6.3V

0.22UF

2

1 C260520%

X5R201

0.22UF6.3V 2

1 C2606

X5R6.3V

201

10%0.1UF

2

1 C2607

X5R

0.1UF6.3V

201

10%2

1 C2608

X5R6.3V

201

10%0.1UF

2

1 C2609

X5R6.3V

201

10%0.1UF

2

1 C2610

X5R6.3V

201

10%0.1UF

2

1 C2611

X5R6.3V

201

10%0.1UF

2

1 C2612

X5R6.3V

201

10%0.1UF

2

1 C2641

X5R6.3V

201

0.1UF10%

2

1R2650

MF201

1%1K1/20W


MCP Graphics SupportSYNC_MASTER=K16_MLB

=PP1V05_S0_MCP_PLL_IFP

=PP3V3R1V8_S0_MCP_IFP_VDD


MCP_IFPAB_RSETMCP_TMDS0_VPROBEMCP_TMDS0_RSET

MCP_IFPAB_VPROBE

MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=0V

GND_MCP_DAC_P3V3

MAKE_BASE=TRUE

PP3V3_S0_MCP_DAC

=PPVCORE_SW_MCP_GFX

26 OF 110

4.4.0

051-8379

24 OF 73

17

17

8 17

17 67

17 67

17 67

17 67

17

20 22

IN OUT

IN OUT

OUT

IN

OUT

IN

IN

IN

OUT

OUTIN

NCNC

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

B

Y

A




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

System Reset Circuit

PCIE Reset (Unbuffered)

LPC Reset (Unbuffered)

Platform Reset Connections

10K pull-up to 3.3V S0 inside MCP

MCP 25MHz Crystal

RTC Crystal

MCP S0 PWRGD & CPU_VLD

10 13 19

21

C2810

25VNP0-C0G201

12PF

5%

21

C2811

25VNP0-C0G201

12PF

5%

21

R2810

MF1/20W

201

0

5%

2

1R281110.0M

0201

1/20WMF

5%

NO STUFF

19 68

21

R2896

MF

1/20W

201

0

5%

XDP

21

R2883

MF1/20W

201

PLACEMENT_NOTE=Place close to U1400 5%

33

21

R2881

MF1/20W

201

PLACEMENT_NOTE=Place close to U1400 33

5%

2

1

R2897

OMIT

SILK_PART=SYS RST

5%

0

PLACEMENT_NOTE=Place R2897 on BOTTOM

MF-LF

1/16W

402

7 40

38

19

19

16

21

R2826

MF

1/20W

201

5%

33

PLACEMENT_NOTE=Place close to U1400

21

R2825

MF

1/20W

201

PLACEMENT_NOTE=Place close to U1400

5%

3319 68

21

C2815

25VNP0-C0G

201

12PF

5%

21

C2816

25V

NP0-C0G201

12PF

5%

31

42

Y281525.0000M

CRITICAL

SM-3.2X2.5MM

21

R2815

MF1/20W

201

0

5%

2

1R2816

MF1/20W

201

1M5%

NO STUFF

19

19

38 68 21

R2829

MF1/20W

201

22

5%PLACEMENT_NOTE=Place close to U1400

19 68

21

R2899

MF

1/20W

201

33

5%

2

1 C2899

6.3V

0201

1.0UF20%

X5R

NO STUFF

38

7 40 68

38 68

41

Y2810

CRITICAL

7X1.5X1.4-SM

32.768K

21

R2891

MF

1/20W

201

0

5%

33

21

R2893

MF1/20W

201

0

5%

63

34 21

R2894

MF1/20W

201

0

5%

53

38 49 57

2

1 C2850

10%

201X5R6.3V

0.1UF

19

5

4

1

2

3

U2850

74LVC1G08GWSOT353


SB Misc

=PP3V3_S5_MCPPWRGD

MCP_PS_PWRGD

RTC_CLK32K_XTALIN

RTC_CLK32K_XTALOUT_RRTC_CLK32K_XTALOUT

MCP_CLK25M_XTALOUT MCP_CLK25M_XTALOUT_R

PM_SYSRST_DEBOUNCE_L

LPCPLUS_RESET_LLPC_RESET_L

PM_CLK32K_SUSCLKPM_CLK32K_SUSCLK_R

XDP_DBRESET_L

SMC_LRESET_L

LPC_CLK33M_SMC_R LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

VR_PWRGOOD_DELAY

ALL_SYS_PWRGD

MCP_CLK25M_XTALIN

PCA9557D_RESET_L

BKLT_PLT_RST_L

PCIE_RESET_LMAKE_BASE=TRUE

AP_RESET_L

PM_SYSRST_L

28 OF 110

4.4.0

051-8379

25 OF 73

8

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NC

NCNC

NC NC

NC

NCNC

NC

NCNC

NC

A14/A15 FOR 2G/4G MONO ONLYCS1 IS FOR 2G DDP RANK CONTROL

H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3100OMIT_TABLE

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

MEM_A_ZQ0

FBGA

2

1C310220%0.47UF

201CERM-X5R-14V2

1C310120%

0.47UF201

CERM-X5R-1

4V

2

1C310020%0.47UF

201CERM-X5R-1

4V

21R3100201

240

1%MF 1/20W

2

1C311220%0.47UF

201CERM-X5R-14V2

1C311120%

0.47UF201

CERM-X5R-1

4V

2

1C311020%

0.47UF201

CERM-X5R-1

4V

21R31102011/20W

240

MF1%H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3110FBGA


MT41J128M8HX-187E OMIT_TABLE

2

1C312220%0.47UF

201CERM-X5R-14V2

1C312120%

0.47UF201

CERM-X5R-1

4V

2

1C312020%

0.47UF201

CERM-X5R-1

4V

21R31202011/20W

240

MF1%H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3120FBGA



2

1C313220%0.47UF

201CERM-X5R-14V2

1C313120%

0.47UF201

CERM-X5R-1

4V

2

1C313020%

0.47UF201

CERM-X5R-1

4V

21R3130201

240

1/20WMF1%H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3130FBGA



DDR3 DRAM Channel A (0-31)SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

MEM_A_CKE<1>

MEM_A_A<14>

MEM_A_ZQ0

MEM_A_ODT<1>


MEM_A_BA<0>

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_RESET_L

MEM_A_A<8>

MEM_A_A<4>



MEM_A_A<0>

PPVREF_S3_MEM_VREFDQ

PPVREF_S3_MEM_VREFCA

MEM_A_DM<0>

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQ<6>MEM_A_DQ<5>MEM_A_DQ<2>MEM_A_DQ<4>



MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

=PPLVDDR_S3_MEM_A

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_CLK_N<0>


MEM_A_A<11>

MEM_A_WE_L


MEM_A_ODT<0>

MEM_RESET_L



MEM_A_DQ<8>

MEM_A_A<4>

MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_A<11>


MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_WE_L

MEM_A_RAS_L

=PPLVDDR_S3_MEM_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_ZQ3



MEM_A_DQ<29>

MEM_A_DQS_N<3>

MEM_A_DM<3>



MEM_A_A<0>


MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<8>

MEM_RESET_L

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_BA<0>

MEM_A_A<9>

MEM_A_ODT<1>

MEM_A_ZQ3

MEM_A_A<11>


MEM_A_CLK_N<0>

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

=PPLVDDR_S3_MEM_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_ZQ2




MEM_A_DQS_P<2>

MEM_A_DQS_N<2>


MEM_A_A<0>



MEM_RESET_L

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_BA<0>


MEM_A_ZQ2

MEM_A_A<14>

MEM_A_CKE<1>

MEM_A_A<11>


MEM_A_CLK_N<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CAS_L

=PPLVDDR_S3_MEM_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_ZQ1


MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DM<1>

MEM_A_A<0>



MEM_A_A<4>

MEM_A_A<8>

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_BA<0>


MEM_A_CKE<1>

MEM_A_ZQ1

MEM_A_RAS_L

MEM_A_ODT<1>MEM_A_CLK_N<0>

MEM_A_A<14>

MEM_A_A<8>

MEM_A_A<10>


MEM_A_DM<2>

MEM_A_A<6>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_A<14>


MEM_A_CKE<1>

MEM_A_DQS_P<3>

MEM_A_DQ<24>

31 OF 110

4.4.0

051-8379

26 OF 73

15 21 26 27 32 66

15 26 27 32 66

26

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 21 26 27 32 66

15 26 27 32 66

15 26 27 28 29

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

26 27 28 29 33

26 27 28 29 33

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

26 27 28 29 33

15 26 27 32 66

15 26 27 28 29

26 27 28 29 33

26 27 28 29 33

15 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

26 27 28 29 33

26 27 28 29 33

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 28 29

15 26 27 32 66

15 21 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

26

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

26 27 28 29 33

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 28 29

15 26 27 32 66

15 21 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

26

15 26 27 32 66

15 21 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66 15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 21 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 21 26 27 32 66

26

15 26 27 32 66

15 26 27 32 66 15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 66

15 66

15 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32

66

15 66

15 66

15 21 26 27 32 66

15 66

15 66

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/APA11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/APA11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NCNC

NC

CS1 IS FOR 2G DDP RANK CONTROL

NC

NC

NC

NCNCNC

NCNC

NCNCNC

NC

NCNC

NCNCNC

NC

A14/A15 FOR 2G/4G MONO ONLY

NC

NCNC

NC NC

NCNC

2

1C3232

4VCERM-X5R-1201

0.47UF20%

2

1C3220

4V

CERM-X5R-1201

0.47UF20%

21R32301%MF 1/20W

240

201

H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3230OMIT_TABLE

MT41J128M8HX-187E


FBGA

21R32201%MF 1/20W

240

201

H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3220OMIT_TABLE


MT41J128M8HX-187E

FBGA

2

1C32124VCERM-X5R-1201

0.47UF20%

2

1C3211

4V

CERM-X5R-1201

0.47UF20%

2

1C3210

4V

CERM-X5R-1201

0.47UF20%2

1C3202

4VCERM-X5R-1201

0.47UF20%

2

1C3201

4V

CERM-X5R-1201

0.47UF20%

2

1C3200

4V

CERM-X5R-1201

0.47UF20%

2

1C3231

4V

CERM-X5R-1201

0.47UF20%

21R32101%MF 1/20W

240

201

H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3210OMIT_TABLE


FBGA

MT41J128M8HX-187E

21R32001%MF 1/20W

240

201

H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3200OMIT_TABLE

MT41J128M8HX-187E


FBGA

2

1C3230

4V

CERM-X5R-1201

0.47UF20%

2

1C3222

4VCERM-X5R-1201

0.47UF20%

2

1C3221

4V

CERM-X5R-1201

0.47UF20%



MEM_A_A<11>


MEM_A_CLK_N<0>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_ZQ9




MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DM<5>

MEM_A_A<0>



MEM_A_A<4>

MEM_A_A<8>

MEM_RESET_L

MEM_A_CKE<0>

MEM_A_BA<0>


MEM_A_ODT<1>

MEM_A_ZQ9

MEM_A_A<14>

MEM_A_CKE<1>

MEM_A_BA<2>

MEM_A_A<11>


MEM_A_CLK_N<0>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

=PPLVDDR_S3_MEM_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_ZQ8




MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DM<4>



MEM_A_A<0>



MEM_A_A<4>

MEM_A_A<8>

MEM_RESET_L

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_BA<0>


MEM_A_ODT<1>

MEM_A_ZQ8

MEM_A_A<14>

MEM_A_CKE<1>

MEM_A_A<11>


MEM_A_CLK_N<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_ZQ10




MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DM<6>


MEM_A_A<0>



MEM_A_A<4>

MEM_A_A<8>

MEM_RESET_L

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_BA<0>


MEM_A_ODT<1>

MEM_A_ZQ10

MEM_A_A<14>

MEM_A_CKE<1>

MEM_A_A<11>


MEM_A_CLK_N<0>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

=PPLVDDR_S3_MEM_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_ZQ11




MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_A_DM<7>

MEM_A_A<0>



MEM_A_A<4>

MEM_A_A<8>

MEM_RESET_L

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_BA<0>


MEM_A_ODT<1>

MEM_A_ZQ11

MEM_A_A<14>

MEM_A_CKE<1>


MEM_A_ODT<0>


=PPLVDDR_S3_MEM_A=PPLVDDR_S3_MEM_A


PPVREF_S3_MEM_VREFCAPPVREF_S3_MEM_VREFCA

32 OF 110

4.4.0

051-8379

27 OF 73

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 28 29

15 21 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

27

15 26 27 32 66

15 21 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

26 27 28 29 33

26 27 28 29 33

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 28 29

15 26 27 32 66

15 21 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

27

15 26 27 32 66

15 21 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

26 27 28 29 33

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 28 29

15 26 27 32 66

15 21 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

27

15 26 27 32 66

15 21 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 28 29

15 26 27 32 66

15 21 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

15 26 27 32 66

27

15 26 27 32 66

15 21 26 27 32 66

26 27 28 29 33

15 26 27 32 66

26 27 28 29 33

8 26 27 30

26 27 28 29 33

26 27 28 29 33 26 27 28 29 33

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NCNC

NC NC

NC

NC

CS1 IS FOR 2G DDP RANK CONTROLA14/A15 FOR 2G/4G MONO ONLY

NC

NC

NC NC

NCNC

H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3300

MT41J128M8HX-187E


MEM_B_ZQ0

FBGAOMIT_TABLE

2

1C33024VCERM-X5R-1201

0.47UF20%

2

1C3301

4V

CERM-X5R-1201

0.47UF20%

2

1C3300

4V

CERM-X5R-1201

0.47UF20%

21R33001/20WMF1%

240

201

2

1C3312

4VCERM-X5R-1201

0.47UF20%

2

1C3311

4V

CERM-X5R-1201

0.47UF20%

2

1C3310

4V

CERM-X5R-1201

0.47UF20%

21R33101%MF 1/20W

240

201

H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3310


MT41J128M8HX-187E

FBGAOMIT_TABLE

2

1C3322

4VCERM-X5R-1201

0.47UF20%

2

1C3321

4V

CERM-X5R-1201

0.47UF20%

2

1C3320

4V

CERM-X5R-1201

0.47UF20%

21R33201%MF 1/20W

240

201

H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3320


MT41J128M8HX-187E

FBGAOMIT_TABLE

2

1C3332

4VCERM-X5R-1201

0.47UF20%

2

1C3331

4V

CERM-X5R-1201

0.47UF20%

2

1C3330

4V

CERM-X5R-1201

0.47UF20%

21R33301%MF 1/20W

240

201

H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3330


MT41J128M8HX-187E

FBGAOMIT_TABLE





MEM_B_A<14>

MEM_B_ZQ0

MEM_B_ODT<1>


MEM_B_BA<0>

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_RESET_L

MEM_B_A<8>

MEM_B_A<4>



MEM_B_A<0>

MEM_B_DM<0>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>



MEM_B_A<5>

MEM_B_CLK_P<0>

MEM_B_BA<1>

=PPLVDDR_S3_MEM_B

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CLK_N<0>


MEM_B_A<11>

MEM_B_CKE<1>

MEM_B_A<14>

MEM_B_ZQ1

MEM_B_ODT<1>


MEM_B_BA<0>

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_RESET_L

MEM_B_A<8>

MEM_B_A<4>


MEM_B_A<2>

MEM_B_A<0>


MEM_B_DM<1>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQ<15>


MEM_B_DQ<8>


MEM_B_ZQ1

MEM_B_A<5>

MEM_B_CLK_P<0>

MEM_B_BA<1>

=PPLVDDR_S3_MEM_B

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_ODT<0>

MEM_B_CLK_N<0>


MEM_B_A<11>

MEM_B_CKE<1>

MEM_B_A<14>

MEM_B_ZQ2

MEM_B_ODT<1>


MEM_B_BA<0>

MEM_B_CKE<0>

MEM_RESET_L

MEM_B_A<8>

MEM_B_A<4>



MEM_B_A<0>



MEM_B_DM<2>

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>




MEM_B_ZQ2

MEM_B_A<3>

MEM_B_A<5>

MEM_B_CLK_P<0>

MEM_B_BA<1>

=PPLVDDR_S3_MEM_B

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_ODT<0>

MEM_B_CLK_N<0>


MEM_B_A<11>

MEM_B_CKE<1>

MEM_B_A<14>

MEM_B_ZQ3

MEM_B_ODT<1>


MEM_B_BA<0>

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_RESET_L

MEM_B_A<8>

MEM_B_A<4>





MEM_B_DM<3>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>




MEM_B_ZQ3

MEM_B_A<3>

MEM_B_A<5>

MEM_B_CLK_P<0>

MEM_B_BA<1>

=PPLVDDR_S3_MEM_B

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_ODT<0>

MEM_B_CLK_N<0>


MEM_B_A<11>

MEM_B_A<0>

MEM_B_CKE<1>

MEM_B_ODT<0>

MEM_B_A<3> MEM_B_DQ<3>

MEM_B_A<1>

MEM_B_DQ<7>

MEM_B_DQ<1>

MEM_B_DQ<0>MEM_B_A<3> MEM_B_DQ<12>

MEM_B_BA<2>


MEM_B_DQ<11>

33 OF 110

4.4.0

051-8379

28 OF 73

26 27 28 29 33

26 27 28 29 33

15 28 29 32 66

28

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

15 26 27 28 29

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

28

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

15 26 27 28 29

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

26 27 28 29 33

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

8 28 29 31

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

28

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 21 28 29 32 66

15 26 27 28 29

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

26 27 28 29 33

26 27 28 29 33

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

8 28 29 31

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32

66

28

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

15 26 27 28 29

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

26 27 28 29 33

26 27 28 29 33

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

8 28 29 31

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

15 28 29 32 66 15 66

15 28 29 32 66

15 66

15 66

15 66 15 28 29 32 66 15 66

15 28 29 32 66

26 27 28 29 33

15 66

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/APA11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/APA11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS VSSQ

WE*

CAS*

RAS*

VDDQVDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4

DQ5

DQ6

DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9

A10/AP




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NCNC

CS1 IS FOR 2G DDP RANK CONTROL

NC

NCNC

NCNC

A14/A15 FOR 2G/4G MONO ONLY

NCNC

NC NC

NC

2

1C343220%0.47UF

201CERM-X5R-14V2

1C342020%

0.47UF201

CERM-X5R-1

4V

21R3430201

240

1/20WMF1%H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3430OMIT_TABLE

MT41J128M8HX-187E


FBGA

21R3420201

240

1/20WMF1%H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3420OMIT_TABLE

MT41J128M8HX-187E


FBGA

2

1C341220%0.47UF

201CERM-X5R-14V2

1C341120%

0.47UF201

CERM-X5R-1

4V

2

1C341020%

0.47UF201

CERM-X5R-1

4V

2

1C340220%0.47UF

201CERM-X5R-14V2

1C340120%

0.47UF201

CERM-X5R-1

4V

2

1C340020%

0.47UF201

CERM-X5R-1

4V 2

1C343120%

0.47UF201

CERM-X5R-1

4V

21R3410201

240

1/20WMF1%H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3410OMIT_TABLE

FBGA

MT41J128M8HX-187E


21R3400201

240

1/20WMF1%H8

H3

D9D1C9B8B2

L9L1J9J1F8F2D8B1

N9N1

A8A1

E1

J8

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

A7

N2

F3

G1

H9

F1

H1

F9

N7J7

A3

D3

C3

E7D2E8E3C8C2C7B3

B7

H2

G9

G7F7

G3

J3K8J2

M3N8M2M8L2L8K2L3

N3K7M7H7

L7K3

U3400OMIT_TABLE

MT41J128M8HX-187E

FBGA


2

1C343020%

0.47UF201

CERM-X5R-1

4V

2

1C342220%0.47UF

201CERM-X5R-14V2

1C342120%

0.47UF201

CERM-X5R-1

4V

DDR3 DRAM Channel B (32-63)SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

MEM_B_A<11>


MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PPLVDDR_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ8




MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DM<4>



MEM_B_A<0>



MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>


MEM_B_ODT<1>

MEM_B_ZQ8

MEM_B_A<14>

MEM_B_CKE<1>


MEM_B_CAS_L

MEM_B_CLK_P<0>

MEM_B_A<11>


MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PPLVDDR_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ11

MEM_B_DQ<57>



MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DM<7>



MEM_B_A<0>



MEM_B_A<4>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<10>

MEM_B_ODT<1>

MEM_B_ZQ11

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_A<11>


MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_RAS_L

=PPLVDDR_S3_MEM_B

MEM_B_BA<1>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ10

MEM_B_DQ<53>

MEM_B_DQ<48>MEM_B_DQ<50>MEM_B_DQ<51>MEM_B_DQ<54>MEM_B_DQ<52>

MEM_B_DM<6>



MEM_B_A<0>



MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>


MEM_B_ZQ10

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_A<11>


MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CAS_L

=PPLVDDR_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ9




MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DM<5>


MEM_B_A<0>



MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>


MEM_B_ODT<1>

MEM_B_ZQ9

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_ODT<1>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQ<49>


MEM_B_DQ<61>

34 OF 110

4.4.0

051-8379

29 OF 73

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

26 27 28 29 33

26 27 28 29 33

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 26 27 28 29

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

29

15 28 29 32 66

15 21 28 29 32 66

26 27 28 29 33

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

8 28 29 31

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

26 27 28 29 33

26 27 28 29 33

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 26 27 28 29

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

29

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

26 27 28 29 33

26 27 28 29 33

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 26 27 28 29

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

29

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

8 28 29 31

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

15 66

26 27 28 29 33

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 26 27 28 29

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

29

15 28 29 32 66

15 21 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 28 29 32 66

15 66

15 66

15 66

15 66

15 28 29 32 66

15 28 29 32 66

15 66




36

BRANCH

REVISION

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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE 2 CAPS ALONG PACKAGE EDGE

2

1C3540

CERM402-LF

2.2UF6.3V20%

OMIT_TABLE

2

1C3541

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3542

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3550

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3551

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3530

402-LF

20%2.2UF6.3VCERM

OMIT_TABLE

2

1C3531

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3554

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3555

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3544

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3545

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3546

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3534

CERM20%2.2UF6.3V402-LF

OMIT_TABLE

2

1C3535

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3520

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3521

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3510

CERM20%6.3V402-LF

2.2UF

OMIT_TABLE

2

1C3511


OMIT_TABLE

2

1C3512

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3500

CERM20%6.3V402-LF

2.2UF

OMIT_TABLE

2

1C35012.2UFCERM402-LF

20%6.3V

OMIT_TABLE

2

1C3524

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3525

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3514

CERM20%

402-LF6.3V2.2UF

OMIT_TABLE

2

1C351520%CERM402-LF6.3V2.2UF

OMIT_TABLE

2

1C3516

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3504

CERM402-LF

20%6.3V2.2UF

OMIT_TABLE

2

1C3505

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

DDR BYPASSING 1SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

=PPLVDDR_S3_MEM_A =PPLVDDR_S3_MEM_A

35 OF 110

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8 26 27 30 8 26 27 30




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2 1


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PAGE


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345678

D

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8 7 5 4 2 1

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

2

1C3640

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3641

402-LF

20%6.3V2.2UFCERM

OMIT_TABLE

2

1C3642

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3650

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C36512.2UFCERM402-LF

20%6.3V

OMIT_TABLE

2

1C3630

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3631

CERM402-LF

20%6.3V2.2UF

OMIT_TABLE

2

1C3654

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3655

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3644

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3645

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3646

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3634


OMIT_TABLE

2

1C3635

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3620


OMIT_TABLE

2

1C3621

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3610

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C36116.3V402-LFCERM20%2.2UF

OMIT_TABLE

2

1C3612

CERM402-LF

20%6.3V2.2UF

OMIT_TABLE

C3600

402-LFCERM6.3V20%2.2UF

OMIT_TABLE

2

1C3601

CERM402-LF

2.2UF20%6.3V

OMIT_TABLE

2

1C362420%

402-LFCERM6.3V2.2UF

OMIT_TABLE

2

1C3625

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C36142.2UF20%CERM402-LF6.3V

OMIT_TABLE

2

1C3615

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3616

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3604

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE

2

1C3605

CERM402-LF

20%2.2UF6.3V

OMIT_TABLE


DDR BYPASSING 2

=PPLVDDR_S3_MEM_B =PPLVDDR_S3_MEM_B

36 OF 110

4.4.0

051-8379

31 OF 73

8 28 29 31 8 28 29 31

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN




36

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JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WEMEM CLOCK TERMINATIONPlace RC end termination after last DRAMPlace Source Cterm at neckdown at first DRAM

15 26 27 66

15 26 27 66

81RP37024X0201

361/32W5%72RP3702 36

4X02015%1/32W54RP37064X02011/32W5%

3663RP3702

4X02015%1/32W36

54RP37024X0201

365%1/32W

81RP37045%1/32W

364X0201

63RP3707 365%1/32W4X0201

72RP37034X02011/32W5%

3663RP3704

4X02015%1/32W36

54RP37035%1/32W4X0201

36

63RP37034X02015%1/32W

3681RP3703

4X02011/32W5%36

54RP37044X02011/32W5%

36

21R37901/20W5%

36201

72RP3706 365%1/32W4X020181RP37065%

364X02011/32W54RP3701

1/32W5% 4X020136

72RP37014X0201

365%1/32W

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

15 21 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

21

R37005%

1/20WMF

30

201

21

R3701

5%

30

MF1/20W201

21

C3700

0.1UFMEM_A_CLK_TERM_R

10%X5R6.3V201

21

C3702

6.3VX5R0.1UF10%201

21

R370430

MF1/20W5%

201

21

R3705305%MF

1/20W201

81RP37015%1/32W

364X020163RP3701

5%1/32W36

4X0201

72RP37075%1/32W

364X0201

72RP37044X02015%1/32W

3663RP3706

4X02015%1/32W36

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

15 26 27 66

63RP37151/32W5%

364X020154RP3715

5%36

4X02011/32W

72RP37151/32W5%

364X0201

81RP37111/32W5%

364X020181RP3709

1/32W5%36

4X0201

81RP37151/32W

365% 4X0201

63RP37104X02011/32W

365%

63RP37094X02011/32W5%

36

72RP37111/32W5%

364X0201

72RP37094X02015%1/32W

3681RP3708

5%1/32W36

4X0201

72RP37085%1/32W

364X0201

63RP37115%

361/32W4X0201

54RP37094X0201

365%1/32W

63RP37085%

361/32W4X020154RP3713

5%36

1/32W4X0201

54RP37105%

361/32W4X0201

72RP37105%1/32W

364X0201

81RP37105%1/32W

364X0201

54RP37081/32W

364X02015%

63RP37135%1/32W

364X0201

72RP37141/32W5% 4X0201

3681RP3714

1/32W5% 4X020136

54RP37141/32W5%

364X0201

63RP37141/32W5%

364X0201

72RP37131/32W5%

364X0201

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 21 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 28 29 66

15 21 28 29 66

15 28 29 66

15 28 29 66

2

1C3704

CERM25V5%

3.3PF

201

2

1C37063.3PF

5%25VCERM201

2

1C37104VCERM-X5R-1201

0.47UF20%

2

1C37134VCERM-X5R-1201

0.47UF20%

2

1C37124VCERM-X5R-1201

0.47UF20%

2

1C37154VCERM-X5R-1201

0.47UF20%

2

1C37144VCERM-X5R-1201

0.47UF20%

2

1C37174VCERM-X5R-1201

0.47UF20%

2

1C37164VCERM-X5R-1201

0.47UF20%

2

1C37184VCERM-X5R-1201

0.47UF20%

2

1C37204VCERM-X5R-1201

0.47UF20%

2

1C37224VCERM-X5R-1201

0.47UF20%

2

1C37244VCERM-X5R-1201

0.47UF20%

2

1C37274VCERM-X5R-1201

0.47UF20%

2

1C37264VCERM-X5R-1201

0.47UF20%

2

1C37294VCERM-X5R-1201

0.47UF20%

2

1C37284VCERM-X5R-1201

0.47UF20%

2

1C37304VCERM-X5R-1201

0.47UF20%

2

1C37334VCERM-X5R-1201

0.47UF20%

2

1C37324VCERM-X5R-1201

0.47UF20%

81RP37075%

364X02011/32W

15 26 27 66

21R37915%

361/20W 201

21R37935%

361/20W 201

21R37921/20W

365% 201

81RP3713 361/32W5% 4X0201

15 21 26 27 66


Memory Active Termination

MEM_A_CLK_N<0>

MEM_A_A<3>

MEM_A_BA<0>MEM_B_CLK_P<0>

=PPDDRVTT_S0_MEM_B

=PPDDRVTT_S0_MEM_A

MEM_A_BA<1>

MEM_A_A<0>

MEM_A_CKE<1>

MEM_A_ODT<1>MEM_A_ODT<0>

MEM_A_A<2>


MEM_A_A<6>VOLTAGE=0V

MEM_B_CLK_TERM_RVOLTAGE=0V

MEM_A_A<9>

MEM_A_CS_L<0>

MEM_A_CKE<0>MEM_A_A<1>

MEM_A_A<4>


MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_A_CLK_P<0>

MEM_A_WE_L

MEM_A_BA<2>

MEM_B_A<8>MEM_B_CAS_L

MEM_A_RAS_LMEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_A<7>

MEM_A_A<14>

MEM_A_A<8>

MEM_A_A<12>

MEM_B_A<0>

MEM_B_A<4>

MEM_B_A<10>


MEM_B_WE_L

MEM_B_A<14>

MEM_B_A<1>

MEM_B_BA<0>

MEM_B_ODT<1>

MEM_B_CKE<1>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_BA<1>MEM_B_A<13>

MEM_B_A<3>

MEM_B_A<12>

MEM_B_A<2>MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_A<7>

MEM_B_RAS_LMEM_B_BA<2>

MEM_B_ODT<0>

37 OF 110

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051-8379

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15 26 27 66

15 28 29 66

8

8

15 28 29 66

15 26 27 66

OUT

OUT

V-

V+

V-

V+

V-

V+

V-

V+

IN

NC

NC

NC

RESET*

A0

A1

A2

SCL

SDA

P0

P1

P2

P5

P6

P7

P3

P4

THRM

VCC

GNDPAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTASCL

SDA

A0

A1

GND

IN

BI




36

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8 7 5 4 2 1


(OD)

RST* on ’platform reset’ so that system

NOTE: Must not enable more than two SO-DIMM margining buffers at once or VRef source may be overloaded.

VREFMRGN:YES - Stuffs VREF MarginingBOM options provided by this page:

Addr=0x30(WR)/0x31(RD)

Addr=0x98(WR)/0x99(RD)

VREFMRGN:NO - Bypasses VREF Margining

+750uA - -528uA (- = sourced) +33uA - -33uA (- = sourced)

D

1.5V (DAC: 0x3A)

0.000V - 1.501V (0x00 - 0x74)1.998V - 1.002V (+/- 498mV)

8.59mV / step @ output

MEM VREG

5DDAC Channel:

PCA9557D Pin:

DAC range:

Nominal value

DAC step size:VRef current:

Margined target:

1A

0.000V - 1.501V (0x00 - 0x74)

C3

- =PP3V3_S3_VREFMRGN

- =I2C_VREFDACS_SCL- =I2C_VREFDACS_SDA- =I2C_PCA9557D_SCL- =I2C_PCA9557D_SDA

Circuitry.

Circuitry.

- =PPVTT_S3_DDR_BUF

Page NotesPower aliases required by this page:

Signal aliases required by this page:

10mA max load

7

CPU GTLREF (FSB)

0.7V (DAC: 0x8B)0.200V - 1.050V (+/- 500mV)0.000V - 1.191V (0x00 - 0x5C)

9.24mV / step @ output

0.75V (DAC: 0x3A)0.300V - 1.200V (+/- 450mV)

+3.4mA - -3.4mA (- = sourced) 7.69mV / step @ output

both at the same time!

(RSVD for FBVREF)

a DAC output, cannot enableNOTE: MEMVREG and FRAMEBUF share

MEM VREF DQ MEM VREF CA

Required zero ohm resistors when no VREF margining circuit stuffed

soft-resets and sleep/wake cycles.NOTE: Margining will be disabled across all

watchdog will disable margining.

52

2

1C3910

201

10%

X5R6.3V

0.1UF

VREFMRGN:YES

21

R394222.6K

1% PLACE_NEAR=R7320.2:1mm

VREFMRGN:YES

MF1/20W

201

2

1R3940VREFMRGN:YES

100K

201

1/20WMF

5%

2

1R3945

201

1/20WMF

VREFMRGN:YES

5%100K

10 65 21

R3944

1% PLACE_NEAR=R1005.2:1mm

267

VREFMRGN:YES

MF1/20W

201

B4

B1

C4

C1

C2

C3

U3920

VREFMRGN:YES

UCSPMAX4253

CRITICAL

B4

B1

A4

A1

A2

A3

U3920UCSPMAX4253

VREFMRGN:YES

CRITICAL

B4

B1

A4

A1

A2

A3

U3940

VREFMRGN:YES

MAX4253UCSP

CRITICAL

B4

B1

C4

C1

C2

C3

U3940

VREFMRGN:YES

MAX4253UCSP

CRITICAL

21

R3900

NONE

OMIT

SHORT

402

NONENONE

21

R3910OMIT

NONE

SHORT

NONE402

NONE

25

21

R3921PLACE_NEAR=U3230.E1.1:2.54MM

201

1/20WMF

VREFMRGN:YES

1%

200

21

R3922

PLACE_NEAR=R3921.2:1MM

201

1/20WMF

VREFMRGN:YES

133

1%

21

R3923PLACE_NEAR=U3230.J8:2.54MM

VREFMRGN:YES

1/20WMF

1%

200

201

21

R3924

PLACE_NEAR=R3923.2:1MM

201

1/20WMF

1%

133

VREFMRGN:YES

2

1R3925100K

201

1/20WMF

VREFMRGN:YES

5%

21

R3920

MF

100K1/20W5%

201

VREFMRGN:YES

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U3910QFN

PCA9557

VREFMRGN:YESCRITICAL

41

41

5

4

2

1

8

7

6

3

10

9

U3900

CRITICAL

MSOP

DAC5574

VREFMRGN:YES

41

41

2

1 C390110%

201X5R6.3V

VREFMRGN:YES

0.1UF

2

1C3900VREFMRGN:YES

2.2UF

CERM402-LF

20%6.3V

2

1C394010%

201X5R

6.3V

VREFMRGN:YES

0.1UF

2

1C39200.1UF

VREFMRGN:YES

6.3VX5R201

10%

RES,MF,1/20W,0.0 OHM,5,0201,SMD117S0002 2 VREFMRGN:NOR3921,R3923


FSB/DDR3 Vref Margining

=PP3V3_S3_VREFMRGN


PPVREF_S3_MEM_VREFCAMIN_LINE_WIDTH=0.3 mm

VOLTAGE=0.75V

=PPVTT_S3_DDR_BUF

VREFMRGN_CA_BUF

=I2C_VREFDACS_SCL

VREFMRGN_CA_DRAM

VREFMRGN_DQ_DRAM

PP3V3_S3_VREFMRGN_DACMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

VREFMRGN_DQ_DRAM_EN

VREFMRGN_DQ_BUF

=I2C_PCA9557D_SCL=I2C_PCA9557D_SDA

VREFMRGN_CPUGTLREF_BUF

DDRREG_FB

CPU_GTLREF

MIN_LINE_WIDTH=0.3 mmPPVREF_S3_MEM_VREFDQ

VOLTAGE=0.75VMIN_NECK_WIDTH=0.2 mm

=I2C_VREFDACS_SDA

MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PP3V3_S3_VREFMRGN_CTRLMIN_LINE_WIDTH=0.3 mm

VREFMRGN_MEMVREG_BUF

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_MEMVREG_EN

PCA9557D_RESET_L

VREFMRGN_CPUGTLREF_EN

VREFMRGN_CA_DRAM_EN

39 OF 110

4.4.0

051-8379

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8

26 27 28 29

8 52

26 27 28 29

OUT

IN

IN

IN

IN

IN

BI

BI

OUT

OUT

OUT

OUT

SG

D

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE +-

PAD

(OD)

0.7V

DLYOUT

IN

IN

OUT




36

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PAGE TITLE

C

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Apple Inc.

PAGE


A

B

C

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D

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8 7 5 4 2 1

DLY = 60 MS +/- 20%

514S0335

CHANNEL

0.750 A (EDP)

P-TYPE

3V S3 WLAN FET

TPCP8102

20-30 MOHM @2.5V

MOSFET

LOADING

RDS(ON)

AIRPORT

BLUETOOTH

7 16

57

21

C4030

0.1UFX5R201

PLACEMENT_NOTE=Place close to J4001.

10% 6.3V

16 67

16 67

21C4031

0.1UF

PLACEMENT_NOTE=Place close to J4001.

6.3V10% 201X5R

7 16 67

7 16 67

2

1C40216.3V10%

201X5R

0.1UF

PLACEMENT_NOTE=Place close to Q4050.

7 18 68

7 18 68

2

1C402010V20%

805X5R

10UF

PLACEMENT_NOTE=Place close to Q4050.

7 16 67

7 16 67

4321

R40521%

CRITICAL

0.25W0.020

805MF-LF

42 71

42 71

32

1

4

87

65

Q4050CRITICAL

23V1K-SMTPCP8102

1

9

2

4

8

3

7

5

6

U4002TDFN

SLG4AP016V

CRITICAL 2

1C4053

2016.3V10%X5R

0.1UF

16

25

19 57 2

1R40535%

201MF

100K1/20W

2

1R40551/20W

1%

201MF

100K

2

1R40541/20W

1%

201MF

232K

2

1C4032

PLACE_NEAR=J4001.27:1.5mm

0.1UFX5R201

10%6.3V

98765432

181716151413

121110

1

212019

J4001SSD-K99CRITICAL

F-RT-SM1

7 38 39

21

C4050

10%16V402X5R

0.1UF2

1C405116V10%

402

0.033UFX5R

21R4050

1/20W5%

201MF

100K2

1R40515%1/20W201MF

10K


X21 WIRELESS CONNECTOR

=PP3V3_S3_WLAN

PCIE_AP_D2R_N

WIFI_EVENT_L

VOLTAGE=3.3V

MIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.25 mm

PP3V3_WLAN_R

ISNS_AIRPORT_N

PCIE_CLK100M_AP_NPCIE_CLK100M_AP_P

=PP3V3_S3_BT

PCIE_AP_D2R_P

PCIE_WAKE_L

AP_RESET_CONN_L

PCIE_AP_R2D_P PCIE_AP_R2D_C_P

ISNS_AIRPORT_P

PM_WLAN_EN_LP3V3WLAN_SS

AP_CLKREQ_L

AP_RESET_L

P3V3WLAN_VMONAP_PWR_EN

VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1 mm

PP3V3_WLAN_F

=PP3V3_S3_WLAN

AP_CLKREQ_Q_L

USB_BT_NUSB_BT_P

PCIE_AP_R2D_N PCIE_AP_R2D_C_N

40 OF 110

4.4.0

051-8379

34 OF 73

7 8

7

7 67

7 39

8 34

7

7 67

OUT

OUT

NCNC

OUT

OUT

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

SATA SSD4 32 1

R4599

0612MF1W

0.0031%

CRITICAL

42 71

42 71

98765432

181716151413

121110

1

212019

J4501CRITICAL

SSD-K99F-RT-SM1

21

R4510

201

5%

MF

0

1/20W

21

R4511

201

0

1/20WMF

5%

2

1C45010.1UF20%CERM10V

PLACE_NEAR=J4501.1:1.5mm402

18 67

18 67

18 67

18 67

21C4516X5R10V10% 2010.01UF

PLACE_NEAR=J4501.3:1.5MM

21C4510


10V 20110% X5R0.01UF

21C4511PLACE_NEAR=J4501.7:1.5MM

20110V10% X5R0.01UF

21C4515PLACE_NEAR=J4501.4:1.5MM

10V10% 201X5R0.01UF


SATA CONNECTORSYNC_MASTER=K16_MLB

ISNS_HDD_NISNS_HDD_P

=PP3V3_S0_HDD

TP_SSD_RSRVD

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

SMC_HDD_OOB_TEMP

SMC_HDD_TEMP_CTL_CONN

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

SATA_HDD_R2D_N

SMC_HDD_TEMP_CTL

SATA_HDD_D2R_N

SATA_HDD_D2R_P

SMC_HDD_OOB_TEMP_CONN

SATA_HDD_R2D_P

MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mmVOLTAGE=5V

PP3V3_S0_HDD_R

45 OF 110

4.4.0

051-8379

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

35 OF 73

7 38

7 67

7 67

7 67

7 38

7 67

OUT1

GND TPAD

OUT2

OC1*

IN

EN1

EN2

OC2*

BI

BI

SYM_VER-1

IN

OUT

IN

OUT

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

IO

IO

NC

GND

VBUS

NC

IN

VBUS

D-

D+

GND




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Right USB Port

SEL=1 Choose USBSEL=0 Choose SMC

(USB_EXTA_MUXED_N)(USB_EXTA_MUXED_P)

514-0740

D4600.5D4600.4

USB/SMC Debug Mux

Port Power Switch

9

6

7

5

8

2

1

4

3

U4690

MSOP

CRITICAL

TPS2052B21

L4605CRITICAL

0603

FERR-220-OHM-2.5A

PLACE_NEAR=J4600.1:3 mm

2

1 C4695OMIT_TABLE

10UF

603

6.3VX5R

20%2

1 C469120%

CERM10V

402

0.1UF

18 68

18 68

2

1C46500.1UF

SMC_DEBUG:YES

10%6.3VX5R201 2

1R465010K5%

201

1/20WMF

4 3

21

L4600DLP11S

90-OHM-100MA

CRITICAL

PLACE_NEAR=D4600.3:2 mm

PLACE_NEAR=D4600.2:2 mm

7 38 39 40

7 38 39 40

38

21

R4651

5%

SMC_DEBUG:NO

0

201

1/20WMF

21

R4652

MF1/20W

201

SMC_DEBUG:NO

0

5%

2

1C46050.01uF

CERM402

20%16V

18

2

1C4690OMIT_TABLE

6.3V20%

603X5R

10UF

1

2

9

108

5

4

37

6

U4650

SMC_DEBUG:YES

TQFNPI3USB102ZLE

CRITICAL

SIGNAL_MODEL=USB_MUX

6

4 5

1

D4600RCLAMP0502N

PLACE_NEAR=J4600.2:2 mmCRITICAL

SLP1210N6PLACE_NEAR=J4600.3:2 mm

7 37 57

2

1C4696

6.3VPOLY-TANT

20%100UF

CASE-B2-SM

CRITICAL

1

6

5

4

3

2

J4600CRITICAL

F-RT-THUSB-RIGHT-K99

SYNC_MASTER=K16_MLB

External USB ConnectorsSYNC_DATE=07/07/2010

=PP5V_S3_RTUSB

=USB_PWR_ENUSB_EXTA_OC_L VOLTAGE=5V


PP5V_S3_RTUSB_A_ILIM

USB_EXTA_MUXED_N

=PP3V42_G3H_SMCUSBMUX

MIN_LINE_WIDTH=0.5 mmPP5V_S3_RTUSB_A_F

VOLTAGE=5VMIN_NECK_WIDTH=0.375 mm

USB_LT1_P

USB_LT1_N

USB_EXTA_NUSB_EXTA_P

USB_EXTA_MUXED_P

USB_DEBUGPRT_EN_L

SMC_RX_LSMC_TX_L

46 OF 110

4.4.0

051-8379

36 OF 73

23

8

68 71

8

7

71

71

68 71




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

516S0862

LIO CONNECTOR

2

1C4720

10%

0.1UF

6.3V

X5RPLACE_NEAR=J4700.32:1.5mm

201

2

1C4710

10%0.1UF

201

X5R6.3V


2

1C4700

10%

0.1UF

201X5R

6.3VPLACE_NEAR=J4700.20:1.5mm

9

87

65

4

38

37

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J4700AXK736327G

F-ST-SM

SYNC_MASTER=N/A SYNC_DATE=N/A

LIO CONNECTORS

=PP1V8R1V5_S0_AUDIO

=PP3V42_G3H_ONEWIRE

SYS_ONEWIRE

SMC_BC_ACOK

=USB_PWR_EN

USB_EXTD_OC_L

=PP3V3_S0_AUDIOUSB_CAMERA_N

USB_CAMERA_P

USB_EXTD_N

USB_EXTD_P

AUD_GPIO_3

=I2C_LIO_SDA

HDA_SYNC

HDA_RST_L

HDA_SDIN0

HDA_BIT_CLK

SPKRAMP_INR_N

SPKRAMP_INR_P

AUD_IPHS_SWITCH_EN

AUD_IP_PERIPHERAL_DET

AUD_I2C_INT_L

=I2C_LIO_SCL

=I2C_MIKEY_SDA

=I2C_MIKEY_SCL

HDA_SDOUT

47 OF 110

4.4.0

051-8379

37 OF 73

7 8

7 8

7 38

7 9 38 39

7 36 57

7 18

7 8 7 18 68

7 18 68

7 18 68

7 18 68

7 48

7 41

7 19 68

7 19 68

7 19 68

7 19 68

7 48 71

7 48 71

7 19

7 17

7 19

7 41

7 41

7 41

7 19 68

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

OUT

BI

IN

IN

OUT

BI

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

BI

BI

BI

BI

BI

BI

OUT

OUT

IN

IN

OUT

ININ

BI

BI

OUT

IN

OUT

OUT

NC

OUT

OUT

OUTNC

NCNCNC

NC

NC

NCNC

NCNCNC

NC

NC

NC

NC

NCNC

NCNC

NC

NCNC

IN

OUT

OUT

P13

P14

P15

P16 P66

P10

P11

P12

P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P36

P37

P40

P41

P42

P43

P44

P45

P46

P47

P50

P51

P52

P60

P61

P62

P63

P64

P65

P67

P70

P71

P72

P73

P74

P75

P76

P77

P80

P81

P84

P85

P86

P90

P91

P92

P93

P94

P95

P96

P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0

PA1

PA2

PA3

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE0

PE1

PE2

PE3

PE4

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PH0

PH1

PH2

PH3

PH4

PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREFAVCC

EXTAL

XTAL

(3 OF 3)

IN

NC

IN

OUT

IN

BI

OUT

BI

BI

BI

BI

IN

IN

IN

OUT

BI

IN

IN

IN

BI

BI

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(DEBUG_SW_2)(DEBUG_SW_1)

If SMS interrupt is not used, pull up to SMC rail.NOTE: SMS Interrupt can be active high or low, rename net accordingly.

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

(OC)

(OC)(OC)

(OC)

(OC)

(OC)

(OC)

H8S2117-R:

(EXCARD_OC_L)

(EXCARD_CP)

(OC)(OC)

(OC)(OC)

(OC)

(SMC_PECI_VREF)(SMC_PECI)

(SMC_PECI_VSTP)

(OC)

(OC)

(EXCARD_PWR_EN)

(OC)(OC)

2

1C490220%

22UF

603

6.3V

OMIT_TABLE

X5R-CERM-1

7 19 40

7 39 40 50

7 39 46

2

1C4907

BYPASS=U4900.E1:D2:5 mm

4VCERM-X5R-1

201

0.47UF20%

2

1 C4903

10V

0.1UF

CERM

20%

402

2

1C4920

10V

402

20%

BYPASS=U4900.M12:L9:5 mm

CERM

0.1UF

21

R4999

MF1/20W5%

4.7PLACE_NEAR=C4920.1:2 mm

201

2

1 C49040.1UF10V20%

CERM402

2 1

XW4900SM

19

53

2

1 C4905

10V

0.1UF

CERM

20%

402

19

57

25 49 57

39

2

1 C4906

CERM10V

402

0.1UF20%

43

42

39

39

43

42

43

39

39 46

7 9 37 39

7 36 38 39 40

7 36 38 39 40

7 57

41

2

1R4909

MF

5%10K

1/20W

201

7 40

7 40

2

1R4901

MF1/20W5%10K

201

2

1R4902

MF1/20W

10K5%

201 2

1R4903

1/20WMF

5%0

NO STUFF

2012

1R4998

MF1/20W5%10K

201

36

7 37

19

39

19

45

39

39

39

39

39

39

45

39

39

39

39

39

39 42

39

7 39 40

39

7 39 40

7 39 40

7 39 40

7 39 46 49

41

41

41

41

41

41

39

39

39

7 36 38 39 40

7 36 38 39 40

39 39

7 19 40

19

25

7 40

19

7 19 40

39

39

19 39 57

39

39

39

F1

F4

G4

H4

G1

H2

G3

J4

C6

B5

A6

D5

C7

B6

A7

L12

N13

M13

N12

N11

L10

M11

N10

H12

J11

J10

K13

J12

K11

K12

L13

E4

F3

G2

C3

C1

B2

C2

A1

B4

A5

D4

D6

D7

D8

A8

B7

C8

D9

A9

E10

F13

E12

E13

F11

D12

E11

D13

D10

C12

C13

D11

B13

A12

A13

B12U4900LGA-HF

H8S2117

OMIT_TABLE

C4

B3

A4

J2

F2

E2

L6

M7

N6

K6

K7

K8

N7

M8

M4

L4

N4

M5

L5

M6

N5

K5

K4

J1

K2

J3

K1

L7

K9

N8

M9

L8

K10

N9

M10

J13

H11

G12

G10

H13

F12

G13

G11

A11

C11

B10

C10

A10

B9

C9

B8

L2

K3

L1

N2

M2

M3

N1

N3U4900LGA-HF

OMIT_TABLE

H8S2117

A3

C5

B11

F10

L3

D2

E1

H10

M1

B1

D3

E3

H1

D1

A2

H3

L9

L11

M12

U4900LGA-HF

H8S2117

OMIT_TABLE

39

7 19 57

7 35

7 35

7 34 39

39

7 19 40 68

7 19 40 68

7 19 40 68

7 19 40 68

7 19 40 68

25

25 68

39

41

7 19 39 57

19

25 68

41

41

39


SMC

LPC_PWRDWN_L

SMC_RSTGATE_LSMC_P10

LPC_AD<0>

SMC_LRESET_L

SMC_HDD_TEMP_CTL

SMB_0_S0_DATA

PM_SLP_S5_L

SMC_PME_S4_LSMC_BC_ACOKSMC_ONOFF_L

PM_SLP_S3_L

SMC_TDO

SMB_BSA_DATA=SMC_SMS_INT

SMC_LID

SMC_TMS

PM_CLK32K_SUSCLK

SMC_TDI

SMC_G3H_POWERON_LWIFI_EVENT_L

USB_DEBUGPRT_EN_L

SMC_CASE_OPEN

SMC_SLPS5_LSMC_ODD_DETECTSMC_RUNTIME_SCI_L

SMC_DP_HPD_L

PM_SLP_S4_L

SMC_PA1PM_SYSRST_L

SYS_ONEWIRE

SMC_FAN_0_CTLSMC_FAN_1_CTLSMC_FAN_2_CTLSMC_FAN_3_CTLSMC_FAN_0_TACHSMC_FAN_1_TACHSMC_FAN_2_TACHSMC_FAN_3_TACH

SMS_X_AXISSMS_Y_AXISSMS_Z_AXISSMC_ANALOG_IDSMC_NB_CORE_ISENSESMC_NB_DDR_ISENSESMC_ADC14SMC_ADC15

SMC_SYS_LED

SMC_MCP_SAFE_MODE

SMB_BSA_CLKSMB_A_S3_DATA

SMB_B_S0_DATASMB_B_S0_CLK

SMC_PROCHOTSMC_THRMTRIP

SMC_PH3


PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V


SMC_XTAL

SMC_TRST_L

SMC_MD1SMC_KBC_MDE

SMC_NMI

SMC_VCL

GND_SMC_AVSS

SMC_EXTAL

SMC_RESET_L

PM_CLKRUN_L

SMB_MGMT_CLKSMC_RX_LSMC_TX_L

SMC_NB_MISC_ISENSESMC_BATT_ISENSESMC_PBUS_VSENSESMC_DCIN_ISENSESMC_GPU_VSENSESMC_GPU_ISENSESMC_CPU_VSENSESMC_CPU_ISENSE

SMC_BIL_BUTTON_L

SMC_ADAPTER_EN

SMC_PM_G2_EN

SMC_RX_L

SMC_SYS_KBDLEDSMC_GFX_THROTTLE_L

SMB_MGMT_DATA

LPC_SERIRQLPC_CLK33M_SMC

LPC_FRAME_LLPC_AD<3>LPC_AD<2>LPC_AD<1>

SMC_BMON_MUX_SEL

SMC_P24

SMC_P20

PM_PWRBTN_LSMC_PROCHOT_3_3_LIMVP_VR_ON

PM_RSMRST_L

RSMRST_PWRGD

SMC_TCK

SMC_HDD_OOB_TEMP

SMS_ONOFF_L

SMC_PA0

PM_BATLOW_L

SMB_A_S3_CLK

SMB_0_S0_CLK

SMC_GFX_OVERTEMP_L

SMC_PB4

SMC_WAKE_SCI_L

SMC_TX_L

MEM_EVENT_L

ALL_SYS_PWRGD

=PP3V3_S5_SMCPP3V3_S5_AVREF_SMC

49 OF 110

4.4.0

051-8379

38 OF 73

E5

39

39

39

39

39

39 42 43

39

43

39

39

39

39

8 39

39

D

S G

IN

OUT

BI

IN

D

S G

IN

IN

IN

IN

IN OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

E

Q2

C

BD

Q1

GS

OUT

G

D

S

OUT

IN

REFOUT

MR1*

THRMGND

RESET*

DELAY

MR2*

VINV+

SN0903048

PAD

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

IN

INOUT

IN

OUT

IN

OUT IN

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

SMC Pull-downs

System (Sleep) LED Circuit

Debug Power "Buttons"

SMC Pull-ups

NOTE: Internal pull-ups are to VIN, not V+.

PLACEMENT_NOTEs:

Used on mobiles to support SMC reset via keyboard.

(IPU)

(IPU)

SMC Reset "Button", Supervisor & AVREF Supply

Desktops: 5VMobiles: 3.42V

SMC Crystal Circuit

MR1* and MR2* must both be low to cause manual reset.

SMC FSB to 3.3V Level Shifting

TO SMC

TO CPU

SMC Aliases

Unused Pins

4 5

3 Q5059SOT563SSM6N37FEAPE

21R5070 10K1/20W MF 2015%21R5071

5%100K

1/20W MF 20121R5073 10KMF 2015% 1/20W21R5074MF5%

100K1/20W 201

21R5076201

100K5% 1/20W MF

21R5077 10K1/20W5% MF 20121R5078 10K

MF1/20W5% 20121R5079 10KMF1/20W5% 20121R5080 10KMF1/20W5% 201

21R5085201

10KMF1/20W5%21R5086

1/20W10K

201MF5%

21R5088 10K5% 1/20W MF 201

21R5090DP_PWR:S0

5% 201100K

1/20W MF

38

10 14 65

21

R5062

5%

3.3K

201

1/20WMF

10 14 65

38

1 2

6 Q5059SOT563SSM6N37FEAPE

21R5091 100K5% 1/20W 201MF21R5092 100K5% 1/20W 201MF

21R5089NO STUFF

5%10K

201MF1/20W

21R5081 10KMF1/20W5% 201

21

R5010

5%

201MF

1/20W

0

2

1Y50105X3.2-SM

20.00MHZ

CRITICAL

21

C5011

5%

15PF

201NPO25V

21

C5010

5%

15PF

NPO25V

201

21R5087MF1/20W5%

470K201

21R50935% 2011/20W MF

10K

38

38

38

38

38 19

38

38

38

38

38 42

38

38

38

38

21

R5096

1/20W

201

5%

0

MF

38 19

38

38

38

38

21R5094 10K5% 1/20W MF 201

38

38

38

2

1R5032SIL

1.47K1%

1/16WMF-LF

402

2

1R5031SIL

5231%

1/16WMF-LF

402 2

1R5030SIL

40.21%1/16WMF-LF402

1 2

46

3

5

Q5030SIL

DMB54D0UVSOT-563

49

4

3

5 Q5060DMB53D0UVSOT-563

2

1R5061

201MF1/20W5%100K

1

2

6

Q5060SOT-563DMB53D0UV

2

1R5060

201MF1/20W5%10K

38

19

31

9

5

8

7

6

2

4

U5010VREF-3.3V-VDET-3.0V

DFN7 46

7 38 39 46

2

1R50005%1K1/20W

201MF

2

1 C502610%

201X5R10V

0.01UF

2

1C5025

6.3V20%

603X5R

10uF

OMIT_TABLE

2

1C5001

201

10V

0.01UF10%

X5R

7 38 40 50

2

1C50200.47UF

6.3V10%

402CERM-X5R

38 39

38

2

1R5015

Place R5015 on BOTTOM side

SILK_PART=PWR_BTN

OMIT

05%1/10WMF-LF6032

1R5014

Place R5014 on TOP side

SILK_PART=PWR_BTN

OMIT

05%

1/10WMF-LF

603

2

1R5001

PLACEMENT_NOTE=Place R5001 on BOTTOM side

SILK_PART=SMC_RST

OMIT

5%01/10W

603MF-LF

38

38

38

38

21R50405%

10K1/20W MF 201

38 39

21

R5020DP_PWR:S0

MF1/20W

201

0

5%7 19 38 57

61

21

R5021DP_PWR:SMC

MF1/20W

201

0

5%38

21

R5022

5%

0

201

1/20WMF

DP_PWR:SMC

PLACE_NEAR=Q9441.2:5 mm38 39 61

12R5098 100K5% 1/20W MF 201

7 38 39 46

SMC SupportSYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

SMC_GFX_OVERTEMP_L

SMC_SLPS5_L

SMC_ADC15

SMS_X_AXIS

SMC_DP_HPD_L

PM_SLP_S3_L

DP_EXT_HPD_L

SMS_Y_AXIS

SMS_Z_AXIS

SMC_ADC14

SMC_NB_CORE_ISENSE

SMC_NB_DDR_ISENSE

SMC_NB_MISC_ISENSE

SMC_ANALOG_ID

SMC_GPU_ISENSE

SMC_GPU_VSENSE

SMC_IG_THROTTLE_LMAKE_BASE=TRUE

=SMC_SMS_INT

MAKE_BASE=TRUESMC_G3H_POWERON_L

MCP_SPKR

SMC_LCDBKLT_ISENSEMAKE_BASE=TRUESMC_WLAN_ISENSEMAKE_BASE=TRUESMC_HDD_ISENSEMAKE_BASE=TRUESMC_CSREG_ISENSEMAKE_BASE=TRUESMC_LCDBKLT_VSENSEMAKE_BASE=TRUESMC_MCP_CORE_ISENSEMAKE_BASE=TRUESMC_MCP_DDR_ISENSEMAKE_BASE=TRUESMC_1V5S3_ISENSEMAKE_BASE=TRUETP_SMC_ANALOG_IDMAKE_BASE=TRUETP_SMC_GPU_ISENSEMAKE_BASE=TRUESMC_MCP_VSENSEMAKE_BASE=TRUE

SMC_GFX_THROTTLE_L

MCP_WAKE_REQ_L

SMS_INT_LMAKE_BASE=TRUE

SMC_MCP_SAFE_MODE

SMC_PH3

SMC_P24

SMC_P10

SMC_P20

SMC_RSTGATE_L

SMC_FAN_3_CTL

SMC_FAN_2_CTL

MAKE_BASE=TRUETP_SMC_PH3MAKE_BASE=TRUETP_SMC_P24

TP_SMC_P20MAKE_BASE=TRUE

MAKE_BASE=TRUETP_SMC_P10

NO_TEST=TRUENC_SMC_FAN_3_TACHMAKE_BASE=TRUE

SMC_FAN_3_TACHMAKE_BASE=TRUE NO_TEST=TRUENC_SMC_FAN_3_CTL

NO_TEST=TRUENC_SMC_FAN_2_TACHMAKE_BASE=TRUE

SMC_FAN_2_TACH

TP_SMC_FAN_1_TACHMAKE_BASE=TRUE

SMC_FAN_1_TACH

NO_TEST=TRUEMAKE_BASE=TRUENC_SMC_FAN_2_CTL

SMC_FAN_1_CTL

SMC_SYS_KBDLED

SMS_ONOFF_L

TP_SMC_FAN_1_CTLMAKE_BASE=TRUE

MAKE_BASE=TRUETP_SMC_SYS_KBDLED

MAKE_BASE=TRUETP_SMS_ONOFF_L

SMC_THRMTRIP

SMC_PROCHOT

CPU_PROCHOT_BUF

CPU_PROCHOT_L_RCPU_PROCHOT_L

PM_THRMTRIP_L

SMC_PROCHOT_3_3_L

=PP3V3_S0_SMC

SMC_EXTAL

SMC_TPAD_RST_LSMC_ONOFF_L

=PP3V3_S5_SMC=PPVIN_S5_SMCVREF

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mmGND_SMC_AVSSMIN_NECK_WIDTH=0.1 mm

SMC_ONOFF_L

PP3V3_S5_AVREF_SMCMIN_NECK_WIDTH=0.1 mmVOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mmSMC_MANUAL_RST_L

SMC_RESET_L

SYS_LED_ANODESMC_SYS_LED

SYS_LED_ILIM

=PP5V_S3_SYSLED

SYS_LED_L_VDIV

SYS_LED_L

SMC_PA0

SMS_INT_L=DP_PWR_ENMAKE_BASE=TRUEDP_PWR_EN

SMC_XTAL_RSMC_XTAL

SMC_PA1

SMC_BC_ACOK

SMC_G3H_POWERON_L

SMC_DP_HPD_L

SMC_PB4

=PP3V3_S5_SMC

SMC_LID

SMC_BIL_BUTTON_L

SMC_CASE_OPENSMC_ADAPTER_EN

MAKE_BASE=TRUETP_SMC_RSTGATE_L

SMC_ONOFF_L

SMC_TX_LSMC_RX_L

SMC_TMSSMC_TDOSMC_TDI

SMC_ODD_DETECT

SMC_TCK

PP3V3_WLAN_F

WIFI_EVENT_L

=PP3V3_SMC_PME

SMC_PME_S4_L

50 OF 110

4.4.0

051-8379

39 OF 73

38

42

42

42

43

43

43

42

42

8

38

8 38 39

8

38 42 43

38

8

38

39

38

38

7 9 37 38

38 39

38 39

38

8 38 39

7 38 46 49

38

38

19 38 57

7 38 39 46

7 36 38 40

7 36 38 40

7 38 40

7 38 40

7 38 40

38

7 38 40

7 34

7 34 38

8

38 46

OUTIN

E0/NC0

SCL

SDAE2

E1

WC*

VCC

VSS

IN

BI

NC

BI

OUT

OUT

OUT

IN

IN

IN

OUTIN

OUTIN

IN

BI

BI

BI

OUT

BI

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

INOUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

LPC+SPI Connector

516S0573

SPI Bus Series Termination

Read: 0xAD/0xAFWrite: 0xAC/0xAE

EFI Debug ROM

2

1R5126475%

LPCPLUS

201

1/20WMF

47 68 21

R512247

5%

201

1/20WMF

21

R511215

5%

201

1/20WMF

19 68

2

1R512747

LPCPLUS

5%

201

1/20WMF

2

1R512805%

LPCPLUS

201

1/20WMF

7

4

8

5

6

3

2

U5101M24M01-R

CRITICAL

SO8N

EFI_DEBUG

2

1R5101EFI_DEBUG

5%0

1/20WMF201

2

1R5104NO STUFF

05%1/20WMF2012

1R5102NO STUFF

5%0

1/20WMF201

2

1R5103EFI_DEBUG

05%1/20WMF201

2

1C5101

402

0.1UF

CERM10V20%

EFI_DEBUG

41

41

9

87

65

4

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J510055909-0374

M-ST-SM

CRITICALLPCPLUS

7 19 38 68

7 38 39

7 38 39

7 38

7 25

7 36 38 39

7 38

47 68 21

R5110

5%

15

201

1/20WMF

19 68

47 68 21

R5111

5%

15

201

1/20WMF

19 68

7 25 68

7 19 38 68

7 19 38 68

7 19 38 68

7 19 47

7 19 38

7 19 38

7 38 39

7 38 39 50

7 38

7 38 39

7 36 38 39

7 19

7 19 38

7 19 38 68

47 68 21

R5123

5%

15

201

1/20WMF

19 68

21

R512047

5%

201

1/20WMF

2

1R5125475%

LPCPLUS

201

1/20WMF

21

R512147

5%

201

1/20WMF


LPC+SPI Debug Connector

SPI_CS0_R_L

SPI_MLB_MISO

=PP3V3_S0_DEBUGROM

DEBUGROM_E1DEBUGROM_E2

SPI_MOSI

SPI_MISO

SPI_CLK_R

=I2C_DEBUGROM_SDA

=I2C_DEBUGROM_SCL

SPI_MOSI_R SPI_MLB_MOSI

SPI_MLB_CLKSPI_CLK

SPI_MLB_CS_LSPI_CS0_L

SPI_ALT_MISOSPI_ALT_MOSISPI_ALT_CLKSPI_ALT_CS_L

LPCPLUS_GPIOSMC_RX_LSMC_NMISMC_RESET_LSMC_TCKSMC_TDILPC_PWRDWN_LLPC_SERIRQSPI_ALT_CS_LSPI_ALT_CLKSPIROM_USE_MLB

LPC_AD<3>LPC_AD<2>LPC_CLK33M_LPCPLUS

=PP5V_S0_LPCPLUS=PP3V3_S5_LPCPLUS

SPI_ALT_MISOSPI_ALT_MOSI

LPC_AD<0>LPC_AD<1>

LPC_FRAME_L

SMC_TMSPM_CLKRUN_L

SMC_TDOLPCPLUS_RESET_L

SMC_TRST_LSMC_MD1SMC_TX_L

51 OF 110

4.4.0

051-8379

40 OF 73

1

8

68

68

68

7 40 68

7 40 68

7 40 68

7 40 68

7 40 68

7 40 68

7 8

7 8

7 40 68

7 40 68




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

U1400(MASTER)

Internal DP

(MASTER)U4900

SMC "Management" SMBus Connections(* = Multiple options)

Samsung LGD Samsung LGD AUO

Battery Manager - (Write: 0x16 Read: 0x17)

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

J9000

K16 K99

MCP89 SMBus 1 is slave port to

(Write: 0xE0 Read: 0xE1)

access internal thermal diodes.

Another slave port is availableat 0x10/0x11, probably not used.

U1400MCP89

MCP89 SMBus "1" Connections

U4900SMC

(MASTER)

Left I/O BoardALS - N/A (Feature Removed)Finstack Temp - (Write: 0x98 Read: 0x99)

U4900SMC

(MASTER)

CPU TempEMC1413: U5515

J4700(See Table)

Left I/O Board

Internal DP

(Write: 0x58 Read: 0x59)

Margin Control

(See Table)J1300

Vref DACsU3900

EFI Debug Serial

(Write: 0x30 Read: 0x31)U3910

U5101(Write: 0xAC/0xAE Read: 0xAD/0xAF)


MikeyJ4700 (LIO Connector)

SMC(MASTER)

SMC

Battery

Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x90 Read: 0x91)

(See Table)J6950

(Write: 0x12 Read: 0x13)ISL6259 - U7000

J5700

U4900

The bus formerly known as "Battery B"

Battery

(MASTER)U4900SMC

Trackpad

SMC "Battery A" SMBus Connections

Battery Charger


(MASTER)


MCP89 SMBus "0" Connections SMC "0" SMBus Connections

U9701LP8545 (Bklt)MCP89

NOTE: SMC RMT bus remains powered and may be active in S3 state

EMC1413: U5535

XDP Connector

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

SMC "A" SMBus Connections

SMC "B" SMBus Connections


MCP Temp(Write: 0xD8 Read: 0xD9)

2

1R52801%

2.61K1/20W

MF201 2

1R52811%2.61K1/20WMF201

2

1R5261

201

1/20WMF

4.7K5%

2

1R52604.7K

5%

201

1/20WMF

2

1R5271

201

1/20W

1K5%

MF2

1R52701K5%

1/20WMF201

2

1R5251NO STUFF

1/20W5%

MF

2.0K

2012

1R5250NO STUFF

5%1/20W

MF

2.0K

201

2

1R52315%2.0K

NO STUFF

1/20WMF2012

1R5230NO STUFF

5%2.0K1/20W

MF201

2

1R52005%1K

201

1/20WMF

2

1R52011K5%

201

1/20WMF

2

1R52365%01/20WMF2012

1R52355%0

1/20WMF201

2

1R52912.0K

201

5%1/20WMF

2

1R5290

MF

5%

201

1/20W

2.0K

2

1R524305%

201

1/20WMF

DPI2C:SMC

2

1R524205%

201

1/20WMF

DPI2C:SMC

12

R5241DPI2C:MCP

0

1/20WMF

5%

201

12

R5240DPI2C:MCP

201

1/20W

0

MF

5%


K16/K99 SMus Connections

=I2C_MCPTHMSNS_SCL

MAKE_BASE=TRUESMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUESMBUS_SMC_A_S3_SCL

SMBUS_MCP_0_DATAMAKE_BASE=TRUE

MAKE_BASE=TRUESMBUS_SMC_B_S0_SCL

=I2C_MIKEY_SCL

MAKE_BASE=TRUESMBUS_MCP_0_CLK

=I2C_MCPTHMSNS_SDA

=PP3V3_S0_SMBUS_SMC_0_S0

=I2C_TPAD_SDA

=SMBUS_BATT_SDA

SMB_BSA_DATA

SMBUS_SMC_BSA_SCLMAKE_BASE=TRUE

=SMBUS_CHGR_SDA

=PP3V42_G3H_SMBUS_SMC_BSA

MAKE_BASE=TRUESMBUS_SMC_MGMT_SCL

SMB_MGMT_DATA

=SMBUS_CHGR_SCL

=SMBUS_BATT_SCL

SMBUS_SMC_BSA_SDAMAKE_BASE=TRUE

SMB_BSA_CLK

=I2C_TCON_SDA

=I2C_TCON_SCL

SMB_0_S0_CLK

SMB_0_S0_DATA=I2C_BKL_1_SDA

SMB_MGMT_CLK

=I2C_TPAD_SCL

MAKE_BASE=TRUESMBUS_SMC_MGMT_SDA

=I2C_MIKEY_SDA

=I2C_PCA9557D_SCL

=I2C_DEBUGROM_SCL

=I2C_DEBUGROM_SDA

=I2C_VREFDACS_SDA

=I2C_VREFDACS_SCL

=I2C_XDP_SCL

=I2C_XDP_SDAMAKE_BASE=TRUEI2C_TCON_SCL

=I2C_PCA9557D_SDA

=PP3V3_S0_SMBUS_MCP_0

=I2C_BKL_1_SCL

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S0_SMBUS_SMC_B_S0=PP3V3_S0_SMBUS_MCP_1

MAKE_BASE=TRUESMBUS_MCP_1_CLK

SMBUS_MCP_1_DATAMAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDAMAKE_BASE=TRUE

=I2C_LIO_SCL

=I2C_LIO_SDA

SMB_A_S3_CLK

SMB_A_S3_DATA

=I2C_CPUTHMSNS_SDA

=I2C_CPUTHMSNS_SCLSMB_B_S0_CLK

SMB_B_S0_DATA

MAKE_BASE=TRUEI2C_TCON_SDA

=PP3V3_S5_SMBUS_SMC_MGMT

MAKE_BASE=TRUESMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCLMAKE_BASE=TRUE

52 OF 110

4.4.0

051-8379

41 OF 73

44

70

70

19 68

70

7 37

19 68

44

8

7 46

49

38

7 70

50

8

70

38

50

49

7 70

38

7 59

7 59

38

38 62

38

7 46

70

7 37

33

40

40

33

33

13

13

71

33

8

62

8

8 8

19 68

19 68

70

7 37

7 37

38

38

44

44 38

38

71

8

70

70

OUT

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

OUT

OUT

OUT

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(CLIPS AT 6.6A)

(CLIPS AT 0.825A)

DDR3 1V5R1V35 Current Sense / Filter

Max Vdiff: 24.0 mV

PLACEMENT_NOTEs:

Gain: 200x

Place RC close to SMC


(For R and C)

(For R and C)

Max Vdiff: 14.6 mV

WF: Verify SSD current!

EDP Current: ??? AMax Vdiff: ??? mV

WF: Verify LCD backlight current!

PLACEMENT_NOTEs:

(200V/V)

CPU Voltage Sense / Filter

(For R and C)

PLACEMENT_NOTEs:

GAIN: 500XSCALE: 0.667A / VMAX VOUT: 3.54V

MAX VOUT: 3VScale: 0.25A / V

EDP Current: 1.2 A?

(500V/V)

PLACEMENT_NOTEs:

(500V/V)

MAX VOUT: 3.33VSCALE: 0.2A / V

GAIN: 500X

LCD Backlight Driver Input Current Sense / Filter

(CLIPS AT 0.66A)

(CLIPS AT 2.2A)

DIVIDER: 1/22


RTHEVENIN = 4573 Ohms

divider when high.Enables PBUS VSense

EDP Current: 0.727 A?

WF: Verify Airport current!

PBUS Voltage Sense Enable & Filter

MCP Voltage Sense / Filter

HDD Current Sense / Filter

(500V/V)GAIN: 200XSCALE: 0.4A / VMAX VOUT: 3.5V

(For R and C)

AirPort Current Sense / Filter

WF: Verify SO-DIMM current!Max Vdiff: 13.0 mVEDP Current: 7 A

39

2

1 C53590.22UF

X5R6.3V20%

201

21

R5359

MF201

1%

4.53K

1/20W

57

2

1R5316

MF1/20W

201

1%100K

2

1R5315

MF1/20W

201

1%100K

38

2

1 C53150.22UF

201

20%6.3VX5R

2

1R531727.4K

1%

201

1/20WMF

2

1R53185.49K

1%

201

1/20WMF

4

1

5

2

3

6

Q5315NTUD3169CZ

SOT-963

39

39

39

39

21

R53654.53K

1%

Place close to SMC

1/20WMF201

2

1 C536520%6.3V

0.22UF

Place close to SMC

X5R201

2

1 C53600.1UF10%

X5R6.3V

201

3

1

6

4

5

2

U5360INA210

SC70

2

1 C5375

Place close to SMC

0.22UF

X5R

20%6.3V

201

2

1 C5385

Place close to SMC

6.3V20%

X5R201

0.22UF

3

1

6

4

5

2

U5370SC70

INA210

3

1

6

4

5

2

U5380SC70

INA211

2

1 C5395

Place close to SMC

0.22UF

X5R

20%6.3V

201

3

1

6

4

5

2

U5390SC70

INA211

2

1 C5370

6.3VX5R

0.1UF10%

201

2

1 C53800.1UF

201

6.3V10%

X5R

2

1 C539010%0.1UF

X5R6.3V

201

21

R53754.53K

201MF

1/20W1%

Place close to SMC

21

R53854.53K

1%

Place close to SMC

1/20WMF201

21

R5395

201MF

1/20W1%

4.53K

52 71

52 71

34 71

34 71

35 71

35 71

62 71

62 71

21

XW5310SM

PLACE_NEAR=D9701.2:5 MM

2

1R53191%

1/20W

201

1M

MF

2

1R5320

MF1/20W

1%

201

47K

21

R5321 PLACE_NEAR=U4900:5 MM

1/20W1%

MF201

226K

2

1 C5310OMIT_TABLEPLACE_NEAR=U4900:5 MM

0402

20%6.3VX5R

2.2UF

38 39

21

XW5359SM

PLACE_NEAR=R7525.2:5 MM

38 21

R5309

201

1/20W1%

MF

4.53K

2

1 C5309

6.3V

201

20%

X5R

0.22UF

21

XW5309

PLACE_NEAR=L7400.2:5 MM

SM

SYNC_MASTER=K16_MLB

Voltage & Current SensingSYNC_DATE=07/07/2010

MCPVSENSE_IN

PBUS_G3H_VSENSE

PBUSVSENS_EN_L_DIV

=PBUSVSENS_EN

PBUSVSENS_EN_L

PPBUS_G3H

GND_SMC_AVSS

SMC_PBUS_VSENSE

LCDBKLT_VSEN

LCDBKLT_VSEN_DIV SMC_ADC15

PPVOUT_SW_LCDBKLT

=PP3V3_S0_BKLTISNS

ISNS_LCDBKLT_N

=PP3V3_S0_HDDISNS

ISNS_P5VHDD_IOUTISNS_HDD_N

GND_SMC_AVSS

SMC_WLAN_ISENSE

GND_SMC_AVSS

ISNS_P5VWLAN_IOUT

=PP3V3_S3_WLANISNS

ISNS_1V5S3_IOUT

GND_SMC_AVSS

GND_SMC_AVSS

SMC_1V5S3_ISENSE

CPUVSENSE_IN

GND_SMC_AVSS

GND_SMC_AVSS

PPVCORE_S0_MCP

PPVCORE_S0_CPUSMC_CPU_VSENSE

SMC_MCP_VSENSE

ISNS_1V5_S3_N

ISNS_1V5_S3_P

ISNS_AIRPORT_N

ISNS_AIRPORT_P

ISNS_LCDBKLT_P

SMC_HDD_ISENSE

ISNS_HDD_P

ISNS_LCDBKLT_IOUT SMC_LCDBKLT_ISENSE

=PP3V3_S3_1V5S3ISNS

53 OF 110

4.4.0

051-8379

42 OF 73

7 8 49

38 39 42 43

7 59 62

8

8

38 39 42 43

38 39 42 43

8

38 39 42 43

38 39 42 43

38 39 42 43

38 39 42 43

7 8

7 8

8

V+

REFIN+

IN- OUT

GND

OUT

OUT

IN

OUT

IN OUT

VER 1

VCC

A

1

0

B1

GND

B0

SELIN

IN

IN

IN

OUTIN

OUTIN-

IN+ REF

V+

GND

IN

IN

OUT

IN

IN

OUTIN-

IN+ REF

V+

GND

+IN

-IN

V+

V-




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(200V/V)

R5431:

MAX VOUT: 3.352V

MCP VCore Current Sense Filter

SCALE: 2.5A / V

MAX VOUT: 3.00V

Charger/Load side

Battery side

NOTE: Monitoring current from battery to PBUS (battery

From chargerSense R: R7050Value: 10 mOhmMax Vdiff: 80mV

PLACEMENT_NOTEs:

(100V/V)

(Sense R "output")

Max Vdiff = 24.8mV

Gain: 100xScale: 10A / V

R7593 at the same time!

(For R and C)

(For R and C)

Max VOut: 2.88V

Sense R is R7525, 1mOhm

(Sense R "input")MAX VOUT: 2.38V

MCP MEM VDD Current Sense / Filter

Sense R: R7020Value: 20 mOhm

ISL6259 Gain: 20x

MAX VOUT: 1.24V

discharge) across R7050

(100V/V)

NOTE: Do not stuff R5415 and

(For R’s and C)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

DCIN (AMON) Current Sense, RMUX & Filter

(For Rs and C)

CPU VCore Load Side Current Sense / Filter

For production, stuff BMON:PRODFor engineering, stuff BMON:ENG

INA213 Gain: 50x

Chipset Regulators High-Side Current Sense / Filter

ISL6259 Gain: 36x

Battery (BMON) Current Sense, MUX & Filter

PLACEMENT_NOTEs:

(For R and C)

SCALE: 1A / V

From charger

GAIN: 100X

(CLIPS AT 3.3A)

Gain: 36xScale: 2.778A / V

GAIN: 200X

PLACEMENT_NOTEs:

VERIFY ALL RESISTOR AND GAINS

2

1 C5417

201

0.1UF6.3V10%

X5R

3

1

6

4

5

2

U5402SC70

INA21039

2

1 C543620%0.22UF

Place close to SMC

6.3V

402X5R

38

2

1 C5418

6.3V

BMON:ENG

0.1UF

201X5R

10%

50 21

R5431

PLACE_NEAR=U5413:2 mm

5%

BMON:PROD

201

1/20W

0

MF

2

1R5423

1/20W5%

BMON:ENG

100K

MF201

2

1C545910%

6.3V

BMON:ENG

0.1UF

X5R201

38

53

2

1R5480NOSTUFF

Place close to SMC402

MF-LF1/16W

1%17.4K

21

R5471

MF-LF

15.0K

1%1/16W

402

Place close to SMC

38

2

1 C548710%0.0068UF

CERM25V

402

Place close to SMC

5

6

2

1

3 4

U5413

CRITICAL

NC7SB3157P6XGSC70

BMON:ENG

38

50 70

50 70

4

3

2

1R5492CRITICAL

0612

0.0021%

MF1W

50

2

1R5482

MF-LF

1%

NOSTUFF

Place close to SMC

402

1/16W

133K

39 21

R5416

MF

4.53K

1%

201

1/20W

Place close to SMC

2

1 C5472

6.3VX5R

0.22UF

Place close to SMC

20%

201

54

21

R5415

5%

0

1/20WMF201

2

1 C54200.1UF6.3VX5R

10%

201

3

1

6

4

5

2

U5420SC70

INA2149

9

2

1R5411

201

1/20W5%0

MF

39

2

1 C5435

Place close to SMC 402

6.3V20%

X5R

0.22UF

2

1C5400

201X5R

6.3V10%

0.1UF

2

1R5410

201

1/20W5%0

MF

21

21

2

1 C54340.1UF6.3VX5R

10%

NOSTUFF

201

21

R5417

1/16W1%

402MF-LF

4.53K

Place close to SMC

2

3

1

Q5401CRITICAL

2SA2154MFV-YAESOD

2

1R5412118

1/16W1%

402MF-LF

21

R5418

201

1%

4.53K

Place close to SMC

1/20WMF

3

1

6

4

5

2

U5403INA214

SC70BMON:ENG

PLACEMENT_NOTE=Place near sense resistor

5

2

14

3

U5400SC70-5OPA330

2

1 C5470

402

0.068UF10%10VCERM

21

R5481

201

150K

1%1/20WMF

21

R5401300K

201

1%1/20WMF

2

1 C5490

402

0.0033UF10%50VCERM


Current Sensing

GND_SMC_AVSS

CSREG_IOUT

BMON_INA_OUT SMC_BMON_MUX_SEL

=PP3V42_G3H_BMON_ISNS

GND_SMC_AVSS

SMC_BATT_ISENSEBMON_AMUX_OUT

CHGR_AMON

GND_SMC_AVSS

SMC_DCIN_ISENSE

MCPDDRFET_KELVIN

MCPDDR_SENSE_B

SMC_CPU_ISENSE

SMC_CSREG_ISENSEISNS_CSREG_N

=PP3V3_S0_CSREGISNS

GND_SMC_AVSS

IMVP6_PMON

MCPDDRFET_SENSE

=PP3V3_S0_MCPDDRISNS

MCPDDR_SENSE_C

CHGR_CSO_R_N

=PPBUS_G3H_R_OUTISNS_CSREG_P

SMC_MCP_DDR_ISENSE

GND_SMC_AVSS

MCPCORE_IOUT=MCPCOREISNS_N

=MCPCOREISNS_P

GND_SMC_AVSS

SMC_MCP_CORE_ISENSE

CHGR_CSO_R_P

MCPDDR_SENSE_E

MCPDDR_SENSE_AMP

=PPBUS_G3H_R_IN

CHGR_BMON

=PP3V3_S0_MCPCOREISNS MCPCORES0_IMON

54 OF 110

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051-8379

43 OF 73

38 39 42 43

8

38 39 42 43

38 39 42 43

71

8

38 39 42 43

8

8

71

38 39 42 43

38 39 42 43

8

8

BI

BI

BI

BI

BI

BI

THRM_PADDN2/DP3

DP2/DN3

VDD

SMDATA

SMCLKGND

DN1

DP1 THERM*/ADDR

ALERT*

THRM_PADDN2/DP3

DP2/DN3

VDD

SMDATA

SMCLKGND

DN1

DP1 THERM*/ADDR

ALERT*

BI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Addr: 0xD8(Wr)/0xD9(Rd)

MCP Thermal Diode

Local sensor for MCP Proximity

MCP T-Diode Thermal Sensor

FIXME: OFFGRID

CPU T-Diode Thermal Sensor

Addr: 0x98(Wr)/0x99(Rd)

Local sensor for CPU Proximity

CPU Thermal Diode

DRAM/SSD Temperature

2

1 C551510%0.1UF

201X5R6.3V

41

41

2

1 C553510%6.3VX5R201

0.1UF

2

3

1Q5501

PLACEMENT_NOTE=Place Q5501 near DRAMs below MCP

CRITICAL

SOT732-3BC846BMXXH

21

R551547

5%

201

1/20WMF

21

R5535

5%

47

201MF

1/20W

2

1C5522

201

2.2NF

X5R10V10%

19 71

19 71

2

1C5521

201X5R10V

2.2NF10%

10 71

10 71

U5535

PLACEMENT_NOTE=Place U5535 near MCP

CRITICAL

DFNEMC1413

1

11

7

9

10

6

4

2

5

3 8

U5515EMC1413

PLACEMENT_NOTE=Place U5515 near CPU

CRITICAL

DFN 2

1R551710K5%

201

1/20WMF

2

1R551610K1%

201

1/20WMF

2

1R5536

201

15K

MF1/20W

1%

2

1R553710K5%

201

1/20WMF

2

1C5520

201

10%2.2NF

10VX5R

41

41

2

3

1Q5535

PLACEMENT_NOTE=Place Q5535 near J9000

CRITICAL

SOT732-3BC846BMXXH 2

1C55232.2NF

10%10VX5R201

Thermal SensorsSYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

=I2C_MCPTHMSNS_SCL

=I2C_MCPTHMSNS_SDA

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

CPU_THERMD_N

CPUTHMSNS_THERM_L

CPUTHMSNS_ALERT_L

DRAMTHMSNS_D2_P

=PP3V3_S0_CPUTHMSNS

DRAMTHMSNS_D2_N

CPU_THERMD_P

PP3V3_S0_CPUTHMSNS_RMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=3.3V

MCPTHMSNS_ALERT_L

MCPTHMSNS_THERM_L

MCP_THMDIODE_P

MLBR_THMDIODE_P

MLBR_THMDIODE_N

PP3V3_S0_MCPTHMSNS_R

VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm

=PP3V3_S0_MCPTHMSNS

MCP_THMDIODE_N

55 OF 110

4.4.0

051-8379

44 OF 73

8

71

71

71

8

D

GS




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NC

FAN CONNECTOR

518S0793

GNDMOTOR CONTROLTACH5V DC

NC

21R566547K

201MF1/20W5%

2

1R5660

201

47K1/20W

5%MF

2

1R5661100K

MF1/20W

5%

201

21

3

Q5660SOD-VESM-HFSSM3K15FV

4321

6

5

J5600FF14A-4C-R11DL-B-3H

F-RT-SM

CRITICAL


Fan

=PP3V3_S0_FAN

SMC_FAN_0_TACH

SMC_FAN_0_CTL

FAN_RT_TACH

FAN_RT_PWM

=PP5V_S0_FAN

56 OF 110

4.4.0

051-8379

45 OF 73

8

38

38

7

7

8

BI

BI

OUT

IN

OUT

SYM_VER-1

BI

BI

BI

BI

BI

BI

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

518S0794

IPD Flex Connector

2

1C5710


0.1uF20%

CERM10V

402

2

1C57200.1UF

X5R6.3V

201

10%


7 41 46

98765432

1413121110

1

16

15

J5700FF14A-14C-R11DL-B-3H

F-RT-SM

CRITICAL

2

1C57000.1UF

201

10%

X5R6.3V


7 41 46

7 38 39 46

7 38 39 46 49

7 39 46

2

1C5732

X7R-CERM

PLACE_NEAR=J5700.8:1.5MM201

100PF10%25V

2

1C5733

PLACE_NEAR=J5700.9:1.5mm201

100PF

25VX7R-CERM

10%

2

1C5734

PLACE_NEAR=J5700.11:1.5MM201X7R-CERM

100PF

25V10%

2

1C5735

10%

PLACE_NEAR=J5700.12:1.5MM201X7R-CERM

25V

100PF

2

1C5736

PLACE_NEAR=J5700.14:1.5MM201

100PF

25VX7R-CERM

10%

4 3

21

L5710DLP0NS90-OHM

18 68 71

18 68 71

7 46 71

7 46 71

21

L5720

0402-LFPLACE_NEAR=J5700.10:1.5MM

FERR-120-OHM-1.5A

21

R57300

5% MF-LF1/16W402

IPD_3V3:S5

21

R5731

MF-LF402

1/16W

0

5%

IPD_3V3:S3

7 46 71

7 46 71

38 39


WELLSPRING 1

=I2C_TPAD_SCL

USB_TPAD_CONN_P

SMC_LID

PP5V_S5_LDO

USB_TPAD_N

=I2C_TPAD_SDA

=PP3V3_S5_TPAD

=PP3V42_G3H_TPAD

USB_TPAD_P

USB_TPAD_CONN_N

=I2C_TPAD_SDA

SMC_LID

SMC_ONOFF_L

SMC_TPAD_RST_L

=I2C_TPAD_SCL

USB_TPAD_CONN_P

=PP3V3_S3_TPAD

SMC_TPAD_RST_L

PP5V_TPAD_FILTVOLTAGE=5V MIN_NECK_WIDTH=0.20mm MIN_LINE_WIDTH=0.5 mm

USB_TPAD_CONN_N

SMC_ONOFF_L

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mmPP3V3_TPAD_CONN

VOLTAGE=3.3V

SMC_PME_S4_L

57 OF 110

4.4.0

051-8379

46 OF 73

56

8

7 8

7 41 46

7 38 39 46 49

7 38 39 46

7 39 46

7 41 46

8

7

7

OUTIN

IN IN

IN

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1




36

BRANCH

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Frequency

0

0

1

1

SPI_MOSI SPI_CLK

0

1

0

1

MCP89 SPI Frequency Select

62.5 MHz

41.7 MHz

25.0 MHz

31.2 MHz

NOTE: 42 & 62 MHz use FAST_READ command.

ROM will ignore SPI cycles.NOTE: If HOLD* is asserted

2

1C61000.1UF

10%

201X5R

6.3V

2

1R61013.3K5%

201

1/20WMF

40 68 40 68

40 68 40 68

7 19 40

3

8

2

56

7

4

1

U610032MBIT

MX25L3205DM2I-12G

SOP

CRITICAL

OMIT_TABLE

2

1R61515%10K

SPI:41MHZ&SPI:62MHZ

201

1/20WMF

2

1R61535%10K

SPI:25MHZ&SPI:31MHZ

201

1/20WMF

2

1R615210K

5%

SPI:25MHZ&SPI:41MHZ

201

1/20WMF

2

1R615010K

5%

SPI:31MHZ&SPI:62MHZ

201

1/20WMF

SPI ROMSYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

=PP3V3_S5_ROM

SPI_MLB_MOSISPI_MLB_CLK

SPI_WP_LSPI_MLB_MISO

SPI_MLB_CS_L

SPIROM_USE_MLB

61 OF 110

4.4.0

051-8379

47 OF 73

8

IN

IN

IN

IN-

IN+ OUT+

OUT-

GAINSHDN*

PVDD

NC

PGND




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

APN:353S2888

80 HZ < FC < 132 HZ

GAIN

SPEAKER LOWPASS

SPEAKER AMPLIFIERS

6DB

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM

21

C66100.1UF

CRITICAL

6.3V10%

201X5R

7 37 71

2

1C66070.1UF

201

6.3V10%

X5R2

1C6601CRITICAL

6.3V20%

2012-LLPPOLY-TANT

47UF

21

R6610

1/20W5%

201MF

07 37

7 37 71

C2

A1

A2

B1

C1

A3

B3

C3

U6610MAX98300

WLP

2

1R6612NOSTUFF

1/20W5%

201MF

100K

21

C6611CRITICAL

0.1UF

X5R201

10%6.3V

2

1R6611

1/20W5%

201MF

100K

2

1R6613

MF

100K5%

NOSTUFF

1/20W

201

21

R6614

402MF-LF1/16W

0

5%

SYNC_MASTER=AUDIO SYNC_DATE=02/09/2010

AUDI0: SPEAKER AMP

R_SPKRAMP_SHDN

VOLTAGE=5VMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

PP5V_S3_U6610

MAX98300_R_N

=PP5V_S3_AUDIO_AMP

SPKRAMP_INR_NR_AMP_GAIN

SPKRAMP_INR_P

AUD_GPIO_3



SPKRAMP_R_N_OUT



SPKRAMP_R_P_OUT

MAX98300_R_P

66 OF 110

4.4.0

051-8379

48 OF 73

B2

71

8

7 49

7 49

71

NC

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

NC

NC

IN

IN

NC

NC

G

D

S

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

NEG

POS

POS

NEG

NEG

SYS_DETECT

SDA

SCL

POS




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

518-0369

3.425V "G3Hot" Supply

518S0508

Vout = 1.25V * (1 + Ra / Rb)

<Rb>

<Ra>

60MA MAX OUTPUT

Vout = 3.425V

APN:518S0519

HALL EFFECT PADS

SPKR

SIL ON MLB FOR DEVELOPMENT ONLY

S3 AND S0 INDICATOR LEDS FOR DEVELOPMENT ONLY

BATTERY CONNECTOR

Supply needs to guarantee 3.31V delivered to SMC VRef generator

MLB TO LIO POWER CABLE CONNECTOR

998-3029

(Switcher limit)

2

1 C6905

50V

0.01UF

603

20%

CERM

2

1 C6999

6.3V

603-1X5R

20%

10UF

CRITICALOMIT_TABLE

2

1C6994

X5R201

6.3V20%

0.22UF

2

1R6995

1/20W

348K

201

MF

1%

2

1 C6995

201

22PF5%

CERM50V

2

1R6996

201

MF1/20W

1%

200K

2

1C6990

10%25V

2.2UF

X5R-CERM603

21

R6905

MF-LF

1/8W

10

5%

805

2

1C69500.1UF

X5R25V

402

10%

21

3

D6950RCLAMP2402B

SC-75

CRITICAL

NOSTUFF

2

1R6950

5%

10K

201

1/20WMF

2

1 C6955

10%

402

CERM

50V

0.001UF

NOSTUFF

21

R6961

5%

0

MF201

1/20W

6

9

48

5

1

3

2

U6990

DFN

CRITICAL

LT3470A

21

L699533UH-20%-0.39A-0.435OHM

CRITICAL

DP418C-SM

6

5

4

3

2

1

J6900M-RT-SM

WTB-PWR-M82

2

1 C69060.01UF

X5R

201

10%10V

2

1C6951

X5R

10%16V

1UF

402

7 48

7 48

3

2

1

D6905

SOT-323

BAT30CWFILM

CRITICAL

8

7

6

5 4

3

2

1

J6955SM

HALL-SENSOR-MLB-PADS-K99

OMIT_TABLE

2

1

4

3

J690378171-0002

M-RT-SM

CRITICAL

K

AD69202.0X1.25MM-SM

S3_S0_LED

GREEN-3.6MCD

K

AD69102.0X1.25MM-SMGREEN-3.6MCD

S3_S0_LED

4

5

3

Q6940

SOT-363

2N7002DW-X-G

S3_S0_LED

2

1R6941

402

5%1/16WMF-LF

S3_S0_LED

1K

2

1R69401K5%1/16WMF-LF

S3_S0_LED

402

KA

D6900SIL

2.0X1.25MM-SMGREEN-3.6MCD

9

8

7

6

5

4

3

2

1

13

12

11

10

J6950F-RT-TH

CRITICAL

BAT-K99


DC-In & Battery Connectors

DIDT=TRUE

P3V42G3H_BOOST

=PP3V42_G3H_REG

=PP3V3_S3_DBGLEDS

PPBUS_G3H

SWITCH_NODE=TRUE DIDT=TRUE


P3V42G3H_SW


VOLTAGE=18.5V

PPVIN_G3H_P3V42G3HMIN_LINE_WIDTH=0.4 mm


ITS_ALIVE CORE_VOLTAGES_ON_R

SYS_LED_ANODE

ALL_SYS_PWRGD

SMC_LID_R

=PP3V42_G3H_HALL

SPKRAMP_R_N_OUT

SPKRAMP_R_P_OUT

SMC_LID

=PP5V_S3_LIO_CONN

P3V42G3H_FB

MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.6MMVOLTAGE=18.5VPPDCIN_G3H_OR_PBUS_RPPDCIN_G3H_OR_PBUS

=PP18V5_DCIN_CONNMIN_LINE_WIDTH=1mm

VOLTAGE=18.5VMIN_NECK_WIDTH=0.20mm

CORE_VOLTAGES_ON

PPVBAT_G3H_CONN

=SMBUS_BATT_SDA

SYS_DETECT_L

=SMBUS_BATT_SCL

69 OF 110

4.4.0

051-8379

49 OF 73

7

8

8

7 8 42

39

25 38 57

7

7 8

7 38 39 46

7 8

50

7 8

7 50

41

7

41

OUT

OUT

IN

BI

OUT

AMON

BMON

ACOK

LGATE

PHASE

BOOT

SGATE

AGATE

CSIP

CSIN

DCIN

VNEG

CSOP

CSON

THRM_PAD

PGND

VDDPVDD

BGATE

UGATE

ICOMP

VCOMP

ACIN

SDA

VFRQ

CELL

VHST

SCL

SMB_RST_N

IN

S

G

D

G

D

S

IN

G

D

S

G

D

S




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

FROM ADAPTER

(CHGR_DCIN)

TO/FROM BATTERY

DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

* R7051 HAS 2.2OHM TO COMPENSATE UNVALANCED VOLTAGE

Reverse-Current Protection

(CHGR_AGATE)

ACIN pin threshold is 3.2V, +/- 50mV

Input impedance of ~40K meets

DIVIDER SETS ACIN THRESHOLD AT 12.18V

(PPVBAT_G3H_CHGR_R)

Q7055.

30mA max loadsparkitecture requirements

(CHGR_CSO_N)

(AGND)

353S2392

(PPVBAT_G3H_CHGR_R)

This node is powered

through body diodes:

* DCIN through Q7080.

Charger TOP FETs and

* PBUS through Q7085,

(CHGR_BGATE)

K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT

20V/V

(GND)

Float CELL for 1S

(OD)

36V/V

(CHGR_CSO_P)

f = 400 kHz

Inrush Limiter

Max Current = 8A

TO SYSTEM

(CHGR_SGATE)

2

1R7011

MF

1%

10.5K

1/20W

201

2

1 C7042

10%

X5R

6.3V

0.1UF

201

2

1 C7016

201X5R-X7R16V

470PF10%

2

1R7016

MF201

3.01K1%

1/20W

2

1C7015

201X5R-X7R

16V10%

470PF

2

1R7015

201

1/20WMF

5%

220K

2

1C7002

10V

402

1UF

X5R

10%

2

1 C7000

X5R402-1

1UF10%10V

21

R70014.7

5%

402MF-LF1/16W

2

1R7010

201MF

1/20W1%

30.1K

21

XW7000

PLACE_NEAR=U7000.29:1mmPLACE_NEAR=U7000.22:1mm

SM

2

1C7001

X5R

10%10V

402

1UF

2

1 C7021

10%

402

X5R25V

0.1UF

2

1C7022

X5R

0.1UF

25V

402

10%

2

1 C70200.047UF

16V

X7R

10%

402

2

1 C70250.22UF

10V

CERM

10%

PLACE_NEAR=U7000.25:2mm

402

321

4

5

Q7035

LFPAK-HF

RJK0305DPB

CRITICAL

21

R7022

MF1/20W

201

5%

10

21

R7021

MF201

1/20W5%

10

2

1C7030

20%

POLY-TANT25V

CRITICAL

CASE-D3L

33UF-0.06OHM

2

1C7031

20%

25VPOLY-TANT

33UF-0.06OHM

CRITICAL

CASE-D3L

F7040

1206-1

7AMP-24V

CRITICAL

21R7051201MF1/20W5%

2.2

21R7052 05% 201MF1/20W

2

1R7086

201MF

1/20W

332K1%

2

1R7081

1/20W

62K

201MF

5%

2

1C70050.22UF

20%

603X5R

25V

43

43

41

41

2

1C7011

10%0.01UF

201X5R

10V

2

1 C70500.47UF

10V

10%

X5R

402

2

1C7026

10%1000PF

201

16V

X7R

9

43

21

R70500.010.5%

1W

MF

0612-3

4

3

2

1R70200.0200.5%

MF-LF

0612

1W

CRITICAL

2

1 C7037

X7R

402

10%0.001UF

50V

PLACE_NEAR=Q7030.5:1.5mm

2

1 C70451000PF

PLACE_NEAR=L7030.2:1.5mm

201

16VX7R

10%

8

12

4

20

19

7

24

29

1326

10

11

23

22

21

5

2

18

17

28

276

25

15

16

9

1

14

3

U7000

ISL6259HRTZ

TQFN

CRITICALOMIT_TABLE

2

1R7002

MF

1/20W

100K5%

NO STUFF

201

57

32

1

4

5

Q7055

PWRPK-1212-8

CRITICAL

SI7615DN

2

1R7013

201

MF1/20W

1001%

3

2

1

D7005

CRITICAL

BAT30CWFILMSOT-323

2

1C7085

25V10%

0.1UF

402X5R

2

1

R7080

201MF1/20W

100K5%

2

1

R7085

1/20W

1%

MF

201

470K

321

4

5

Q7030RJK0332DPB-01

LFPAK-SM

CRITICAL

2

1

C7041

CASE-B2

11VELEC

CRITICAL

20%

62UF

21

R7005

5%

201MF

1/20W

20

2

1 C7035

X5R

25V

10%

1UF

603-1

2

1 C7036

X5R

603-1

1UF10%

25V

21

L70304.7UH-9.5A

IHLP4040DZ-SM

CRITICAL

21

R7000

201

MF1/20W

0

5%

7 38 39 40

5A

5

4

1

Q7080SI5419DU

CRITICAL

POWERPAK

5A

5

4

1

Q7085SI5419DU

CRITICAL

POWERPAK

2

1C7043

CASE-B2

62UF20%

11V

CRITICAL

ELEC2

1C7040

20%

CASE-B2ELEC

62UF

11V

CRITICAL

2

1 C7014

10%

1UF

603-1

25V

X5R2

1C7013

25V

X5R402

10%0.1UF

2

1C7012

10V

X5R

0.01UF10%

201

2

1 C7017

X5R

10UF

25V

805

10%

PBus Supply & Battery ChargerSYNC_MASTER=K6_MLB SYNC_DATE=11/09/2009


VOLTAGE=5.1V

PP5V1_CHGR_VDDP


PP5V1_CHGR_VDD



VOLTAGE=5.1V

CHGR_RST_L

=PP3V42_G3H_CHGR

=PPBUS_G3H

CHGR_SGATE_DIV


CHGR_CSI_P

CHGR_CSO_P

DIDT=TRUE

CHGR_BOOT

GND_CHGR_AGND


VOLTAGE=0V

VOLTAGE=8.4V



PPVBAT_G3H_CHGR_REG


VOLTAGE=18.5V

PPDCIN_G3H_CHGR


CHGR_CSI_R_N

CHGR_ACIN

CHGR_ICOMP

CHGR_CSO_N

CHGR_VNEG

CHGR_VCOMP

CHGR_VCOMP_R

=CHGR_ACOK

CHGR_CELL

=SMBUS_CHGR_SCL

CHGR_LGATEGATE_NODE=TRUE DIDT=TRUE

CHGR_AMON

CHGR_CSI_R_P

CHGR_VNEG_R

SMC_RESET_L

CHGR_BMON

GND_CHGR_AGND

=SMBUS_CHGR_SDA

CHGR_VFRQ

CHGR_DCIN_D_R

CHGR_CSO_R_N

CHGR_CSO_R_P

CHGR_UGATEGATE_NODE=TRUE DIDT=TRUE



PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmSWITCH_NODE=TRUE

CHGR_PHASE

DIDT=TRUE


CHGR_AGATE_DIV


PPDCIN_G3H_OR_PBUS

VOLTAGE=18.5V



PPDCIN_G3H_INRUSHMIN_LINE_WIDTH=0.6 mm

VOLTAGE=18.5V

PPVBAT_G3H_CHGR_R

VOLTAGE=8.4V

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 mm

CHGR_BGATE

CHGR_AGATE

=PPDCIN_S5_CHGR

CHGR_SGATE

CHGR_DCIN

CHGR_CSI_N

70 OF 110

4.4.0

051-8379

50 OF 73

8 57

8

70

70

50

70

70

70

50

43 70

43 70

7 49

49 8

70

OUT

IN IN

EN

EN2EN1

DRVL2

SKIPSEL1

SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2

CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

OUT

IN

GND/S2

VSW/S1/D2

GHS/G1

GLS/G2

VIN/D1

G

D

S

G

D

S




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

F=400KHZ

Vout = 3.3V

5.3A MAX OUTPUT

353S2678

F=400KHZ

Vout = 5.0V

5.6A MAX OUTPUT

2

1C72001UF10%

X5R16V

402

21

L7260CRITICAL

PCMC063T-SM

2.5UH-14A

2

1 C72411UF

X5R

10%16V

402

2

1C7264

402

0.1UF10%25VX5R

2

1C7290OMIT

10UF

6.3V

603

20%

X5R

2

1 C7224

10%25VX5R402

0.1UF

2

1C7252150UF

POLY-TANT6.3V20%

CRITICAL

CASE-B2-SM

2

1C7250

X5R

10UF

805

20%10V

2

1 C7281

402

16V

1UF10%

X5R

21

L7220

PCMC063T-SM

2.5UH-14A

CRITICAL

2

1C7203OMIT_TABLE

10%

402CERM6.3V

1UF

2

1 C7205OMIT_TABLE

6.3V

10UF

X5R

20%

603

2

1R7206

1/20WMF

1%

201

249K

57

2

1

XW7261SM

PLACE_NEAR=L7260.2:3mm

2

1C7201

10V10%

402CERM

0.22UF

2

1R7260

1%

201

1/20WMF

23.2K

2

1R7261

1%10K

201

1/20WMF

2

1R7220

1/20W1%41.2K

MF201

2

1R7221

1%10K

201MF1/20W

2

1C7240

11VELEC

CASE-B2

62UF20%

CRITICAL

21

XW7200SM

PLACE_NEAR=U7201.28:1mm2

1R72161%1/20WMF201

3.16K

21

R7246

1/20WMF

1%

1.87K

201

2

1

XW7260


SM

21

C7218

16V10%

X5R402

0.1UF

21

R7247

1/20WMF

1%

1.87K

201

2

1R7256

MF1/20W

3.16K1%

201

2

1

XW7220SM


2

1

XW7221SM


2

1R7236

1%6.04K

MF201

1/20W

2

1R7237

201

20K

1/20WMF

1%

NO STUFF

2

1

XW7262SM


2

1

XW7222SM


2

1

C7292

CASE-B2-SMTANT6.3V20%

150UF-0.018OHM-1.8ACRITICAL

2

1R7239

MF1/20W

201

NO STUFF

1%20K

2

1C7239

10%100PF

X7R-CERM25V

201

2

1R7238

1%

MF201

6.04K

1/20W

2

1C7238

X5R

10%

201

0.01UF

10V

57 57

21R7248

5%

0

201MF1/20W

NO STUFF

2

1R72490

201

1/20WMF

5%

2

1 C7272

X7R

10%16V

201

1000PF


2

1 C7283

16V


X7R

10%1000PF

2012

1 C7270

PLACE_NEAR=Q7220.5.2:1.5mm

1000PF

201

10%

X7R16V

2

1 C727110%

X7R16V

201

1000PF

PLACE_NEAR=L7220.1.2:1.5mm

29

22

13

23

169

2631

2

33

2532

19

6

3

205

14

11

28

214

12

2730

241

187

178

1510

U7201QFN

CRITICAL

TPS51980

2

1C7282

ELEC

CRITICAL

CASE-B2

11V20%

62UF

2

1R724505%

MF-LF402

1/16W

2

1R7251PLACE_NEAR=U7201.4:2mm

402MF-LF1/16W

05%

2

1R7252

5%0

1/16WMF-LF402


57

57

8

732

54

6

1

Q7260CRITICAL

SIZ700DTPOWERPAIR-6X3.7

2

1C7236

10%

X5R10V

0.01UF

201

2

1C7237

10%100PF

X7R-CERM25V

201

21

C7288

402X5R

10%16V

0.1UF

1

2R7264

402

1/16W5%0

MF-LF

3 2 1

4

5

Q7225RJK03E0DNS

HWSON-8

CRITICAL

3 2 1

4

5

Q7220HWSON-8

CRITICAL

RJK03E0DNS

SYNC_MASTER=K16_MLB

5V / 3.3V Power SupplySYNC_DATE=07/07/2010

P5VS3_VFB1

=PP5V_S3_REG

P5VS3_VFB1-R

DIDT=TRUE SWITCH_NODE=TRUEP5VS3_LL


=PPVIN_S5_P5VP3V3

P3V3S5_CSN2

P3V3S5_COMP2

P5VS3_EN_R

P5VS3_COMP1

P5VS3_CSN1

P5VS3_DRVHGATE_NODE=TRUEDIDT=TRUEMIN_LINE_WIDTH=0.6 mm


DIDT=TRUEMIN_NECK_WIDTH=0.2 mm

P5VS3_VBST_RMIN_LINE_WIDTH=0.6 mm

P5VP3V3_VREF2P5VP3V3_VREF2

P5VS3_PGOOD

P5VS3_CSP1

P5VS3_VBSTMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P5VP3V3_VREG3

P3V3S5_PGOOD

P3V3S5_VBST_R


DIDT=TRUE

=PP5V_S3_REG

=PP3V3_S5_REG

DIDT=TRUESWITCH_NODE=TRUEMIN_NECK_WIDTH=0.2 mm

P3V3S5_LLMIN_LINE_WIDTH=0.6 mm

P5VP3V3_VREF2

P3V3S5_VFB2_R


DIDT=TRUEP3V3S5_VBST

=P5V3V3_REG_EN

P3V3S5_RFP5VS3_FUNC

P3V3S5_COMP2_R

=P3V3S5_EN=P5VS3_EN

P5VS3_COMP1_R

P5VP3V3_VREG3

DIDT=TRUEGATE_NODE=TRUEP3V3S5_DRVH


P3V3S5_CSP2_R

P5VS3_CSP1_R

MIN_LINE_WIDTH=0.6 mm DIDT=TRUEP5VS3_DRVL

GATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mm

P3V3S5_CSP2GATE_NODE=TRUE


P3V3S5_DRVLDIDT=TRUE

P5VP3V3_VREG5

P3V3S5_EN_R

P3V3S5_VFB2

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0V

GND_P5VP3V3_SGND

051-8379

4.4.0

72 OF 110

51 OF 73

8 51

8

51 51

51

8 51

8 57

51

51

56

MODE

VDDQSNSCOMP

NC0

NC1

VTTSNS

VTT

VTTREF

PGOOD

S3

S5

VTTGND THRM_PAD GND CS_GNDPGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILTV5IN

SYM (2 OF 2)

IN

IN

OUT

NCNC

G

D

S

OUT

OUT

G

D

S




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1


(DDRREG_DRVL)

(DDRREG_LL)

(DDRREG_VBST)

f = 400 kHz13A Max OutputVout = 1.501V / 1.352V

Vout = 0.75V * (1 + Ra / Rb)

(DDRREG_DRVH)

(DDRREG_CSGND)

VDDQ PGOOD

VDDQ/VTTREF Enable

VTT Enable

Vout = VTTREF

Vout = VDDQSNS/2

10mA max load

(DDRREG_VDDQSNS)

(DDRREG_FB)

(GND_DDRREG_SGND)

<Ra>

<Rb>Use LVDDR3:YES for fixed 1.35V operation or LVDDR3:NO for fixed 1.5V operation.

21

C7325

402

0.1UF

16V10%

X5R

2

1R7320

MF1/20W1%15K

201

2

1R7321LVDDR3:YES

201MF1/20W

18.7K1%

2

1 C733210%1UF16V

402X5R

2

5

124

23

8

9

22

15

14

25

11

10

13

18

12

7

4

20

3

19

21

17

16

6

U7300

QFN

CRITICAL

TPS51116

21

R73054.7

1/16WMF-LF

5%

402

2

1 C7361

6.3VX5R-CERM-1603

22UF20%

OMIT_TABLE

2

1C7360

6.3VX5R-CERM-1

603

22UF20%

OMIT_TABLE

21

XW7360SM


21

XW7335SM


2

1C735033000PF

201X5R

10%6.3V

57

2

1C73004.7UF

10VX5R

10%

805

57

2

1R7310

201

1/20WMF

1%12K

21

L7330

IHLP2525CZ-SM

0.82UH-20%-13A-0.0067OHM

CRITICAL

2

1

XW7345SM

PLACE_NEAR=L7330.2:1 MM

2

1C735510UF

X5R6.3V

603

20%

OMIT_TABLE

2

1C7341

CASE-B2-SM

330UF

TANT2.5V

CRITICAL

20%

2

1 C7340

CASE-B2-SM

CRITICAL

330UF

TANT2.5V20%

2

1 C734510UF

X5R

OMIT_TABLE

6.3V

603

20%

2

1 C7333

201

16V

1000PF10%

X7R


2

1C730510%

402-1X5R10V

1UF

21

XW7300PLACE_NEAR=U7300.3:1 mm PLACE_NEAR=U7300.25:1 mm

SM

321

4

5

Q7335CRITICAL

PWRPK-12128SIS426DN

2

1C732010%

X7R16V

201

1000PF

LVDDR3:YES

2

1R7380100K

5%

201MF

1/20W

42 71

42 71

2

1C7331CRITICAL

62UF11VELEC

CASE-B2

20%2

1C7330

CASE-B2

62UF11VELEC

CRITICAL

20%

2

1C7346PLACE_NEAR=R7350.1:1.5MM

16V10%

X7R201

1000PF

321

4

5

Q7330SIS426DNPWRPK-12128

CRITICAL

3

4

1

2R73501%

1/4WMF-LF1206

CRITICAL

0.002

LVDDR3:NOR73211114S0331 RES,15K,1%,1/16W,MF-LF,0402


1.5V/1.35V LVDDR3 Supply

DDRREG_FB

=PPVIN_S0_DDRREG_LDO

PPDDR_S3_REG_RMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.5V

ISNS_1V5_S3_P

=DDRREG_EN=DDRVTT_EN

DDRREG_VTTSNS

DDRREG_VBSTDIDT=TRUE


DDRREG_CS

DDRREG_CSGNDMIN_LINE_WIDTH=0.1 mmMIN_NECK_WIDTH=0.1 mm

=PP5V_S3_DDRREG

VOLTAGE=5V

PP5V_S3_DDRREG_V5FILTMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mmDDRREG_LLSWITCH_NODE=TRUEDIDT=TRUE MIN_NECK_WIDTH=0.17 mm

DIDT=TRUEGATE_NODE=TRUEDDRREG_DRVH


=PPVIN_S3_DDRREG

DDRREG_VDDQSNS


=PPDDR_S3_REG

ISNS_1V5_S3_N

=PPVTT_S3_DDR_BUF

DIDT=TRUEGATE_NODE=TRUE


DDRREG_DRVLMIN_LINE_WIDTH=0.6 mm


VOLTAGE=0VMIN_NECK_WIDTH=0.17 mm

GND_DDRREG_SGND

DDRREG_PGOOD

=PP3V3_S3_PDCISENS

=PPVTT_S0_DDR_LDO

73 OF 110

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051-8379

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33

8

8

8

8

8 33

8

8

S

G

D

D

G

S

NCNC

NCNC

OUT

NC

OUT

IN

NC

V5FILT

OSRSELISLEW

VID6

DROOP

TRIPSEL

VR_TT*

THERM

GNDSNS

VREF

VID0

VID1

VID2

VID3

VID4

VID5

CSP

CSN

LL

VR_ON

GND

PGND

DPRSLPVR

DRVL

PGOOD

DRVH

VBST

PWRMON

DPRSTP*

CLK_EN*

VSNS

V5IN

TONSEL

IN

IN

IN

IN

IN

IN

ININ

IN




36

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PAGE


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8 7 5 4 2 1

MIN_LINE_WIDTH

MIN_NECK_WIDTH

MIN_NECK_WIDTH

MAX CURRENT = 18A

MIN_LINE_WIDTH

IMVP6 CPU VCORE REGULATOR

PWM FREQ. = 400KHZ

(CPUIMVP_LL)

OCP = 21.5MV / R7480 + 3.1A

18A @ 1V = 1.62VVPMON = 90 X R7480 X VO X IO

LOAD LINE = R7480 X 6 / (500U X R7414)

21

L7400

PCMC104T-SM

CRITICAL

0.36UH-30A-1.05MOHM

2

1 C7453

X5R

10%1UF

16V

4022

1 C7458CRITICAL

11V

62UF20%

ELECCASE-B2

2

1 C745962UF20%11V

CRITICAL

ELECCASE-B2

2

1 C74571UF

402

16V10%

X5R

3

4 6

5

2

1

Q7400S1

IRF6710

CRITICAL

43

5

7621

Q7451DIRECTFET-MXIRF6795

CRITICAL

4 3

2 1

R7480

MF-1

1%

0612

1W

CRITICAL

0.001

2

1 C7454PLACE_NEAR=Q7400.1:1.5mm

X7R

10%16V

201

1000PF

2

1 C7455PLACE_NEAR=R7480.1:1.5MM

16V10%

X7R

1000PF

201

21

R74910

MF

5%

201

1/20W

21

R7492

201

0

5%

MF1/20W

2

1C74141UF10%16V

X5R-X7R603-2

21R74512011/20W MF5%

470

21R7452 4705% MF1/20W 201

2

1 C7451

201

10%

X7R-CERM25V

100PF

2

1R741505%

MF-LF1/16W

402

25

43

38

2

1C7452

201

10%

X7R-CERM25V

100PF

2

1 C7412

X5R-CERM

4.7UF

603

10%6.3V

2

1C7413

603CERM16.3V20%

2.2UF

6

1

8

25

10

11

12

13

14

15

16

18

21

31

27

28

7

26

22

33

29

19

30

5

2

20

17

32

9

23

4

3

24

U7400

QFNTPS51982RHB

CRITICAL

2

1 C7415

5%100PF

25VCERM201

11 12 65

11 12 65

2

1R7414

MF201

1/20W1%

3.01K

2

1R7411

5%0

MF1/20W

2012

1R7410

MF1/20W

5%0

201

11 12 65

11 12 65

11 12 65

11 12 65

11 12 65

21

XW7400SM

2

1R7426150K5%

MF1/20W

2012

1R7425

1%1/20W

124K

MF201

2

1R7421NO STUFF

5%

201

1/20WMF

10K

2

1R7420

5%

MF

0

1/20W

201

2

1 C7456

11V

62UF20%

CASE-B2ELEC

CRITICAL

I787

2

1R7422

201

2.0K

1/20WMF

5%

21R7453

1/20W1%

MF201

499

14 65

2

1C7450NO STUFF

100PF5%

50V

402CERM

2

1 C7460

10VCERM

10%

402

0.22UF

IMVP6 CPU VCore RegulatorSYNC_MASTER=POWER SYNC_DATE=07/13/2005

0.20 MM0.25 MMPP1V7_S0_IMVP6_VREF

IMVP6_CS_R_N

IMVP6_VSEN_P

IMVP6_VSEN_N

IMVP6_CS_R_P

IMVP6_CS_P

VR_PWRGOOD_DELAY

CPU_VID<2>

=PPVCORE_S0_CPU_REG

=PPVIN_S5_CPU_IMVP

IMVP6_TONSEL

=PP3V3_S0_IMVP

CPU_VID<5>

PM_DPRSLPVR

GATE_NODE=TRUE

IMVP6_DRVL

DIDT=TRUE

IMVP6_ISLEW

IMVP6_THERM

IMVP6_DROOP

DIDT=TRUE

IMVP6_VBST

DIDT=TRUE

IMVP6_DRVH

GATE_NODE=TRUE

IMVP6_VBST_RC

DIDT=TRUE

IMVP6_PMON

IMVP6_DPRSLPVR


IMVP_VR_ON

CPU_VCCSENSE_P

1.5 MM 0.20 MMIMVP6_VBST_RC

1.5 MM 0.20 MMIMVP6_DRVH

1.5 MM 0.20 MMIMVP6_LL

0.20 MMPP5V_S0_IMVP6_V5FILT 0.25 MM0.25 MM 0.20 MMIMVP6_VBST

1.5 MM 0.20 MMIMVP6_DRVL

CPU_VCCSENSE_N

0.25 MM 0.20 MMIMVP6_THERM

GND_IMVP6_SGND 0.20 MM0.50 MM

CPU_VID<4>

CPU_VID<6>

CPU_VID<3>

=PP5V_S0_CPU_IMVP

PP5V_S0_IMVP6_V5FILT

VOLTAGE=5V

DIDT=TRUE

SWITCH_NODE=TRUE

IMVP6_LL

PPVCORE_S0_CPU_REG_RVOLTAGE=1.25VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.7VPP1V7_S0_IMVP6_VREF

CPU_DPRSTP_L

VOLTAGE=0VGND_IMVP6_SGND

IMVP6_OSRSEL

IMVP6_TRIPSEL

IMVP6_CS_N

0.20 MM0.25 MMIMVP6_ISLEW

0.25 MM 0.20 MMIMVP6_DROOP

74 OF 110

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53

71

65

65

71

71

8

8 8

53

53

53

53

53

53

53

11 65

53

53

53

53 53

53

11 65

53

53

8

53

53

53

53

71

53

53

IN

IN

IN

OUT

OUT

IN

IN

NC

IN

IN

NC

ISP

OCSET

ISN

ICOMP

LGATE

COMP

VDIFF

AF_EN

IMON

VID3

VID2

VDD

BOOT

FB

FDE

PGND

PGOOD PHASE

PVCC

RTN

THRM_PAD

VID0

VID1

VO

VSEN

VSS

VW

UGATE

VINRBIAS

SOFT

VR_ON

G

D

S

G

D

SG

D

S




36

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DR


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PAGE TITLE

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Apple Inc.

PAGE


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8 7 5 4 2 1

(MCPCORES0_FB)

(MCPCORES0_COMP)

(MCPCORES0_VO)

(MCPCORES0_ISN)

(MCPCORES0_ICOMP)

Vimon = 31 * Io * R7525 * (1 + R7575/R7573)

(MCPCORES0_UGATE)

OCP = R7569 X 10UA / ( R7525 X (1 + R7575 / R7573) )

0100 0.8750V

0011 0.8875V

0010 0.9000V

1101 0.9625V

1110 0.9500V

0000 0.9250V

0101 0.8625V

0110 0.8500V

0111 0.8375V

1000 0.8250V

1001 0.8125V

1010 0.8000V

1011 0.7875V

(MCPCORES0_VW)

VID<3:0> VOLTAGE

K6 NOTES : XOR AND INVERTER IS REMOVED, CANNOT SYNC THIS PAGE FROM T27

0001 0.9125V

1111 0.9375V

1100 0.9750V

(MCPCORES0_VDIFF)

(MCPCORES0_VSEN)

(MCPCORES0_RTN)

f = 300 kHz

(Q7560 Limit)

MAX CURRENT: 15A(MCPCORES0_PHASE)

19

19

21

R7568

201

1/20WMF

20

1%

21

R7566

201

1/20WMF

1%

20

2

1 C75701000PF

16V10%

X7R201

2

1R7563

201

1/20WMF

1%100

2

1 C75760.1UF

402

16VX7R-CERM

10%

2

1R7572

201

1%1/20W

MF

147K

57

57

2

1R7561

201

1K

1/20WMF

5%

21

XW7561


SM 2

1R7575

201MF1/20W1%22.1K

2

1R7573

201

1/20W1%

MF

10K

21

R7569

201

1/20WMF

1%

9.76K

1

2R7565

MF-LF603

05%1/10W

2

1C7564

603

5%10V

0.22UF

CERM-X7R2

1 C7550

16V

402X5R

1UF10%

21

R7560

CRITICAL

1/10W5%

603MF-LF

2.2

2

1 C7562

X5R402

16V10%1UF

21

R7578

201

1/20WMF

1%

200

21

R7579

MF201

3.01K

1/20W1%

21

R7577

201

1%1/20WMF

150K

21

C7580

402CERM

560PF

10%50V

21

C7581100PF

CERM402

50V5%

2

1R7571

1%100

1/20WMF201

21

C75824700PF

CERM402

10%100V

2

1C7579

402

10%50VX7R

0.001UF

2

1R7576

201MF

1%6.98K

1/20W

2

1 C756610UF

4V

603

20%

X5R

2

1C7568

20%270UF

2V

CASE-B4-SM

CRITICAL

TANT

2

1 C7565270UF

CRITICAL

CASE-B4-SMTANT2V20%

2

1C7567

603

4V

10UF

X5R

20%

2

1 C7561

X5R

10%1UF

16V

402

2

1 C7563

201

16V

1000PF


X7R

10%

21

R7500

MF-LF

1%1/16W

402

100

2

1C7573

201NP0-C0G

25V5%

47PF

2

1C7575

201NP0-C0G

25V5%

47PF

43

21

R75250.001

1%1W

0612MF-1

CRITICAL

21

L7560CRITICAL

0.47UH-20%-0.0021OHM-26A

PCMB103T-SM

2

1C7540CRITICAL

CASE-B2

11VELEC

62UF20%

43

2

1C7541

CASE-B2

11VELEC

62UF20%

CRITICAL

22 71

22 71

21R7593 05% MF1/20W 201

NOSTUFF

21R7590 05% MF1/20W 201

21R75915%

0MF1/20W 201

2

1 C7578

10%

X7R16V

201

1000PF2

1 C7577

10%16VX7R201

1000PF

21R7592MF1/20W5% 201

0

21R7594 0MF1/20W5% 201

19

19

4

15

8

29

12

14

27

26

25

24

7

16

18

33

2

9

1

22

1931

20

3

21

13

11

28

10

32

6

5

17

30

U7500

CRITICAL

ISL9563B

QFN

321

4

5


CRITICAL

321

4

5


CRITICAL

2

1 C7569

201

16V

1000PF

X7R

10%

PLACE_NEAR=R7525.1:1.5MM

321

4

5

Q7566PWRPK-12128SIS426DN

CRITICAL


MCP VCore Regulator


PP5V_S0_MCPREG_VDD

VOLTAGE=5V


DIDT=TRUE

MCPCORES0_LGATE


GATE_NODE=TRUE

MCPCORES0_IMON_R


MCPCORES0_PHASE

DIDT=TRUESWITCH_NODE=TRUE

MCPCORES0_UGATE


GATE_NODE=TRUEDIDT=TRUE


VOLTAGE=1VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MMPPMCPCORE_S0_R

MCPCORES0_VO

MCPCORES0_RTN

MCPCORES0_FDE


MIN_LINE_WIDTH=0.6 mmGND_MCPCORES0_AGND

MCP_VID2_REG

MCP_VID0_REG

MCPCORES0_PGOOD

=PPMCPCORE_S0_REG

MCPCORES0_VW

=MCPCORES0_EN

MCP_VID<0>

MCPCORES0_VSEN_P

MCP_VID<2>

MCP_VID<1>

MCPCORES0_IMON

MCPCORES0_VSEN_N

MCPCORES0_VDIF_C

=PPMCPCORE_S0_REG

MCP_VID<3>


DIDT=TRUE

MCPCORES0_BOOT_R


=PP5V_S0_MCPREG

=PPVIN_S0_MCPCORE

MCPCORES0_ISN

MCPCORES0_OCSET

MCPCORES0_ICOMP

MCPCORES0_ISP

MCPCORES0_ISP_R

MCPCORES0_RBIAS


DIDT=TRUEMCPCORES0_BOOT

MCPCORES0_VSEN

MCPCORES0_SOFT

MCP_VID3_REG

MCP_VID1_REG

MCPCORES0_VDIFF

MCPCORES0_FB

MCPCORES0_COMP_C

MCPCORES0_COMP

75 OF 110

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051-8379

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23

9

8 54

8 54

8

8

9

IN BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC PVCC

GND PGND

EN

FB

OUT

G

D

S

G

D

S




36

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8 7 5 4 2 1

(CPUVTTS0_OCSET)

Place XW7610, XW7611

<Rb>

<Ra>

(CPUVTTS0_VO)

remote sensing.at desired location for

f = 300 kHz

Vout = 1.05V11.5A Max Output

Vout = 0.5V * (1 + Ra / Rb)OCP = R7641 x 8.5uA / R7640

57

34

12

R7640CRITICAL

0.001

MF-10612

1W1%

2

1C7630

402

1UF

X5R

10%16V

2

1C762020%11V

ELEC

62UF

CASE-B2

CRITICAL

2

1C7621

CASE-B2

62UF

ELEC11V20%

CRITICAL

2

1 C7622


X7R

10%1000PF16V

201

2

1 C7647OMIT_TABLE

X5R6.3V

10UF

603

20%

2

1 C760110UF20%

X5R10V

6032

1R7601

1/10W5%

MF-LF603

2.2

21

XW7600SM

2

1 C7603

X7R

10%16V

0.047UF

402

2

1R76411.78K

1%1/20W

MF201

2 1

C7640

25V5%

402

1000PF

NP0-C0G

2

1R7642

201MF1/20W1%1.78K

1

2R7644

201MF1/20W1%3.01K

2

1R76452.74K1%1/20WMF201

8

13

11

4

2

14

10

9

16

7

15

1

5

6

3 12

U7600ISL95870

UTQFN

CRITICAL

21

L7630CRITICAL

0.82UH-20%-13A-0.0067OHM

IHLP2525CZ-SM

2

1C7602

X5R603

2.2UF16V10%

2

1R7603

201MF1/20W5%0

57

2

1 C7605

201

16V

1000PF10%

X7R2

1C7604

201

10%

X7R16V

1000PF

2

1R76043.01K

1%1/20W

MF201

2

1R7605

201

2.74K1/20W

MF

1%2

1C7648CRITICAL

270UF

CASE-B4-SMTANT2V20%

2

1C7649CRITICAL

270UF

CASE-B4-SMTANT

2V20%

2

1C76231000PF

201

16VX7R

10%


21

XW7611SM

21

XW7610SM

321

4

5

Q7630CRITICAL

RJK03E0DNSHWSON-8

321

4

5

Q7635HWSON-8RJK03E0DNS

CRITICAL

CPUVTT (1.05V) Power SupplySYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

CPUVTTS0_CS_P

CPUVTTS0_OCSET

=PPCPUVTT_S0_REGCPUVTTS0_LL

DIDT=TRUE


SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.2 mm

PPCPUVTT_S0_REG_RMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

CPUVTTS0_CS_N

CPUVTTS0_VO


DIDT=TRUE

CPUVTTS0_VBST

=PPVIN_S0_CPUVTTS0

DIDT=TRUEGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmCPUVTTS0_DRVH


DIDT=TRUEGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mm

CPUVTTS0_DRVL

=PPCPUVTT_S0_REGCPU_VTTSENSE_P

CPU_VTTSENSE_N

CPUVTTS0_FB

CPUVTTS0_PGOOD

=PP5V_S0_CPUVTTS0

CPUVTTS0_RTN

CPUVTTS0_FSEL

=CPUVTTS0_EN

CPUVTTS0_AGNDMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0V

CPUVTTS0_SREF

VOLTAGE=5VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmPP5V_S0_CPUVTTS0_VCC

76 OF 110

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71

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71

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8 55

71

71

8

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND THRM_PAD

SS

IN0

IN1

THRML_PAD

EN FB

BIAS

OUT0

OUT1

GND

PG

OUT

OUT

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND THRM_PAD

OUT

GND

EN

OUTIN

NC NCIN





36

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8 7 5 4 2 1

MCPPLL_LDO - STUFFS U7740 AND RELATED CIRCUITRY.

MAX CURRENT = 1.5A

<Rb>

<Ra>

<Ra>

Vout = 1.05V

Vout = 0.8V * (1 + Ra / Rb)

<Ra>

<Rb>

TO USE 1.05V S0, MCPPLL_R:REG MUST BE ACTIVE, MCPPLL_LDO CAN BE ACTIVE, MCPPLL_R:LDO MUST BE INACTIVE.

f = 1.6MHZ

f = 1.6MHZ

Vout = 1.508V

TO USE U7740, MCPPLL_R:LDO AND MCPPLL_LDO MUST BE ACTIVE.

MCPPLL_R:LDO - 1.05V S0 USED FOR MCP PLL LDO POWER.

BOMOPTIONs:

<Rb>

1.5V S0 Regulator

Max Current = 0.5A

1.05V S0 MCP PLL LDO

MAX CURRENT = 0.016A

Vout = 0.8V * (1 + Ra / Rb)

MAX CURRENT = 1.5AVout = 0.902V

Vout = 0.8V * (1 + Ra / Rb)

Vout = 5.0V

MCP 0.9V S5 (AUXC) Switcher

5.0V S5 IPD LDO

2

1 C7750

PLACE_NEAR=U7750.1:1.5mm

CRITICAL

22UF

CERM

6.3V

805

20%

2

1R7751

1/20W

2.55K1%

MF201

2

1R7752

MF1/20W1%20K

201

2

1C7751

201

25VNP0-C0G

47PF5%

21

L7750CRITICAL

2.2UH-3.25A

IHLP1616BZ-SM

57

1

6

9

4 5

3

8

7

2

U7750DFN

CRITICAL

ISL8009B

2

1 C7743

201

10VX5R

2.2NF10%

MCPPLL_LDO

11

7 3

10

9

2

1

6

85

4

U7740

CRITICAL

TPS74701SON

MCPPLL_LDO

2

1R7747

201MF

MCPPLL_LDO

4.42K1%

1/20W

2

1C77411UF6.3V

402CERM

10%

MCPPLL_LDO

2

1R7743MCPPLL_R:LDO

100

402MF-LF

5%1/16W

2

1C7740MCPPLL_LDO

1UF

402CERM6.3V10%

2

1R7746

201MF

1/20W

MCPPLL_LDO

1%1.37K

2

1 C774220%4VX5R402

MCPPLL_LDO

4.7UF

21

R7744

1/16W

0

402

5%

MCPPLL_R:LDO

MF-LF

21

R7745MCPPLL_R:REG

402

5%

MF-LF1/16W

0

21

R7748

201MF

1/20W5%

0

MCPPLL_LDO

57

57

57

1

6

9

4 5

3

8

7

2

U7710

CRITICAL

ISL8009BDFN

2

1 C7710

8056.3VCERM20%22UF

PLACE_NEAR=U7710.1:1.5mm

2

1R7712

201

113K1%1/20WMF

2

1C77115%

47PF

201

25VNP0-C0G

2

1R77111%100K

MF201

1/20W

2

1 C7715

805CERM6.3V20%22UF

21

L7710

IHLP1616BZ-SM

CRITICAL

2.2UH-3.25A

57

2

1R7750

402

1/16W

MCPPLL_R:LDO

5%

MF-LF

0

2

1 C775520%22UF

CRITICAL

CERM6.3V

805

2

1 C7712PLACE_NEAR=U7710.1:1.5mm

X7R201

16V10%1000PF

2

1 C7716

201X7R

10%1000PF16V


2

1C7752PLACE_NEAR=U7750.1:1.5mm

1000PF

X7R16V10%

201

2

1C77561000PF16V10%

X7R


201

51

2

3

U7760SOT23-5

MIC5235-2.5V

OMIT_TABLE

2

1C7761IPD_5V:S5_EXT

X5R402

16V10%1UF 2

1 C7760

402X5R-CERM

IPD_5V:S5_EXT

2.2UF20%10V

57

21

R7760IPD_5V:S3

1/16W

0

MF-LF

5%

402

21

R7761

5%

MF-LF1/16W

0


IPD_5V:S5_INT

402

IPD_5V:S5_EXTIC,LDO,MIC5235,5V,1%,150MA,SOT23-5 U7760353S3034 1


Misc Power Supplies

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mm

VOLTAGE=5V

PP5V_S5_LDO

P5VP3V3_VREG5

=PP3V3_S5_P0V9S5

P0V9S5_PGOOD

=PP3V3_S0_P1V5S0

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmPP3V3_S0_MCP_PLL_LDO_BIAS

VOLTAGE=1.5VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmPP1V5_S0_MCPPLLLDO

=PP5V_S3_TPAD

P5V_S5_EN

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_REGMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

P1V5S0_EN


=PP1V5_S0_REG

=PP0V9_S5_REG

=P0V9S5_EN

P1V5S0_PGOOD P1V5S0_FB

MCPPLLLDO_SS

=PP1V05_S0_MCP_PLL_UF_R

=PP1V05_S0_MCP_PLL_OR

MCPPLLLDO_PGOODMCPPLLLDO_PGOOD_R

MCPPLLLDO_FB


MIN_NECK_WIDTH=0.2 mmSWITCH_NODE=TRUE

P1V5S0_SW

DIDT=TRUE


P0V9S5_FB


DIDT=TRUE

P0V9S5_SW

SWITCH_NODE=TRUE

=PPBUS_5V_S5

77 OF 110

4.4.0

051-8379

56 OF 73

4

46

8 57

8

8

8

8

8

8

8

8

8

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

IN

IN

D

SG

D

S G

D

SG

OUT

NC

IN

OUT

D

G S

OUT

VDD

OUT_A*

OUT_A

THRMGND

IN_A

DLY_1C

IN_B

OUT_BDLY (OD,IPU)

(OD,IPU)

(OD,IPU)(IPD)

1.3V

PAD

2:1

-

+

OUTIN

OUT

IN

OUT

IN

THRM_PADGND

V3MON

V4MON RST*

MR*

VDD VDDA

V2MON

Q3

Q2

Q4

Q1

NC

NC

IN

OUT

OUT

IN

OUT

OUT

D

SG

IN

OUT

OUT

IN

OUT

OUT

OUT

IN

OUT

IN

IN

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

NOTE: "AC" term valid only when Q7891 is stuffed

WLAN Enable Generation"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

3.3V w/Divider: 2.345V

Internal pull-ups 100K +/- 20%

S5 Rail Enables & PGOOD

Pull-up is with power FET.

DLY > 10 ms

Threshold: ??

353S2809

S0 Rail PGOOD (ISL Version)

S0 Rail PGOOD Circuitry

Q4: 0.660V

S0 Rail PGOOD (BJT Version)

V4MON: 0.610VV3MON: 0.610V

U7750 EN tied to VIN

Q2: 0.XXXVWorst-Case Thresholds:

Q3: 0.640V

Power Control Signals

353S2718

(IPU)

V2MON: 3.000VVDD: 2.9140VWorst-Case Thresholds:

ISL6259 Frequency Select

Sleep (S3)

Soft-Off (S5)

Battery Off (G3Hot)

1

1

0

1 Run (S0)

State SMC_PM_G2_ENABLE

0

0

0

1

0

0

11

PM_SLP_S4_L PM_SLP_S3_L

the same time as MEMVDD rail (Q2300).VTT rail must ramp up in aboutVTT Rail Enable

S0 Rail Enables

Need to re-characterize for power sequencing!

ENET Rail Enables

S3 Rail Enables

Need to re-characterize for power sequencing!

51

25 38 49

12

R7813

1/20W

0

201

5%

MF

2

1 C7813NO STUFF

10V

0.068UF10%

CERM402

21

R78120

MF201

1/20W5%

2

1 C7812NO STUFF

0.47UF10VX5R402

10%

51

7 36 37

2 1

R7859

201

1/20WMF

5%

100

58

1

2R78845.1K5%1/20W

201MF

2

1 C78840.47UF10%

402X5R10V

58

56

7 19 38 39 57

19 38 39

19 34

45

3Q7890SSM6N37FEAPE

SOT563

1 2

6Q7891SOT563SSM6N37FEAPE

WLAN_PCTL:HW

12

6Q7890SSM6N37FEAPE

SOT563

34

2

1C7870

402CERM10V20%

0.1uF

S0PGOOD_ISL

2

1R7871S0PGOOD_ISL

20.0K1/16W

1%

MF-LF402

2

1R787010K1/16W

402

1%

MF-LF

S0PGOOD_ISL56

52

21

R7864VFRQ:SLPS4

5%

0

201MF

1/20W

21

R7863

MF

5%

0

201

VFRQ:SLPS3

1/20W

21

3

Q7860VFRQ:SLPS4&VFRQ:SLPS3

SSM3K15FVSOD-VESM-HF

2

1R7861

MF

10K

201

1/20W

VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH

5%

2

1R78605%

VFRQ:LOW

201

10K1/20WMF

50

1

9

8

4

36

2

5

7

U7840SLG4AP012

TDFN

CRITICAL

2

1 C7841220PF25V

201

10%

X7R-CERM

2

1C7840

6.3VX5R201

0.1UF10%

38 56

51

2

1 C780110%

NO STUFF

33000PF6.3VX5R201

7 38

51

19 21

72

6

5

3

9

8

1

4

U7870

S0PGOOD_ISL

TDFN

CRITICAL

ISL88042IRTJJZ

3

2

8

46

1

7

5

Q7820

DFN2015H4-8ASMCC0179

S0PGOOD_BJTCRITICAL

2

1R7821S0PGOOD_BJT

201

15K1/20WMF

1%

2

1R7822S0PGOOD_BJT

1%

MF1/20W

201

7.15K

21

R7823

201

5%1/20WMF

1K

S0PGOOD_BJT

21

R7824S0PGOOD_BJT

201

1K

1/20WMF

5%

21

R7825

1/20W

S0PGOOD_BJT

201MF

5%

1K

2

1R7827S0PGOOD_BJT

100

201

1/20WMF

5%

21

R7828S0PGOOD_BJT

201

1/20WMF

5%

10

21

R7872S0PGOOD_ISL

10

5%1/20WMF201

2

1R7826

201MF

1/20W1%

S0PGOOD_BJT

150K

19

58

58

51

58

21

R7840

201

0

5%

MF1/20W

21

R7842

1/20WMF

5%

201

0

21

R7841

1/20WMF

5%

201

0

21

R7845

201

1/20WMF

0

5%

21

R78430

201

5%

MF1/20W

21

R78440

201

5%

MF1/20W

56

45

3Q7891SOT563

SSM6N37FEAPE

WLAN_PCTL:HW

7 19 38 57

52

2

1R7891WLAN_PCTL:SW

5%1/16W

0

402MF-LF

21

R7811

1/20W

5.1K

MF

5%

201

2

1 C7846NO STUFF

0.47UF10%10VX5R402

56

2

1R7846

5%0

MF-LF402

1/16W

57

2

1R7899

603

NO STUFF

MF-LF1/10W

05%

2

1 C7810

402

0.47UF10VX5R

10%

57

42

2

1R7810100K

5%

MF1/20W

201

1

2R7882

201

15K

MF1/20W5%

1

2R7881

201MF1/20W5%33K

1

2R788022K

201MF

5%1/20W

2

1 C7882

10VX5R402

10%0.47UF

2

1 C7881

402

10%

X5R10V

0.47UF

2

1 C7880

10VX5R

10%

402

0.47UF

55

7 19 38 39 57

2

1R7879

201

1/20WMF

5%100K

54

2

1R782010K

5%

MF1/20W

201

54

55


Power Sequencing

S0PGOOD_BJTS0PGOOD_BJT_L

VMON_3V3_DIV

PP1V5_S0

PP1V05_S0

DDRREG_ENMAKE_BASE=TRUE

P0V9S5_PGOOD

CPUVTTS0_ENMAKE_BASE=TRUE

=DDRREG_EN

=P3V3S3_EN

S5PGOOD_DLY

MAKE_BASE=TRUEMCP_MEM_VDD_EN

PM_SLP_S3_R_LMAKE_BASE=TRUE

=CPUVTTS0_EN

=P3V3S0_ENMAKE_BASE=TRUEP3V3S0_EN

=PBUSVSENS_EN

MCPCORES0_ENMAKE_BASE=TRUE

PP3V3_S0

=DDRVTT_EN

P3V3S3_ENMAKE_BASE=TRUE

=P5VS3_EN

PM_SLP_RMGT_LMAKE_BASE=TRUE

=P3V3ENET_EN=P0V9ENET_EN

=P1V5S0_EN

PM_SLP_S3_L

P1V5S0_ENMAKE_BASE=TRUE

=PP3V42_G3H_CHGR

CHGR_VFRQ

CHGR_VFRQ_GATE

PM_SLP_S4_L

PP5V_S0

PP3V3_S0

=PP3V3_S5_VMON

VMON_Q4_BASE

VMON_EMITTER

=PP3V3_S0_PWRCTL

PP3V3_S0_VMON

VOLTAGE=3.3V


VMON_Q3_BASE

PP1V5_S0PP1V05_S0 S0PGOOD_RST_L

CPUVTTS0_PGOOD

MCPPLLLDO_PGOOD

MCPCORES0_PGOOD

P1V5S0_PGOOD

PM_SLP_S3_L

ALL_SYS_PWRGDMAKE_BASE=TRUE

=MCPCORES0_EN

VMON_Q2_BASE

MAKE_BASE=TRUEP5VS3_EN

=P0V9S5_EN

PP3V3_S5

PM_SLP_S4_L

=USB_PWR_EN

P3V3S5_PGOOD

P5VS3_PGOOD

MAKE_BASE=TRUEP3V3S5_EN

P3V3S5_EN_L

AC_OR_S0_L

PM_WLAN_EN_L

AP_PWR_EN

SMC_ADAPTER_EN

PM_SLP_S3_L

SMC_PM_G2_ENMAKE_BASE=TRUE

=P5V3V3_REG_EN

P5V_S5_EN

RSMRST_PWRGDMAKE_BASE=TRUE

=P3V3S5_EN

=PP3V42_G3H_PWRCTL

=PP3V3_S5_P0V9S5

P3V3_BLEED

=PP3V3_S5_REG

P3V3S5_EN_L

=P5VS0_EN

78 OF 110

4.4.0

051-8379

57 OF 73

7 8 57 71

7 8 57

7 8 57 71

56

8 50

7 19 38 57

7 8

7 8 57 71

8

8

7 8 57 71

7 8 57

7 19 38 39 57

7 8 71

8

8 56

8 51

GND

VOUT

ON

VIN

D

S

G

D

SG

D

SG

IN

SG

D

IN

IN

D

G S

D

G S

D

G S

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

3.3V S3 FET 3.3V ENET Switch

0.9V ENET FET

3.294 A (EDP)Loading

FDC638P

2.0 A @85C

2.0 A @85C

65 mOhm @2.5V

65 mOhm @2.5V

FDC638P

P-Channel

Part

0.100 A (EDP)

3.3V S0 FET

7.2 A @85C

ID(max)

Loading

ID(max)

14 mOhm @4.5V

TPCP8102

Type

Loading

Rds(on)

Type

ID(max)

Part

Type

R(on)

I(max)

Loading

50 mOhm Max

0.4 A (EDP)

2 A

Load Switch

TPS22924C

18 mOhm Typ

U7980

Q7940

Rds(on)

Q7910

Q7930MOSFET

P-Channel

5V S0 FET

Rds(on)

Type

MOSFET

P-Channel

1.274 A (EDP)

N-Channel

SI2312BDS

3.25 A @85C

0.140 A (EDP)

MOSFET

Rds(on)

Loading

ID(max)

Type

37 mOhm @2.5V

Q7990

4

3

6

5

2

1

Q7910FDC638P_G

SM

CRITICAL

B1

A1

B2

A2

C2

C1

U7980TPS22924

CRITICAL

CSP

2

1C7980OMIT_TABLE

10%6.3VCERM402

1UF

2

1C7991

X5R10V10%

0.01UF

201

2

1

3

Q7990CRITICAL

SI2312BDSSOT23

2

1C799010%

X5R6.3V

0.1UF

201

12

6Q7991SSM6N37FEAPE

SOT563

21

R7990

5%

100K

MF1/20W

201

21

R7991

201

1/20WMF

10K

1%

2

1R799269.8K

1%

MF1/20W

201

45

3Q7991SSM6N37FEAPE

SOT563

2

1 C79110.033UF16VX5R402

10%

57

32

1

4

87

65

Q7930TPCP810223V1K-SM

CRITICAL

4

3

6521

Q7940CRITICAL

FDC638P_GSM

21

R791047K

201MF

1/20W5%

2

1R7912

201MF

1/20W5%

10K

21

C79300.01UF

10%

X5R201

10V

2

1 C793110%16VX5R402

0.033UF

21

R7930

201MF

1/20W

47K

5%

2

1R7932100K

201MF

1/20W5%

57

57

21

3

Q7903SSM3K15FV

SOD-VESM-HF

21

3

Q7905SOD-VESM-HF

SSM3K15FV

21

C7940

10%16VCERM402

0.01UF

2

1C794110%16VX5R402

0.033UF

21

C7910

201

10VX5R

10%

0.01UF

21

R7940

MF1/20W

201

47K

5%

2

1R7942

MF1/20W

201

5%47K

21

3

Q7945SOD-VESM-HF

SSM3K15FV

57

57


Power FETs

P0V9ENET_SS

P0V9ENET_EN_L

P0V9ENET_EN_L_RC

=PP0V9_ENET_P0V9ENETFET

=P0V9ENET_EN

=PP3V3_S5_P0V9ENETFET

=PP0V9_ENET_FET

=PP3V3_S3_FET

P5VS0_EN_L

=P3V3S3_EN

=P3V3S0_EN

=P5VS0_EN

P3V3S3_EN_L

=PP3V3_S0_FET

=PP3V3_S5_P3V3S0FET

P3V3S0_EN_L

P5VS0_SS

=PP5V_S3_P5VS0FET

=PP5V_S0_FET

P3V3S3_SS

P3V3S0_SS

=PP3V3_ENET_FET

=P3V3ENET_EN

=PP3V3_S5_P3V3ENETFET=PP3V3_S5_P3V3S3FET

79 OF 110

4.4.0

051-8379

58 OF 73

8

8

8

8

8

8

8

8

9 8

8

GND THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

BI

BI

BI

IN

SYM_VER-2

SYM_VER-2

NC




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

DisplayPort I/F

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

(DP_INT_AUX_CH_C_N)

LED Backlight I/F

Internal DP Connector: 518S0787LCD Connector

Pull-ups on panel side,4.7 kOhm to 3.3V

(DP_INT_AUX_CH_C_P)

2

1 C901210UF

603X5R6.3V20%

OMIT_TABLE

2

1C901110%

6.3VX5R201

0.1UF

2

1R90141K5%

1/20WMF201

2

1 C90090.1UF

201X5R6.3V10%

5

4

3

2

7

1

6

U9000MFET-2X2

FPF1009

CRITICAL

2

1C90175%50V

C0G-CERM603

1000PF

PLACEMENT_NOTE=PLACE CLOSE TO J9000

2

1C901510%16VX7R201

1000PF

21

C90240.1uF

402X5R16V10%

21

C9025

10%16VX5R402

0.1uF

21

C9020

10%16VX5R402

0.1uF

21

C90210.1uF

402X5R16V10%

21

C90220.1uF

402X5R16V10%

21

C9023

10%16VX5R402

0.1uF

9

8

7

6

5

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J9000F-RT-SM

CRITICAL

CABLINE-CA

2

1R9050100K

5%1/20W

MF201

21

R9060

201

5%

MF1/20W

0

2

1R9080100K5%1/20WMF201

2

1R9070100K

MF201

1/20W5%

9

7 62

7 62

7 62

7 62

7 62

7 62

9 71

9 71

9 71

9 71

9 17

9 71

9 71

7 41

7 41

4

32

1

FL9000CRITICAL

TCM1210-4SM12-OHM-100MA

4

32

1

FL9001TCM1210-4SM12-OHM-100MA

CRITICAL

21

L9004

0402-LF

FERR-120-OHM-1.5A


Internal DisplayPort Connector

DP_INT_AUX_CH_C_PDP_INT_AUX_CH_C_N

DP_INT_ML_F_N<1>

DP_INT_HPD

DP_INT_ML_C_P<1>

DP_INT_ML_C_N<0>

DP_INT_ML_F_N<0>

DP_INT_ML_P<0>

=I2C_TCON_SCL

=I2C_TCON_SDA

PP3V3_SW_LCD_UFMIN_LINE_WIDTH=0.30 MMMIN_NECK_WIDTH=0.20 MMVOLTAGE=3.3V

DP_INT_ML_F_P<1>

DP_INT_ML_C_N<1>

DP_INT_ML_C_P<0>

MIN_LINE_WIDTH=0.30 MMMIN_NECK_WIDTH=0.20 MMVOLTAGE=3.3V

PP3V3_SW_LCD

DP_INT_HPD_CONN

LED_RETURN_4LED_RETURN_3

LED_RETURN_5

=PP3V3_S0_LCD

DP_INT_AUX_CH_N

DP_INT_AUX_CH_P

DP_INT_ML_N<0>

DP_INT_ML_P<1>

DP_INT_ML_N<1>

LCD_IG_PWR_EN

LED_RETURN_2

DP_INT_ML_F_P<0>

LED_RETURN_1

LED_RETURN_6

PPVOUT_SW_LCDBKLT

90 OF 110

4.4.0

051-8379

59 OF 73

7 71

7 71

7 71

71

71

7 71

7 71

71

71

7

7

8

7 71

7 42 62

IN

D SG

DSG

D SG

DSG

BI

BIBI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: Pulled up to 5V on DP connector page.

(DP_CA_DET_RC)

FET spec’ed for 1.5V Vgs operaiton.

21

C9300

X5R

10%

0.1UF

6.3V

201

21

C9301

201

6.3VX5R

10%

0.1UF

9

45

3

Q9302SIGNAL_MODEL=DP_AUXCH_FET

SOT563SSM6N37FEAPE

12

6


SSM6N37FEAPESOT563

45

3

Q9300SSM6N37FEAPE

SOT563

SIGNAL_MODEL=DP_AUXCH_FET

CKPLUS_WAIVE=PdifPr_badTerm

12

6


CKPLUS_WAIVE=PdifPr_badTerm

SOT563SSM6N37FEAPE

9

9 9

9

2

1C9302

201

3300PF10%10VX7R

21

R9302

MF1/20W5%

201

22

External DisplayPort SupportSYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

DP_EXT_AUX_CH_N

DP_CA_DET

DP_AUX_CH_C_P

DP_EXT_DDC_DATA

DP_CA_DET_RC

DP_AUX_CH_C_N

DP_EXT_DDC_CLK

DP_EXT_AUX_CH_P

93 OF 110

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BI

IO

NC

NC

IO

NC

IO

IO

NC

GND

GND

DP_PWR

AUX_CHPGND

RETURN

ML_LANE3PGND

ML_LANE3N

GND

ML_LANE1P

ML_LANE2N

ML_LANE2P

ML_LANE1N

GND

CONFIG1

HOT_PLUG_DETECT

ML_LANE0P

ML_LANE0N

AUX_CHN

CONFIG2

SHIELD PINS

OUT

SYM_VER-2IN

SYM_VER-2

SYM_VER-2

SYM_VER-2

IN

IO

NC NC

IO

GND

OUT

IO

NC NC

IO

GND

IN

IN

IN

IN

IN

IN

G

D

S

G

D

S

OUT

G

D

S

G

D

S

BI

IN

IN

OC*

OUT

EN

GND




36

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SHEET

PAGE TITLE

C

A

D

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Apple Inc.

PAGE


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B

C

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D

B

8 7 5 4 2 1

(CA) has 100kpull-up to DP_PWR.

to 100K (DPv1.1a).greater than or equaldown HPD input withDP Source must pull

Port Power Switch

Cable AdapterDP to DVI/HDMI

NOTE: Q9440 must have Drain to Gate leakage of < 500 nA and gate to Source resistance of > 5 MOhm.

9 71

2

1 C940010%

201X5R10V

0.01UF

2

1C948020%

6.3V

603

22UF

X5R-CERM-1

OMIT_TABLE

1 2 4 5

3

D9410DP_ESD

RCLAMP0524P

CRITICAL

SLP2510P8

2

1C9487CRITICAL

100UF6.3V

POLY-TANTCASE-B2-SM

20%

19

10

12

15

17

9

11

3

5

22 21

2

14 13

8 7

1

20

6

4

16

18

J9400F-RT-TH

MINIDSPLYPRT-K99

CRITICAL

39

4

3 2

1

FL9403CRITICAL

12-OHM-100MATCM1210-4SM

9 71

4

32

1

FL9400CRITICAL

12-OHM-100MATCM1210-4SM

4

32

1

FL940112-OHM-100MA

CRITICAL

TCM1210-4SM

4

32

1

FL9402CRITICAL

TCM1210-4SM12-OHM-100MA

9 71

2

1R94215%

201MF

1/20W

100K

12

3

D9411DP_ESD

SLP2510P8RCLAMP0524P

CRITICAL

21C94150.1UF 6.3V10% 201X5R

21C9414X5R 2010.1UF 6.3V10%

9

21C9411201X5R0.1UF 6.3V10%

21C9410X5R 2010.1UF 6.3V10%

2

1R94205%

100K

201MF

1/20W

52

6

43

1

D9400RCLAMP0504F

SC70-6-1

DP_ESDCRITICAL

54

3

D9411DP_ESD

SLP2510P8

CRITICAL

RCLAMP0524P

2

1R9425

201

1/20WMF

1M5%

21C9417X5R0.1UF 6.3V10% 201

21C9416201X5R6.3V10%0.1UF

21C9413201X5R0.1UF 6.3V10%

21C9412201X5R0.1UF 6.3V10%

9 71

9 71

9 71

9 71

21

L9400

0603

FERR-120-OHM-3A

9 71

9 71

4

5

3

Q94402N7002DW-X-G

SOT-363

1

2

6

Q94402N7002DW-X-G

SOT-363

2

1R9443

201

1/20WMF

100K5%

2

1R9442

1/20WMF

100K

201

5%

9

1

2

6

Q94412N7002DW-X-G

SOT-363

4

5

3

Q94412N7002DW-X-G

SOT-363

2

1R94225%

MF1/20W

201

1M

2

1R94455%

1/20WMF201

10K

2

1R94445%

10K

201

1/20WMF

2

1R9423

201

1/20WMF

100K5%

9 71

39

2

1 C94810.1UF

201

10%

X5R6.3V 2

1 C9486OMIT_TABLE

603X5R

10UF20%6.3V

1

3

5

2

4

U9480TPS2051B

CRITICAL

SOT23

2

1C948510%

0.1UF

X5R201

6.3V


DisplayPort Connector

DP_EXT_ML_F_N<3>

DP_EXT_AUX_CH_C_P

PP3V3_SW_DPPWRMIN_LINE_WIDTH=0.50 MMMIN_NECK_WIDTH=0.20 MMVOLTAGE=3.3V

DP_CA_DET_Q

DP_EXT_ML_F_P<2>

DP_EXT_ML_F_N<1>DP_EXT_ML_F_P<3>

HDMI_CEC

=PP3V3_S5_DP_PORT_PWR

=DP_PWR_EN

DP_HPD_Q

DP_EXT_HPD_L

PP3V3_SW_DPILIM

PP3V3_SW_DPILIMMIN_LINE_WIDTH=0.50 MMMIN_NECK_WIDTH=0.20 MMVOLTAGE=3.3V

=PP3V3_S0_DPCONN

=PP3V3_S0_DPCONN

TP_DPPWR_OC_L

DP_EXT_ML_P<1>

DP_EXT_ML_N<1>

DP_EXT_HPD

DP_EXT_ML_P<3>

DP_EXT_ML_N<3>

DP_EXT_ML_N<0>

DP_EXT_ML_P<0>

DP_EXT_ML_N<2>

DP_EXT_ML_P<2>

DP_CA_DET_Q_L

=PP5VR3V3_S0_DPCADET

DP_EXT_CA_DET

DP_EXT_AUX_CH_C_N

DP_EXT_ML_C_N<3>

DP_EXT_ML_C_P<3>

DP_EXT_ML_F_P<0>DP_EXT_ML_F_N<0>

DP_EXT_ML_C_N<0>

DP_EXT_ML_F_P<1>

DP_EXT_ML_C_N<1>

DP_EXT_ML_C_P<1>

DP_EXT_ML_F_N<2>

DP_EXT_ML_C_N<2>

DP_EXT_ML_C_P<2>

DP_EXT_ML_C_P<0>

94 OF 110

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10 9 7 6

109

67

71

7

71

71

71

8

61

61

8 61

8 61

8

71

71

71

71

71

71

71

71

71

71

71

71

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

OUT1

FSET

GD

FILTER

ISET

PWM

EN

FAULT

THRM

GND_L

GND_SW

OUT6

VINVDDIO VLDO

FB

SW

OUT2

OUT4

OUT5

VSYNC

OUT3SCLK

SDA

GND_S

PAD

IN

IN

BI





36

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NO STUFF R9740, C9740, C9741, R9754

FOR LP8543:

I_LED=23.2mA

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.

10.2 ohm resistors for current

Addr: 0x58(Wr)/0x59(Rd)

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

measurement on LED strings.

STUFF R9741

Fpwm=9.62kHzsee spec for others

(EEPROM should set EN_I_RES=1)I_LED=369/Riset

2

1R9755

MF1/20W

5%

201

10K

21

R9741

201

1/20W5%

MF

10K

2

1 C9799

1210-1

50VX5R

10%10UF

2

1 C9797

X5R1210-1

50V10%10UF

21

L970122UH-2.5A

CRITICAL

IHLP2525CZ-SM

3 41 2

R97000.01

1WMF

0612

0.5%

CRITICAL

42 71

42 71

21

R9757

201MF

5%

0

1/20W

2

1C9712

25V10%

X5R805

10UF


CRITICAL

2

1 C9713


X5R402

25V10%0.1UF

2

1 C9796

50V

402

10%

X7R-CERM

220PF

PLACE_NEAR=U9701.21:3mm21

D9701SOD-123

RB160M-60G

CRITICAL

21

R97220

BKLT:PROD

MF-LF1/16W5%

402

21

R97210

5%

BKLT:PROD

1/16WMF-LF402

21

R9720

402MF-LF1/16W

BKLT:PROD

0

5%

7 59

7 59

21

R9753

201

5%1/20WMF

0

7 59

7 59

7 59

7 59

21

R9718

5%

0

1/16WMF-LF402

BKLT:PROD

21

R97190

1/16WMF-LF

BKLT:PROD

402

5%

21

R9717

5%

0

BKLT:PROD

1/16WMF-LF402

2

1R9715

1/20W

100K

201MF

1%

21

R9731

201

1%1/20WMF

200K

2

1 C97230.1UF10%

NO STUFF

402X5R25V

2

1C9710


10%25V

1UF

603-1X5R2

1C9711


0.1UF

201

6.3VX5R

10%

21

XW9710SM

19

22

23

8

25

24

11

10

2

18

17

16

14

13

12

3

1 9

15

6

5

20

21

7

4

U9701OMIT_TABLECRITICAL

LLP

LP8545SQX

2

1 C97140.01UF


0201X7R

10%10V

2

1R9703

201MF1/20W5%0

NO STUFF

2

1R9702

201

5%

MF1/20W

0

9 21

R970433

201MF

1/20W5%

2

1 C9704

NP0-C0G25V

33PF5%

201

2

1R9714

201

18.2K

MF1/20W1%

21

R9701

201MF

0

5%1/20W

41

41

2

1R97161%

90.9K

201

1/20WMF


LCD Backlight Driver

R9717,R9718,R9719 BKLT:ENG3 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM103S0198

3 R9720,R9721,R9722 BKLT:ENGRES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM103S0198

IC,LP8545,LED BKLT CTRLR,PRODUCTIO,LLP24353S2896 1 CRITICALU9701 PROJ:K16

IC,LP8545,LED BKLT CTRLR,LLP24,K99 VER U9701 CRITICAL1 PROJ:K99353S2967

TP_BKL_FAULT

BKL_EN

MIN_LINE_WIDTH=0.4 MMGND_BKL_SGNDMIN_NECK_WIDTH=0.2 MMVOLTAGE=0V

BKL_FSET

BKL_VSYNC_R

BKL_ISEN6


BKL_ISET

VOLTAGE=24VSWITCH_NODE=TRUEDIDT=TRUE


PPBUS_SW_LCDBKLT_PWR_SW


PPVIN_SW_BKL_RMIN_LINE_WIDTH=0.4 MM

PP5V_S0_BKL_VLDO

VOLTAGE=5V


VOLTAGE=12.6V

MIN_LINE_WIDTH=0.5mmPPBUS_SW_BKLMIN_NECK_WIDTH=0.25mm

=PP3V3_S0_BKL_VDDIO

BKL_FLTR

BKL_ISEN5


BKL_SDA

LCD_BKLT_PWMMIN_NECK_WIDTH=0.20 mm

LED_RETURN_3MIN_LINE_WIDTH=0.5 mm


LED_RETURN_4

LED_RETURN_2MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm


LED_RETURN_6

MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mmLED_RETURN_5

MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mmLED_RETURN_1

=I2C_BKL_1_SCL

=I2C_BKL_1_SDA

=PP5V_S0_BKL

PPBUS_SW_LCDBKLT_PWR

BKL_PWM

PPBUS_SW_LCDBKLT_PWR

ISNS_LCDBKLT_P

BKL_ISEN1MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mm


BKL_ISEN2


BKL_ISEN4


BKL_ISEN3

ISNS_LCDBKLT_N

BKL_SCL


VOLTAGE=24V

PPVOUT_SW_LCDBKLTMIN_NECK_WIDTH=0.2 MM

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62 63

62 63

7 42 59

IN

D

SG

D

SG

IN




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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

P-TYPE

FDC638APZ

PPBUS S0 LCDBkLT FET

LOADING

RDS(ON)

MOSFET

43 mOhm @4.5V

0.4 A (EDP)

.

CHANNEL

2

1R9808

201MF1/20W1%301K

2

1R9809147K

201

1%

MF1/20W

2

1C98020.1UF

10%16VX5R402

4

3

65

21

Q9806CRITICAL

FDC638APZ_SBMS001SSOT6-HF

25

12

6Q9807SSM6N37FEAPE

SOT563

45

3Q9807SSM6N37FEAPE

SOT563

2

1R981010K

201

1/20W5%

MF

21

F9800CRITICAL

2AMP-32V

0603

9

LCD Backlight SupportSYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

=PPBUS_S0_LCDBKLT

LCDBKLT_EN_DIV

LCDBKLT_DISABLE

BKLT_PLT_RST_L

LCD_BKLT_EN

VOLTAGE=8.4V

PPBUS_SW_LCDBKLT_PWRMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.4 mm

LCDBKLT_EN_L


PPBUS_S0_LCDBKLT_FUSEDMIN_LINE_WIDTH=0.4 mm

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C

A

D

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Apple Inc.

PAGE


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B

C

345678

D

B

8 7 5 4 2 1

40x 1uF 0402ADDITIONAL CPU VCORE HF DECOUPLING

LAYOUT NOTE:

LAYOUT NOTE:




LAYOUT NOTE:

LAYOUT NOTE:


C9909OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9908

OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9907

OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9906

OMIT_TABLE

402-LF

CRITICAL

6.3V2.2UF20%CERM

C9905OMIT_TABLE

2.2UF6.3V20%

402-LFCERM

CRITICALC99042.2UF

OMIT_TABLE

6.3V20%

402-LFCERM

CRITICALC9903CRITICAL

2.2UF

OMIT_TABLE

6.3V20%

402-LFCERM

C9902OMIT_TABLECRITICAL

2.2UF6.3V20%

402-LFCERM

C9901OMIT_TABLE

2.2UF

CRITICAL

6.3V20%

402-LFCERM

C9900OMIT_TABLE

2.2UF6.3V20%

402-LFCERM

CRITICAL

C9919OMIT_TABLE

2.2UF6.3V20%

402-LFCERM

CRITICALC9918

OMIT_TABLECRITICAL

CERM6.3V2.2UF20%

402-LF

C9917OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9916OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9915

402-LF

OMIT_TABLE

6.3V2.2UF20%CERM

CRITICALC9914CRITICAL

2.2UF

OMIT_TABLE

6.3V20%

402-LFCERM

C9913OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9912

OMIT_TABLE

CERM

CRITICAL

6.3V2.2UF20%

402-LF

C9911OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9910

OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICAL

C9929OMIT_TABLECRITICAL

6.3V2.2UF20%

402-LFCERM

C99282.2UF

402-LF

OMIT_TABLE

6.3V20%CERM

CRITICALC9927

OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9926

OMIT_TABLE

2.2UF6.3V20%

402-LFCERM


6.3V2.2UF20%

402-LFCERM


6.3V2.2UF20%

402-LFCERM

CRITICALC9923

OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9922

OMIT_TABLE

2.2UF6.3V20%

402-LFCERM

CRITICALC9921

OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9920

OMIT_TABLE

CERM402-LF6.3V2.2UF20%

CRITICAL

C9939OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9938

OMIT_TABLE

6.3V2.2UF20%

402-LFCERM


6.3V2.2UF20%

402-LFCERM

CRITICALC9936

OMIT_TABLE

6.3V2.2UF20%

402-LFCERM


6.3V2.2UF20%

402-LFCERM

CRITICALC9934OMIT_TABLECRITICAL

6.3V2.2UF20%

402-LFCERM

C9933OMIT_TABLE

6.3V2.2UF20%

402-LFCERM

CRITICALC9932

OMIT_TABLECRITICAL

6.3V2.2UF20%

402-LFCERM

C9931OMIT_TABLE

6.3V2.2UF20%

402-LFCERM


6.3V2.2UF20%

402-LFCERM

CRITICAL


Additional CPU/GPU Decoupling

=PPVCORE_S0_CPU

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MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM


LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD






36

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C

A

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PAGE


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8 7 5 4 2 1





TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM


























Signals within each 4x group should be matched within 5 ps of strobe.FSB 4X signals / groups shown in signal table on right.

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 135 ps.Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 270 ps.Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

Intel Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

SR DG recommends at least 25 mils, >50 mils preferred

Some signals require 27.4-ohm single-ended impedance.Most CPU signals with impedance requirements are 55-ohm single-ended.

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

ELECTRICAL_CONSTRAINT_SET

CPU / FSB Net Properties

FSB 2X signals / groups shown in signal table on right.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

FSB Clock Constraints

CPU Signal Constraints

MCP FSB COMP Signal ConstraintsSOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4


FSB (Front-Side Bus) ConstraintsPHYSICAL

FSB 4X Signal Groups

SPACING

NET_TYPE

Signals

FSB 2X

FSB 1X Signals

FSB 1X signals shown in signal table on right.

(See above)

(FSB_CPURST_L)

(CPU_VCCSENSE)(CPU_VCCSENSE)

=4x_DIELECTRICFSB_DATA ?TOP,BOTTOM

=STANDARD=STANDARD*FSB_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

* =1:1_DIFFPAIR =1:1_DIFFPAIRFSB_DSTB_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

=4x_DIELECTRICCLK_FSB ?TOP,BOTTOM

8 MILCPU_8MIL ?*

?CPU_COMP * 25 MIL

CPU_AGTL ?* =STANDARD

25 MILCPU_GTLREF * ?

=3x_DIELECTRIC ?CLK_FSB *

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF*CLK_FSB_100D

8 MIL* ?MCP_FSB_COMP

CPU_ITP * ?=2:1_SPACING

MCP_50S =50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE* =STANDARD=STANDARD

?FSB_ADDR * =STANDARD

=2x_DIELECTRIC*FSB_DATA ?

*FSB_DSTB ?=3x_DIELECTRIC =5x_DIELECTRIC ?FSB_DSTB TOP,BOTTOM

=3x_DIELECTRIC ?FSB_ADDR TOP,BOTTOM

=3x_DIELECTRIC ?TOP,BOTTOMFSB_1X


CPU/FSB Constraints

25 MIL ?CPU_VCCSENSE *

CPU_AGTL ?=2x_DIELECTRICTOP,BOTTOM

=27P4_OHM_SE=27P4_OHM_SE* =27P4_OHM_SE =27P4_OHM_SE 7 MIL7 MILCPU_27P4S

* =STANDARD =STANDARDCPU_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

*FSB_1X =STANDARD ?

TOP,BOTTOM ?FSB_ADSTB =4x_DIELECTRICFSB_ADSTB ?* =2x_DIELECTRIC

CPU_55S CPU_AGTL CPU_STPCLK_LCPU_ASYNC

CPU_55S PM_THRMTRIP_LCPU_8MILPM_THRMTRIP_L

FSB_CLK_ITP CLK_FSB FSB_CLK_ITP_PCLK_FSB_100D

CPU_55SXDP_TRST_L CPU_ITP XDP_TRST_L

MCP_FSB_COMPMCP_50S MCP_CPU_COMP_VCCMCP_CPU_COMP

MCP_50S MCP_BCLK_VML_COMP_VDDMCP_CPU_COMP MCP_FSB_COMP

CPU_VCCSENSE IMVP6_VSEN_NCPU_27P4S

CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_PCPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_NCPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P

CPU_55S IMVP6_VID<6..0>CPU_8MIL

CPU_55S CPU_VID<6..0>CPU_8MIL

CPU_55SXDP_BPM_L5 CPU_ITP XDP_BPM_L<5>CPU_55S XDP_CPURST_LCPU_ITP

CPU_55SXDP_BPM_L XDP_BPM_L<4..0>CPU_ITP

CPU_55SXDP_TCK CPU_ITP XDP_TCK

CPU_55S XDP_TDOXDP_TDO CPU_ITP

CPU_55SXDP_TMS CPU_ITP XDP_TMS

CPU_55SPM_DPRSLPVR CPU_AGTL PM_DPRSLPVR

FSB_CLK_MCP CLK_FSBCLK_FSB_100D FSB_CLK_MCP_N

FSB_CLK_CPU FSB_CLK_CPU_NCLK_FSBCLK_FSB_100D

CLK_FSB_100DFSB_CLK_ITP CLK_FSB FSB_CLK_ITP_N

FSB_1X FSB_HIT_LFSB_1X FSB_55SFSB_HITM_LFSB_1XFSB_1X FSB_55S

CPU_55S CPU_SMI_LCPU_ASYNC CPU_AGTL

CPU_55SCPU_PWRGD CPU_AGTL CPU_PWRGDCPU_55S CPU_PROCHOT_LCPU_PROCHOT_L CPU_AGTL

CPU_55S CPU_FERR_LCPU_FERR_L CPU_8MIL

CPU_55S CPU_BSEL<2..0>CPU_AGTLCPU_BSEL

CPU_55S CPU_AGTL CPU_A20M_LCPU_ASYNC

FSB_TRDY_LFSB_1X FSB_1XFSB_55S

FSB_1X FSB_CPURST_LFSB_CPURST_L FSB_55S

FSB_LOCK_LFSB_1XFSB_1X FSB_55S

FSB_1X FSB_DRDY_LFSB_1X FSB_55S

FSB_BNR_LFSB_1XFSB_1X FSB_55S

FSB_ADDR_GROUP1 FSB_ADDR FSB_A_L<35..17>FSB_55S

FSB_DSTB0 FSB_DSTB FSB_DSTB_L_N<0>FSB_DSTB_55S

FSB_D_L<31..16>FSB_DATAFSB_DATA_GROUP1 FSB_55SFSB_DINV_L<1>FSB_DATAFSB_DATA_GROUP1 FSB_55S

FSB_D_L<63..48>FSB_DATAFSB_DATA_GROUP3 FSB_55S

FSB_DATA_GROUP3 FSB_DINV_L<3>FSB_DATAFSB_55SFSB_DSTB_L_P<3>FSB_DSTBFSB_DSTB3 FSB_DSTB_55S

FSB_DSTBFSB_DSTB3 FSB_DSTB_L_N<3>FSB_DSTB_55S

FSB_ADDRFSB_ADDR_GROUP0 FSB_A_L<16..3>FSB_55S

FSB_ADDR_GROUP0 FSB_REQ_L<4..0>FSB_ADDRFSB_55S

FSB_ADSTB FSB_ADSTB_L<1>FSB_ADSTB1 FSB_55S

FSB_ADS_LFSB_1X FSB_1XFSB_55SFSB_BREQ0_LFSB_BREQ0_L FSB_1XFSB_55S

FSB_ADSTB FSB_ADSTB_L<0>FSB_ADSTB0 FSB_55S

CPU_55S CPU_AGTL FSB_CPUSLP_LFSB_CPUSLP_L

FSB_DSTB0 FSB_DSTB_L_P<0>FSB_DSTBFSB_DSTB_55S

FSB_DINV_L<2>FSB_DATAFSB_DATA_GROUP2 FSB_55S

FSB_DSTB FSB_DSTB_L_P<1>FSB_DSTB1 FSB_DSTB_55S

FSB_DATA_GROUP0 FSB_DINV_L<0>FSB_DATAFSB_55S

FSB_DATA_GROUP0 FSB_D_L<15..0>FSB_DATAFSB_55S

FSB_DSTBFSB_DSTB2 FSB_DSTB_L_N<2>FSB_DSTB_55S

FSB_DSTB_L_P<2>FSB_DSTBFSB_DSTB2 FSB_DSTB_55S

FSB_DATA FSB_D_L<47..32>FSB_DATA_GROUP2 FSB_55S

FSB_DSTB1 FSB_DSTB FSB_DSTB_L_N<1>FSB_DSTB_55S

FSB_BPRI_LFSB_1XFSB_1X FSB_55S

FSB_1X FSB_DBSY_LFSB_1X FSB_55S

FSB_1X FSB_DEFER_LFSB_1X FSB_55S

FSB_1X FSB_RS_L<2..0>FSB_1X FSB_55S

CPU_GTLREFCPU_50SCPU_GTLREF CPU_GTLREF

MCP_50S MCP_CPU_COMP_GNDMCP_CPU_COMP MCP_FSB_COMP

CPU_55S CPU_AGTL IMVP_DPRSLPVR

FSB_CLK_CPU FSB_CLK_CPU_PCLK_FSBCLK_FSB_100D

CPU_55S CPU_AGTL FSB_DPWR_LCPU_ASYNC

CPU_55S CPU_AGTL CPU_DPRSTP_LCPU_DPRSTP_L

CPU_55S CPU_AGTL CPU_DPSLP_LCPU_FROM_SB

MCP_BCLK_VML_COMP_GNDMCP_50SMCP_CPU_COMP MCP_FSB_COMP

CPU_55SCPU_IERR_L CPU_IERR_L

CLK_FSB_100DFSB_CLK_MCP CLK_FSB FSB_CLK_MCP_P

CPU_55S CPU_ITPXDP_TDI XDP_TDI

CPU_27P4SCPU_COMP CPU_COMP CPU_COMP<0>CPU_50SCPU_COMP CPU_COMP<1>CPU_COMP

CPU_COMP CPU_COMP<2>CPU_27P4S CPU_COMP

CPU_50SCPU_COMP CPU_COMP<3>CPU_COMP

CPU_55S CPU_NMICPU_ASYNC_R CPU_AGTL

CPU_55S CPU_INTRCPU_ASYNC_R CPU_AGTL

CPU_55S CPU_INIT_LCPU_INIT_L CPU_AGTL

CPU_55S CPU_AGTL CPU_IGNNE_LCPU_ASYNC

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Apple Inc.

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345678

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8 7 5 4 2 1











AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM













































MEM_A/B_CKE EC SET NAME IS CHANGED ON K6, CANNOT SYNC THIS PAGE FROM T27

Memory Net PropertiesELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACINGPHYSICAL

Memory Bus Constraints

NV DG says 2x inner, 4x outer








Memory Bus Spacing Group Assignments

Need to support MEM_*-style wildcards!


MCP MEM COMP Signal ConstraintsSOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.3

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 360 ps

CMD/CTRL signals should be matched within 150 ps.CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.

DQ signals should be matched within 5 ps of associated DQS pair.DDR3:

All memory signals maximum length is 1.030 ps.

No DQS to clock matching requirement.

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SEMEM_50S =STANDARD* =STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SEMEM_55S =STANDARD* =STANDARD

=70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF* =70_OHM_DIFF =70_OHM_DIFFMEM_70D

MCP_MEM_COMP * =STANDARD =STANDARD=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

=2x_DIELECTRICMCP_MEM_COMP * ?

MEM_DQS2MEM*MEM_CLKMEM_DQS

MEM_DQS MEM_DQS2MEM*MEM_CTRL

* MEM_DQS2MEMMEM_DQS MEM_CMD

* MEM_DQS2MEMMEM_DQS MEM_DQS

MEM_DQS MEM_DQS2MEM*MEM_DATA

*MEM_DQS MEM_CTRL2MEMMEM_CTRL

*MEM_CLK MEM_CTRL2MEMMEM_CTRL

*MEM_CTRL MEM_CTRL2CTRLMEM_CTRL

* MEM_CTRL2MEMMEM_DATAMEM_CTRL

MEM_CTRL2MEM*MEM_CMDMEM_CTRL

*MEM_CLK MEM_CLK2MEMMEM_DQS

MEM_CLK2MEMMEM_CLK *MEM_DATA

* MEM_CLK2MEMMEM_CLKMEM_CLK

* MEM_CLK2MEMMEM_CTRLMEM_CLK

*MEM_CLK MEM_CLK2MEMMEM_CMD

MEM_2OTHER**MEM_DATA

**MEM_DQS MEM_2OTHER

* *MEM_CMD MEM_2OTHER

* *MEM_CLK MEM_2OTHER

**MEM_CTRL MEM_2OTHER

* MEM_DATA2DATAMEM_DATAMEM_DATA

MEM_DQS *MEM_DATA MEM_DATA2MEM

MEM_CMD *MEM_DATA MEM_DATA2MEM

MEM_CTRL MEM_DATA2MEM*MEM_DATA

MEM_CLKMEM_DATA MEM_DATA2MEM*

MEM_DQS *MEM_CMD MEM_CMD2MEM

MEM_DATA MEM_CMD2MEMMEM_CMD *

MEM_CMD2CMDMEM_CMDMEM_CMD *

MEM_CLK MEM_CMD2MEM*MEM_CMD

MEM_CTRL MEM_CMD2MEMMEM_CMD *

?*MEM_2OTHER 25 MIL

=1.5:1_SPACING ?*MEM_DATA2DATA

*MEM_DQS2MEM =3:1_SPACING ?

?* =3:1_SPACINGMEM_DATA2MEM

=3:1_SPACING ?*MEM_CMD2MEM

?*MEM_CMD2CMD =1.5:1_SPACING

=4:1_SPACING ?*MEM_CLK2MEM

?* =2:1_SPACINGMEM_CTRL2CTRL

=2.5:1_SPACING ?*MEM_CTRL2MEM


Memory Constraints

MEM_55SMEM_A_DQ_BYTE7 MEM_DATA MEM_A_DQ<63..56>

MEM_50SMEM_A_CKE MEM_CTRL MEM_A_CKE<3..0>

MEM_50SMEM_B_CKE MEM_CTRL MEM_B_CKE<3..0>

MEM_50SMEM_A_CNTL MEM_A_CS_L<3..0>MEM_CTRL

MEM_50SMEM_A_CMD MEM_CMD MEM_A_BA<2..0>MEM_50SMEM_A_CMD MEM_CMD MEM_A_RAS_L


MEM_55SMEM_A_DQ_BYTE6 MEM_A_DQ<55..48>MEM_DATA


MEM_55SMEM_A_DQ_BYTE4 MEM_DATA MEM_A_DM<4>

MEM_55SMEM_A_DQ_BYTE6 MEM_A_DM<6>MEM_DATA

MEM_A_DQS4 MEM_DQS MEM_A_DQS_N<4>MEM_70D


MEM_A_DQS7 MEM_70D MEM_DQS MEM_A_DQS_P<7>

MEM_B_CLK MEM_70D MEM_B_CLK_N<5..0>MEM_CLK

MEM_50SMEM_B_CNTL MEM_CTRL MEM_B_CS_L<3..0>

MEM_70D MEM_DQS MEM_A_DQS_P<5>MEM_A_DQS5

MEM_A_DQS3 MEM_70D MEM_DQS MEM_A_DQS_P<3>


MEM_50SMEM_A_CNTL MEM_A_ODT<3..0>MEM_CTRL

MEM_50SMEM_A_CMD MEM_A_A<15..0>MEM_CMD

MEM_50SMEM_A_CMD MEM_CMD MEM_A_CAS_LMEM_50SMEM_A_CMD MEM_A_WE_LMEM_CMD







MEM_DQSMEM_70DMEM_B_DQS0 MEM_B_DQS_P<0>MEM_DQS MEM_B_DQS_N<0>MEM_B_DQS0 MEM_70D

MEM_A_DQS7 MEM_A_DQS_N<7>MEM_DQSMEM_70D

MEM_B_CLK MEM_70D MEM_B_CLK_P<5..0>MEM_CLK

MEM_70D MEM_CLKMEM_A_CLK MEM_A_CLK_P<5..0>MEM_70D MEM_CLKMEM_A_CLK MEM_A_CLK_N<5..0>



MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS_N<0>

MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS_N<1>MEM_DQSMEM_A_DQS1 MEM_A_DQS_P<1>MEM_70D




MEM_70D MEM_DQS MEM_A_DQS_N<3>MEM_A_DQS3

MEM_70D MEM_DQS MEM_A_DQS_N<5>MEM_A_DQS5

MEM_A_DQS6 MEM_DQS MEM_A_DQS_P<6>MEM_70D

MEM_55S MEM_DATA MEM_B_DQ<47..40>MEM_B_DQ_BYTE5




MEM_50S MEM_CMD MEM_B_WE_LMEM_B_CMD





MEM_55S MEM_DATA MEM_B_DM<0>MEM_B_DQ_BYTE0

MEM_50S MEM_CMD MEM_B_BA<2..0>MEM_B_CMD

MEM_DQSMEM_70D MEM_B_DQS_N<6>MEM_B_DQS6

MEM_DQSMEM_70D MEM_B_DQS_P<7>MEM_B_DQS7




MEM_DQS MEM_B_DQS_N<4>MEM_70DMEM_B_DQS4
















MEM_50S MEM_CTRLMEM_B_CNTL MEM_B_ODT<3..0>

MCP_MEM_COMP_VDDMCP_MEM_COMPMCP_MEM_COMP MCP_MEM_COMPMCP_MEM_COMP_GNDMCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MEM_50S MEM_CMD MEM_B_CAS_LMEM_B_CMD

MEM_50S MEM_CMD MEM_B_RAS_LMEM_B_CMD

MEM_50S MEM_B_A<15..0>MEM_CMDMEM_B_CMD


MEM_A_DQS0 MEM_A_DQS_P<0>MEM_70D MEM_DQS

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SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.6Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3.

Max trace length: LVDS 10 inches, DP 8.5 inches.DisplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

SATA intra-pair matching should be 1 ps.

NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm.DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 100 ps.

LVDS intra-pair matching should be 5 mils. Pairs should be matched within 100 mils.


SATA Interface Constraints

R/G/B signals should be matched as close as possible and < 10 inches.

CRT signal single-ended impedence varies by location:

- 50-ohm from first to second termination resistor.

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1.

NEED PCIe Gen1/Gen2 notes!

Digital Video Signal Constraints

- 37.5-ohm from MCP to first termination resistor.

- 75-ohm from output of three-pole filter to connector (if possible).

Analog Video Signal Constraints



MCP89 Net PropertiesNET_TYPENET_TYPE

SPACINGPHYSICAL

PCI-Express

PCIE_90D =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF* =90_OHM_DIFF=90_OHM_DIFF

PCIE ?TOP,BOTTOM =4X_DIELECTRIC

20 MILCLK_PCIE ?*

8 MILMCP_PEX_COMP ?*

PCIE =3X_DIELECTRIC ?*

=100_OHM_DIFF=100_OHM_DIFFCLK_PCIE_100D =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFF


MCP Constraints 1

CRT_2CRT*CRTCRT

CRT_50S =50_OHM_SE =STANDARD* =STANDARD=50_OHM_SE=50_OHM_SE =50_OHM_SE

CRT * ?20 MIL

TOP,BOTTOM =4x_DIELECTRIC ?DISPLAYPORT

?LVDS =4x_DIELECTRICTOP,BOTTOM

CRT_2CRT ?* 15 MIL

?*CRT_2CLK 50 MIL

MCP_DAC_COMP * ?=2x_DIELECTRIC

CRT_SYNC ?* =4x_DIELECTRIC

* ?CRT_2SWITCHER 250 MIL

?*LVDS =3x_DIELECTRIC

=100_OHM_DIFFLVDS_100D * =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF

SATA ?TOP,BOTTOM =4x_DIELECTRIC

* ?SATA_TERMP 8 MIL

?SATA * =3x_DIELECTRIC

*SATA_90D =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=3x_DIELECTRIC* ?DISPLAYPORT

* Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARDMCP_DV_COMP

DP_90D =90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF*

DP_90D DP_IG_ML0_P<3..0>DISPLAYPORTDP_EXT_ML

DP_90D DISPLAYPORT DP_IG_AUX_CH0_PDP_EXT_AUX_CHDP_IG_AUX_CH0_NDISPLAYPORTDP_90DDP_EXT_AUX_CH

MCP_DV_COMPMCP_TMDS0_RSET MCP_TMDS0_RSET

DP_INT_ML DP_90D DP_IG_ML1_P<1..0>DISPLAYPORT

DP_INT_ML DISPLAYPORTDP_90D DP_IG_ML1_N<1..0>

DP_IG_ML0_N<3..0>DP_90D DISPLAYPORTDP_EXT_ML

LVDS_100DLVDS_IG_A_CLK LVDS_IG_A_CLK_PLVDS

LVDS_IG_A_DATA LVDS_100D LVDS_IG_A_DATA_P<2..0>LVDS

LVDS LVDS_IG_A_DATA_P<3>LVDS_100DLVDS_IG_A_DATA3

LVDS_100D LVDS_IG_A_DATA_N<3>LVDSLVDS_IG_A_DATA3

MCP_TMDS0_VPROBEMCP_TMDS0_VPROBE

LVDS_IG_A_CLK_NLVDSLVDS_100DLVDS_IG_A_CLK

LVDS_IG_B_CLK_PLVDSLVDS_IG_B_CLK LVDS_100DLVDS_IG_B_CLK_NLVDSLVDS_100DLVDS_IG_B_CLK

PCIEPCIE_90D PCIE_ENET_D2R_NPCIEPCIE_90D PCIE_ENET_D2R_C_PPCIEPCIE_90D PCIE_ENET_D2R_C_N

PCIEPCIE_90D PCIE_FW_R2D_P

PCIE_FW_R2D PCIE_FW_R2D_C_PPCIEPCIE_90D

PCIEPCIE_90D PCIE_FW_R2D_C_NPCIE_FW_D2R PCIE_FW_D2R_PPCIEPCIE_90D

PCIE_FW_D2R_NPCIEPCIE_90D

PCIE_FW_D2R_C_NPCIEPCIE_90D

CLK_PCIE PEG_CLK100M_PCLK_PCIE_100DMCP_PE0_REFCLKPEG_CLK100M_NCLK_PCIECLK_PCIE_100D

CLK_PCIE PCIE_CLK100M_AP_NCLK_PCIE_100D

CLK_PCIE PCIE_CLK100M_ENET_PCLK_PCIE_100DMCP_PE2_REFCLK

CLK_PCIE PCIE_CLK100M_ENET_NCLK_PCIE_100D

CRT_IG_R_C_PRCRTCRT_50SCRT_RED

CRT_50S CRT_IG_G_Y_YCRTCRT_GREEN

CRT_50S CRT CRT_IG_B_COMP_PBCRT_BLUE

PCIE_CLK100M_FW_NCLK_PCIE_100D CLK_PCIE

PCIE_FW_D2R_C_PPCIEPCIE_90D

PCIE_90D PCIE PEG_D2R_N<15..0>

PEG_D2R_C_N<15..0>PCIEPCIE_90D

PCIE_AP_R2D_C_PPCIE_AP_R2D PCIE_90D PCIE

MCP_SATA_TERMPSATA_TERMPMCP_SATA_TERMP

SATA SATA_ODD_D2R_C_PSATA_90DSATA_ODD_D2R_C_NSATASATA_90D

SATA SATA_ODD_D2R_NSATA_90D

SATA_ODD_D2R_PSATASATA_ODD_D2R SATA_90D

SATA SATA_ODD_R2D_NSATA_90D

SATA SATA_ODD_R2D_C_NSATA_90D

SATA SATA_ODD_R2D_PSATA_90D

SATA_ODD_R2D_C_PSATASATA_ODD_R2D SATA_90D

SATA SATA_HDD_D2R_C_NSATA_90D

SATA SATA_HDD_D2R_C_PSATA_90D

SATA SATA_HDD_D2R_PSATA_HDD_D2R SATA_90D

SATA SATA_HDD_D2R_NSATA_90D

SATA SATA_HDD_R2D_NSATA_90D

SATA_HDD_R2D_PSATASATA_90D

SATA SATA_HDD_R2D_C_NSATA_90D

SATA_HDD_R2D_C_PSATASATA_HDD_R2D SATA_90D

MCP_IFPAB_VPROBEMCP_IFPAB_VPROBE

LVDSLVDS_100DLVDS_IG_B_DATA3 LVDS_IG_B_DATA_N<3>LVDSLVDS_100DLVDS_IG_B_DATA3 LVDS_IG_B_DATA_P<3>

LVDSLVDS_100DLVDS_IG_B_DATA LVDS_IG_B_DATA_P<2..0>

LVDS_100D LVDS_IG_A_DATA_N<2..0>LVDS_IG_A_DATA LVDS

DP_INT_AUX_CH DP_IG_AUX_CH1_NDP_90D DISPLAYPORT

PCIEPCIE_90D PCIE_ENET_R2D_N

PCIEPCIE_90D PCIE_ENET_D2R_PPCIE_ENET_D2R

PCIEPCIE_90D PCIE_ENET_R2D_P

PCIEPCIE_90D PCIE_ENET_R2D_C_N

PEG_D2R_C_P<15..0>PCIEPCIE_90D

PEG_R2D_C_P<15..0>PCIE_90D PCIEPEG_R2D

PEG_D2R_P<15..0>PCIE_90D PCIEPEG_D2R

PCIE_AP_R2D_NPCIEPCIE_90D

PCIE_90D PCIE PEG_R2D_C_N<15..0>

PCIEPCIE_90D PCIE_AP_R2D_P

MCP_IFPAB_RSET MCP_IFPAB_RSETMCP_DV_COMP

LVDS_100DLVDS_IG_B_DATA LVDS LVDS_IG_B_DATA_N<2..0>

MCP_PEX_COMP MCP_PEX0_TERMPMCP_PEX_CLK_COMP

CLK_PCIE PCIE_CLK100M_FW_PCLK_PCIE_100DMCP_PE3_REFCLK

PCIEPCIE_90D PCIE_ENET_R2D_C_PPCIE_ENET_R2D

PCIE_FW_R2D_NPCIEPCIE_90D

PCIE_CLK100M_AP_PCLK_PCIECLK_PCIE_100DMCP_PE1_REFCLK

PCIEPCIE_90D PCIE_AP_D2R_NPCIE_AP_D2R_PPCIE_AP_D2R PCIEPCIE_90D

PCIE_AP_R2D_C_NPCIEPCIE_90D

PEG_R2D_N<15..0>PCIE_90D PCIE

PCIE_90D PCIE PEG_R2D_P<15..0>

CRT_50S CRT_IG_VSYNCCRT_SYNCCRT_SYNC

MCP_TV_DAC_VREFMCP_DAC_COMPMCP_DAC_VREF

CRT_IG_HSYNCCRT_SYNCCRT_50SCRT_SYNC

MCP_TV_DAC_RSETMCP_DAC_COMPMCP_DAC_RSET

DP_INT_AUX_CH DP_IG_AUX_CH1_PDP_90D DISPLAYPORT

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17 24

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9 16

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7 16 34

16 34

18

9 18

9 18

9

9 18

9

9 18

7 35

7 35

18 35

18 35

7 35

7 35

18 35

18 35

17 24

9 17

7 34

7 34

17 24

16

7 16 34

7 16 34

7 16 34

16 34

9 17




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MCP89 Net PropertiesNET_TYPE


SMBus Interface Constraints

USB 2.0 Interface Constraints

SPI Interface Constraints

HD Audio Interface Constraints

LPC Bus ConstraintsPHYSICAL SPACING


(SMBUS_SMC_MGMT_SCL)

(SMBUS_SMC_MGMT_SDA)

SIO Signal Constraints






USB_90D =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF* =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF

=STANDARD*LPC_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD=55_OHM_SE

=STANDARD =STANDARD=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SECLK_LPC_55S *

=1.5x_DIELECTRIC* ?LPC

=2x_DIELECTRIC ?*CLK_LPC

* ?USB =2x_DIELECTRIC

=55_OHM_SE* =STANDARD =STANDARDSMB_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE

=2x_DIELECTRIC ?*SMB

* =STANDARD=STANDARDHDA_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

?* 8 MILMCP_HDA_COMP

=2x_DIELECTRICHDA * ?

=STANDARD =STANDARDCLK_SLOW_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE*

=1.5x_DIELECTRIC*CLK_SLOW ?

=STANDARD=STANDARD* =55_OHM_SE =55_OHM_SE =55_OHM_SESPI_55S =55_OHM_SE

=1.5x_DIELECTRIC*SPI ?

8 MIL =STANDARD =STANDARD =STANDARD8 MIL=STANDARD*MCP_USB_RBIAS

USB ?TOP,BOTTOM =4x_DIELECTRIC

MCP Constraints 2SYNC_DATE=07/07/2010SYNC_MASTER=K16_MLB

SPISPI_55S SPI_ALT_CLK

SPI_55S SPI SPI_ALT_MISOSPI_55S SPI SPI_ALT_MOSI

SPISPI_55S SPI_ALT_CS_L

SPI_55S SPI SPI_MLB_CS_L

SPISPI_55S SPI_MLB_MOSISPI_55S SPI SPI_MLB_CLK

SPI_CS0_LSPI_55S SPI

SPISPI_55S SPI_MOSI

SPI_CLKSPISPI_55S

HDA_55S HDA HDA_RST_R_LHDA_RST_L

HDA_55S HDA HDA_RST_L

SPI_55S SPISPI_MOSI SPI_MOSI_R

SPISPI_55SSPI_CS0 SPI_CS0_R_L

HDA_SDIN_CODECHDA_55S HDA

HDA_55SHDA_SDOUT HDA HDA_SDOUTHDA HDA_SDOUT_RHDA_55S

PM_CLK32K_SUSCLK_RCLK_SLOWCLK_SLOW_55SMCP_SUS_CLK

USB USB_EXTC_NUSB_90D

USBUSB_90D USB_SDCARD_N

USB_90D USBUSB_EXTC USB_EXTC_P

USBUSB_90D USB_T57_PUSB_T57

USB_CAMERA_NUSB_90D USBUSB_BT_PUSB_BT USBUSB_90D

USB_TPAD USB_TPAD_PUSB_90D USBUSB_TPAD_NUSB_90D USB

USB_IR USB_90D USB USB_IR_PUSB_IR_NUSBUSB_90DUSB_EXTB_PUSB_EXTB USBUSB_90DUSB_EXTB_NUSBUSB_90D

USB_90D USB USB_T57_N

USB_90D USB USB_WM_N

HDA_55S HDAHDA_BIT_CLK HDA_BIT_CLK

HDA_55S HDA HDA_SYNC_R

HDA_SDIN0HDA_55S HDAHDA_SDIN0

USB_CAMERA_PUSBUSB_CAMERA USB_90D

USB_BT_NUSBUSB_90D

USB_90D USB_EXTD_NUSB

USB_EXTD USB_90D USB_EXTD_PUSB

USB_90D USB USB_MINI_N

USB_EXTA_MUXED_NUSBUSB_90DUSB_MINI_PUSB_MINI USB_90D USB

USB_EXTA_MUXED_PUSB_90D USB

USB_90D USB_EXTA_NUSB

USB_EXTA_PUSB_90D USBUSB_EXTA

LPC_CLK33M_LPCPLUSCLK_LPC_55S CLK_LPC

LPC_CLK33M_SMCCLK_LPC_55S CLK_LPC

LPC_CLK33M_SMC_RCLK_LPC_55S CLK_LPCMCP_LPC_CLK0

LPC_55SLPC_RESET_L LPC LPC_RESET_LLPC_55S LPCLPC_FRAME_L LPC_FRAME_L

LPCLPC_55S LPC_AD<3..0>LPC_AD

SPI_MISOSPI_55SSPI_MISO SPI

PM_CLK32K_SUSCLKCLK_SLOW_55S CLK_SLOW

MCP_HDA_PULLDN_COMP MCP_HDA_PULLDN_COMPMCP_HDA_COMP

HDA_55S HDA HDA_BIT_CLK_RHDA_55SHDA_SYNC HDA HDA_SYNC

SMB_55S SMB SMBUS_MCP_1_DATASMB_55S SMB SMBUS_MCP_1_CLKSMB_55SSMBUS_MCP_0_DATA SMB SMBUS_MCP_0_DATASMB_55SSMBUS_MCP_0_CLK SMBUS_MCP_0_CLKSMB

MCP_USB_RBIAS MCP_USB_RBIAS MCP_USB_RBIAS_GND

USB_90D USB USB_SDCARD_PUSB_SDCARD

USBUSB_90DUSB_WM USB_WM_P

SPI_55SSPI_CLK SPI_CLK_RSPI

SPISPI_55S SPI_MLB_MISO

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19

7 19 37

19 40

19 40

7 19 37

19

19 25

9 18

9 18

9 18

7 18 37

7 18 34

18 46 71

18 46 71

7 19 37

19

7 19 37

7 18 37

7 18 34

7 18 37

7 18 37

9 18

36 71

9 18

36 71

18 36

18 36

7 25 40

25 38

19 25

19 25

7 19 38 40

7 19 38 40

19 40

25 38

19

19

7 19 37

19 41

19 41

19 41

19 41

18

9 18

19 40

40 47










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SD Card Interface Constraints

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

BCM5764M/BCM57765 co-layout.



NET_TYPE

PHYSICAL

NET_TYPE

SPACING

NOTE: SD_D<7..5> are different to support

ELECTRICAL_CONSTRAINT_SET PHYSICAL

NET_TYPE

SPACING

RGMII Net Properties

SPACING

MCP RGMII (Ethernet) Constraints

SD Card Net Properties

PHYSICAL

Ethernet Net Properties

88E1116R (Ethernet PHY) ConstraintsSOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

=STANDARDMCP_MII_COMP * 7.5 MIL =STANDARD=STANDARD7.5 MIL =STANDARD

=55_OHM_SE =55_OHM_SE* =STANDARD=STANDARDENET_MII_55S =55_OHM_SE =55_OHM_SE

?=3:1_SPACINGMCP_BUF0_CLK *

ENET_MII * ?12 MIL

=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF* =100_OHM_DIFFENET_MDI_100D


Ethernet Constraints

25 MILENET_MDI * ?

SD_55S =55_OHM_SE=55_OHM_SE =55_OHM_SE =STANDARD=STANDARD=55_OHM_SE*

SD_INTERFACE =3X_DIELECTRIC ?*

ENET_RESET_LENET_MIIENET_MII_55S

ENET_MIIENET_MDIO ENET_MDIOENET_MII_55S

ENET_RXCLK ENET_CLK125M_RXCLK_RENET_MIIENET_MII_55S

ENET_MIIENET_MII_55SENET_RXD_STRAP ENET_RXD<3..1>ENET_MII_55S ENET_MIIENET_RXD ENET_RX_CTRL

ENET_MII ENET_RXD_R<3..0>ENET_MII_55S

ENET_CLK125M_RXCLKENET_MII_55S ENET_MII

ENET_MIIENET_TXD ENET_TXD<0>ENET_MII_55S

ENET_MII_55S ENET_TXD<3..1>ENET_MIIENET_TXD

ENET_INTR_L ENET_MII_55S ENET_INTR_LENET_MII

RTL8211_CLK25M_CKXTAL1MCP_BUF0_CLKENET_MII_55S

MCP_BUF0_CLKMCP_CLK25M_BUF0 MCP_CLK25M_BUF0_RENET_MII_55S

MCP_MII_COMP_VDDMCP_MII_COMP MCP_MII_COMPMCP_MII_COMP_GNDMCP_MII_COMP MCP_MII_COMP

ENET_MII ENET_MDCENET_MDC ENET_MII_55S

ENET_MII ENET_PWRDWN_LENET_PWRDWN_L ENET_MII_55S

ENET_MII_55S ENET_CLK125M_TXCLKENET_MIIENET_TXCLK

ENET_TX_CTRLENET_MII_55S ENET_MIIENET_TXD

ENET_MDIENET_MDI_100D ENET_MDI_N<3..0>ENET_MDI ENET_MDI_P<3..0>ENET_MDIENET_MDI_100D

SD_55S SD_INTERFACE SDCONN_DATA<4..0>SD_INTERFACESD_DATA SD_55S SD_D<4..0>

SD_55S SD_INTERFACE BCM57765_CR_DATA<4>

SD_D<7..5>SD_DATA_R SD_INTERFACESD_55S

SD_INTERFACESD_55S SDCONN_DATA<7..5>BCM57765_CR_DATA<7..5>SD_INTERFACESD_55S

SD_CLK SD_55S SD_INTERFACE SD_CLK

SD_55S SD_INTERFACE SDCONN_CLKSD_55S SD_INTERFACE SD_CLK_R

SD_55S SD_INTERFACE SDCONN_CMDSD_INTERFACESD_55SSD_CMD SD_CMD

BCM57765_CR_CMDSD_INTERFACESD_55S

ENET_RXD_STRAP ENET_MII ENET_RXD<0>ENET_MII_55S

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SMBus Charger Net Properties


NET_TYPE

PHYSICAL SPACING

SMC SMBus Net Properties

SPACINGPHYSICAL

NET_TYPE


SMC ConstraintsSYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010

=STANDARD =STANDARD 0.1 MM 0.1 MM* =STANDARD=STANDARD1TO1_DIFFPAIRSMB_55S SMBUS_SMC_A_S3_SCLSMBUS_SMC_A_S3_SCL SMB

SMBUS_SMC_MGMT_SDASMBUS_SMC_MGMT_SDA SMBSMB_55S

SMBUS_SMC_MGMT_SCLSMBSMB_55SSMBUS_SMC_MGMT_SCL

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SCLSMBSMB_55S

SMBUS_SMC_BSA_SDASMBUS_SMC_BSA_SDA SMBSMB_55S

SMBSMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCLSMB_55S

SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDASMBSMB_55S

SMBUS_SMC_B_S0_SDA SMB SMBUS_SMC_B_S0_SDASMB_55S

SMBUS_SMC_B_S0_SCL SMB SMBUS_SMC_B_S0_SCLSMB_55S

SMBUS_SMC_A_S3_SDA SMB_55S SMBUS_SMC_A_S3_SDASMB

CHGR_CSI 1TO1_DIFFPAIR CHGR_CSI_P

1TO1_DIFFPAIR CHGR_CSI_N

CHGR_CSI_R_P1TO1_DIFFPAIR

CHGR_CSO_R_N1TO1_DIFFPAIR

CHGR_CSO_N1TO1_DIFFPAIR

CHGR_CSO_P1TO1_DIFFPAIRCHGR_CSO

CHGR_CSI_R_N1TO1_DIFFPAIR

CHGR_CSO_R_P1TO1_DIFFPAIR

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41

41

41

7 41

7 41

41

41

41

41

50

50

50

43 50

50

50

50

43 50

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE























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SD CARD READER LAYOUT RELAXATIONS

MCP Fanout Constraint Relaxations

Graphics Net Properties

(DP_EXT_ML)

(DP_EXT_AUX_CH)

ELECTRICAL_CONSTRAINT_SET PHYSICAL

NET_TYPE

SPACING


Audio Net PropertiesPHYSICAL

NET_TYPE

SPACING

Power Net PropertiesELECTRICAL_CONSTRAINT_SET

(USB_EXTA)

(USB_EXTA)

PHYSICAL

Misc Net Properties

(USB_TPAD)

(USB_EXTA)

SPACING ELECTRICAL_CONSTRAINT_SET PHYSICAL

NET_TYPE

SPACING

NET_TYPE

(USB_TPAD)

(USB_TPAD)

(USB_TPAD)

(USB_EXTA)

=1:1_DIFFPAIR* =55_OHM_SESENSE_1TO1_55S =55_OHM_SE=55_OHM_SE =1:1_DIFFPAIR=1:1_DIFFPAIR

PWR_P2MMMEM_POWER *MEM_CLK

SB_POWER PWR_P2MMSATA *

SB_POWER PWR_P2MMUSB *

GND * GND_P2MMENET_MDI

PWR_P2MMMEM_POWER *MEM_CTRL

MEM_CLK GND_P2MM*GND

MEM_CMD GND_P2MM*GND

MEM_CTRL GND_P2MM*GND

MEM_DATA GND_P2MM*GND

* 10000.20 MMPWR_P2MM

10000.20 MM*GND_P2MM

MEM_POWER ?* =STANDARD

GND ?=STANDARD*

PCIE *GND GND_P2MM

GND_P2MMUSB *GND

SB_POWER PWR_P2MMCLK_PCIE *

GND_P2MMGND *LVDS

GND_P2MMCLK_PCIE *GND

GND_P2MMSATA *GND

MEM_DQS GND_P2MM*GND

GND_P2MMCPU_GTLREF *GND

GND_P2MMCPU_COMP *GND

GND_P2MM*GNDCLK_FSB

PWR_P2MMMEM_POWER *MEM_CMD

PWR_P2MMMEM_POWER *MEM_DATA

PWR_P2MMMEM_POWER *MEM_DQS

CPU_VCCSENSE *GND GND_P2MM

=1:1_DIFFPAIR=1:1_DIFFPAIR*DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR=1:1_DIFFPAIR*THERM_1TO1_55S =1:1_DIFFPAIR=55_OHM_SE =55_OHM_SE=55_OHM_SE

?25 MILS*ENETCONN

=1:1_SPACING*SENSE ?


K16/K99 Specific Constraints

=1:1_SPACING ?*AUDIO

=1:1_SPACING ?*THERM

0.1 MM 500 MILTOPMCP_MII_COMP

0.25 MM* 250 MILMCP_DV_COMP

0.1 MMTOPMCP_USB_RBIAS 500 MIL

MCP_MEM_COMP 0.1 MM 500 MILTOP

MCP_DV_COMP TOP 500 MIL0.1 MM

* 0.09 MM 5.8 MMMEM_40S

=STANDARDSD_55S *

USB_90D USB USB_TPAD_NMCPTHMSNS_D2 MLBR_THMDIODE_PTHERM_1TO1_55S THERM

THERM CPU_THERMD_PTHERM_1TO1_55SCPU_THERMD

DRAMTHMSNS_D2_PTHERM_1TO1_55S THERMCPUTHMSNS_D2DRAMTHMSNS_D2_NTHERM_1TO1_55S THERM

USB_TPAD_CONN_PUSB_90D USB

USB_EXTA_MUXED_NUSBUSB_90D

USB_LT1_NUSBUSB_90D

USB_90D USB_LT1_PUSB

USB USB_EXTA_MUXED_PUSB_90D

USB_90D USB USB_TPAD_P

USB_TPAD_CONN_NUSB_90D USB

THERM CPU_THERMD_NTHERM_1TO1_55S

MLBR_THMDIODE_NTHERM_1TO1_55S THERMMCP_THMDIODE_PTHERMTHERM_1TO1_55SMCP_THMDIODE

THERM MCP_THMDIODE_NTHERM_1TO1_55S

CPUVTTS0_CS_PSENSESENSE_1TO1_55SSENSE_DIFFPAIRCPUVTTS0_CS_NSENSESENSE_1TO1_55S

IMVP6_CS_R_NSENSESENSE_1TO1_55S

IMVP6_CS_PSENSESENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_1V5_S3_PSENSESENSE_DIFFPAIR SENSE_1TO1_55SISNS_1V5_S3_NSENSESENSE_1TO1_55S

ISNS_CSREG_PSENSESENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_AIRPORT_PSENSE_1TO1_55SSENSE_DIFFPAIR SENSEISNS_AIRPORT_NSENSE_1TO1_55S SENSE

ISNS_CSREG_NSENSE_1TO1_55S SENSE

SENSESENSE_DIFFPAIR SENSE_1TO1_55S ISNS_HDD_P

ISNS_LCDBKLT_NSENSESENSE_1TO1_55S

SENSESENSE_1TO1_55S ISNS_HDD_NISNS_LCDBKLT_PSENSESENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_DIFFPAIR CPU_VTTSENSE_PSENSE_1TO1_55S SENSECPU_VTTSENSE_NSENSESENSE_1TO1_55S

SENSE_DIFFPAIR SENSE_1TO1_55S MCPCORES0_VSEN_PSENSE

SENSESENSE_1TO1_55S MCPCORES0_VSEN_N

PP3V3_S5SB_POWERPP3V3_S0SB_POWERPP1V5_S0SB_POWER

SPKRAMP_INR SPKRAMP_INR_PDIFFPAIR AUDIO

MAX98300_R MAX98300_R_PAUDIODIFFPAIRMAX98300_R_NAUDIODIFFPAIR

I2C_SMC_SMS_SDA_RSMBUS_SMC_MGMT_SDA SMBSMB_55S

SMB_55S SMB I2C_SMC_SMS_SCL_RSMBUS_SMC_MGMT_SCL

DP_INT_ML_N<1..0>DISPLAYPORTDP_90D

DISPLAYPORTDP_90D DP_INT_ML_F_P<1..0>DISPLAYPORTDP_90D DP_INT_ML_F_N<1..0>DISPLAYPORT DP_INT_AUX_CH_C_PDP_90D

DP_INT_AUX_CH_NDISPLAYPORTDP_90D

DP_INT_AUX_CH_PDISPLAYPORTDP_90D

DISPLAYPORT DP_EXT_ML_P<3..0>DP_90DDP_EXT_ML_N<3..0>DISPLAYPORTDP_90D

DISPLAYPORT DP_EXT_ML_C_P<3..0>DP_90DDP_EXT_ML_C_N<3..0>DISPLAYPORTDP_90D

DP_90D DISPLAYPORT DP_EXT_ML_F_P<3..0>DP_90D DISPLAYPORT DP_EXT_ML_F_N<3..0>

DP_EXT_AUX_CH_C_PDP_90D DISPLAYPORT

DP_90D DP_EXT_AUX_CH_C_NDISPLAYPORT

I2C_TCON_SCLSMBSMB_55SI2C_TCON_SDASMB_55S SMB

I2C_TCON_SDA_CONNSMBSMB_55S

I2C_TCON_SCL_CONNSMB_55S SMB

DP_INT_ML_P<1..0>DISPLAYPORTDP_90D

DP_INT_ML_C_P<1..0>DISPLAYPORTDP_90D

DP_90D DISPLAYPORT DP_INT_ML_C_N<1..0>

SPKRAMP_INR_NDIFFPAIR AUDIO

DP_90D DISPLAYPORT DP_INT_AUX_CH_C_N

IMVP6_CS_NSENSESENSE_1TO1_55SIMVP6_CS_R_PSENSESENSE_1TO1_55SSENSE_DIFFPAIR

MEM_POWER PP1V5R1V35_S3

GNDGND

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44

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7 46

36 68

36

36

36 68

18 46 68

7 46

10 44

44

19 44

19 44

55

55

53

53

42 52

42 52

43

34 42

34 42

43

35 42

42 62

35 42

42 62

55

55

22 54

22 54

7 8 57

7 8 57

7 8 57

7 37 48

48

48

9 59

7 59

7 59

7 59

9 59

9 59

9 61

9 61

61

61

61

61

9 61

9 61

41

41

9 59

59

59

7 37 48

7 59

53

53

7 8




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TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS
































K99 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

0.350 MM5X_DIELECTRIC ?*

*1.5X_DIELECTRIC 0.105 MM ?

2X_DIELECTRIC 0.140 MM ?*

0.210 MM3X_DIELECTRIC ?*

0.280 MM*4X_DIELECTRIC ?

ISL4,ISL9 0.250 MM0.250 MM27P4_OHM_SE Y

TOP,BOTTOM 0.110 MM50_OHM_SE Y 0.110 MM

Y50_OHM_SE ISL3,ISL4,ISL9,ISL10 0.090 MM 0.090 MM

55_OHM_SE =STANDARD=STANDARD=STANDARD =STANDARDY =STANDARD*

40_OHM_SE 0.140 MMISL3,ISL4,ISL9,ISL10 Y 0.140 MM

=STANDARD50_OHM_SE =STANDARD* Y =STANDARD=STANDARD =STANDARD

0.3 MMBGA_P3MM * ?

0.2 MM*BGA_P2MM ?

0.1 MM ?*BGA_P1MM

0.130 MM0.130 MM0.155 MM0.155 MMISL4,ISL970_OHM_DIFF Y

55_OHM_SE ISL3,ISL4,ISL9,ISL10 Y 0.076 MM0.076 MM

ISL4,ISL980_OHM_DIFF 0.160 MM0.160 MM0.125 MM0.125 MMY

0.130 MM0.130 MM0.135 MM0.135 MMISL3,ISL10 Y70_OHM_DIFF

TOP,BOTTOM Y55_OHM_SE 0.090 MM 0.090 MM

0.170 MM40_OHM_SE 0.170 MMYTOP,BOTTOM

15.5.1NO_TYPE,BGA MMTOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

0.250 MM27P4_OHM_SE 0.250 MMYISL3,ISL10

TOP,BOTTOM 0.130 MM0.130 MM0.175 MM0.175 MM70_OHM_DIFF Y

70_OHM_DIFF =STANDARD=STANDARDY* =STANDARD=STANDARD=STANDARD

=STANDARD =STANDARDY =STANDARD*1:1_DIFFPAIR 0.1 MM 0.1 MM

0.200 MM0.085 MMY100_OHM_DIFF 0.085 MM 0.200 MMISL4,ISL9

0.105 MMY90_OHM_DIFF 0.105 MM 0.210 MM 0.210 MMISL4,ISL9

0.089 MMY90_OHM_DIFF 0.089 MM 0.210 MM 0.210 MMISL3,ISL10

=STANDARD =STANDARD=STANDARD=STANDARD* Y =STANDARD90_OHM_DIFF

0.140 MM 0.140 MM0.140 MM0.140 MM75_OHM_DIFF ISL4,ISL9 Y

0.105 MM0.105 MM95_OHM_DIFF ISL4,ISL9 0.210 MM0.210 MMY

0.115 MM95_OHM_DIFF 0.210 MM0.210 MM0.115 MMYTOP,BOTTOM

=STANDARD95_OHM_DIFF =STANDARDY* =STANDARD =STANDARD=STANDARD

95_OHM_DIFF ISL3,ISL10 0.210 MM0.210 MM0.089 MMY 0.089 MM

100_OHM_DIFF =STANDARD =STANDARD =STANDARD=STANDARD=STANDARD* Y

TOP,BOTTOM Y 0.115 MM 0.115 MM 0.210 MM 0.210 MM90_OHM_DIFF

0.160 MM0.160 MM0.109 MM0.109 MMISL3,ISL10 Y80_OHM_DIFF

80_OHM_DIFF 0.160 MM0.160 MM0.140 MM0.140 MMTOP,BOTTOM Y

80_OHM_DIFF =STANDARD* Y =STANDARD =STANDARD =STANDARD=STANDARD

* =DEFAULT =DEFAULT=DEFAULTY 12.7 MM =DEFAULTSTANDARD

*DEFAULT 0.076 MM 30 MM 0 MM 0 MMY 0.100 MM

75_OHM_DIFF =STANDARD=STANDARD =STANDARDY* =STANDARD =STANDARD

75_OHM_DIFF 0.160 MM0.160 MM0.160 MM0.160 MMTOP,BOTTOM Y

0.300 MM100_OHM_DIFF Y 0.075 MM 0.075 MM 0.300 MMISL3,ISL10

0.091 MMY100_OHM_DIFF TOP,BOTTOM 0.091 MM 0.200 MM 0.200 MM

Y75_OHM_DIFF 0.120 MM 0.140 MM0.140 MM0.120 MMISL3,ISL10

=STANDARD=STANDARD =STANDARD =STANDARDY =STANDARD*27P4_OHM_SE

=STANDARD=STANDARD* =STANDARDY =STANDARD=STANDARD40_OHM_SE

?* =STANDARDPP1V5_MEM

0.25 MM2.5:1_SPACING * ?

=STANDARDGND * ?

0.2 MM 1000GND_P2MM *

1000PWR_P2MM * 0.2 MM

?=STANDARDNB_STATIC *

1:1_SPACING * ?0.1 MM

1.5:1_SPACING ?* 0.15 MM

0.18 MM* ?1.8:1_SPACING

0.2 MM* ?2:1_SPACING

2.28:1_SPACING ?* 0.228 MM

0.3 MM3:1_SPACING * ?

4:1_SPACING * 0.4 MM ?

STANDARD * =DEFAULT ?

DEFAULT 0.1 MM ?*


K99 RULE DEFINITIONS

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DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICALDESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICALDESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL



DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL






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TAIYO YUDEN

MURATA TAIYO YUDEN

TAIYO YUDEN MURATA

TAIYO YUDEN MURATA

SAMSUNG

SAMSUNG

SAMSUNG

SAMSUNG

22UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS

10UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS

2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

MURATA 1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

3 CAP, 22UF, 6.3V, 20%, 0603 C1223,C1226,C1227 CRITICAL SS_CAP_22UF138S0635

4 C1210,C1214,C1217,C1218CAP, 22UF, 6.3V, 20%, 0603138S0635 SS_CAP_22UFCRITICAL

5 CAP, 22UF, 6.3V, 20%, 0603 C1230,C4902,C7360,C7361,C9480 SS_CAP_22UFCRITICAL138S0635

C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999CRITICAL138S0626 CAP, 10UF, 6.3V, 20%, 06038 SS_CAP_10UF

10138S0634 TY_CAP_2_2UFC3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641CAP, 2.2UF, 6.3V, 20%, 0402 CRITICAL

Acoustic Cap BOM Config Tables


8138S0626 CAP, 10UF, 6.3V, 20%, 0603 CRITICALC4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647 SS_CAP_10UFCAP, 10UF, 6.3V, 20%, 0603138S0626 1 C1280 CRITICAL SS_CAP_10UF

C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249CAP, 2.2UF, 6.3V, 20%, 0402 SS_CAP_2_2UFCRITICAL138S0632 10

C7203,C79802138S0628 MU_CAP_1UFCRITICALCAP, 1UF, 6.3V, 10%, 0402

C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C53109 MU_CAP_2_2UF138S0633 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICAL

C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647CRITICAL8 CAP, 10UF, 6.3V, 20%, 0603138S0625 MU_CAP_10UFC9012,C9486,C2500,C2520,C2560,C2567,C2600,C69998 TY_CAP_10UF138S0627 CAP, 10UF, 6.3V, 20%, 0603 CRITICAL

CAP, 2.2UF, 6.3V, 20%, 040210138S0634 TY_CAP_2_2UFC3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541CRITICAL

5 C1230,C4902,C7360,C7361,C9480CAP, 22UF, 6.3V, 20%, 0603 CRITICAL TY_CAP_22UF138S0688

3 CAP, 22UF, 6.3V, 20%, 0603 C1223,C1226,C1227 TY_CAP_22UF138S0688 CRITICAL4 CAP, 22UF, 6.3V, 20%, 0603 C1210,C1214,C1217,C1218 CRITICAL TY_CAP_22UF138S0688

5 C1230,C4902,C7360,C7361,C9480CAP, 22UF, 6.3V, 20%, 0603138S0676 MU_CAP_22UFCRITICAL3 C1223,C1226,C1227CAP, 22UF, 6.3V, 20%, 0603138S0676 MU_CAP_22UFCRITICAL4 C1210,C1214,C1217,C1218CAP, 22UF, 6.3V, 20%, 0603 CRITICAL138S0676 MU_CAP_22UF

138S0632 CAP, 2.2UF, 6.3V, 20%, 0402C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641CRITICAL10 SS_CAP_2_2UF

2 C7203,C7980 CRITICAL SS_CAP_1UFCAP, 1UF, 6.3V, 10%, 0402138S0629

C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259 SS_CAP_2_2UF10 CRITICALCAP, 2.2UF, 6.3V, 20%, 0402138S0632

CRITICALC9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919 SS_CAP_2_2UF10 CAP, 2.2UF, 6.3V, 20%, 0402138S0632

10 C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929CAP, 2.2UF, 6.3V, 20%, 0402 SS_CAP_2_2UF138S0632 CRITICAL

C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 SS_CAP_2_2UFCAP, 2.2UF, 6.3V, 20%, 040212138S0632 CRITICAL

138S0632 C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C53109 CRITICALCAP, 2.2UF, 6.3V, 20%, 0402 SS_CAP_2_2UF

SS_CAP_2_2UFC9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909CRITICAL10138S0632 CAP, 2.2UF, 6.3V, 20%, 0402

CAP, 2.2UF, 6.3V, 20%, 0402138S0632 C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516CRITICALSS_CAP_2_2UF10

CRITICALC9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999 MU_CAP_10UFCAP, 10UF, 6.3V, 20%, 06038138S0625

1 C1280 CRITICAL MU_CAP_10UF138S0625 CAP, 10UF, 6.3V, 20%, 0603 C12801 CAP, 10UF, 6.3V, 20%, 0603 TY_CAP_10UF138S0627 CRITICALCRITICALC4690,C4695,C5025,C7205,C7290,C7345,C7355,C76478138S0627 CAP, 10UF, 6.3V, 20%, 0603 TY_CAP_10UF

CRITICALC3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616CAP, 2.2UF, 6.3V, 20%, 040210138S0632 SS_CAP_2_2UFCAP, 2.2UF, 6.3V, 20%, 0402 CRITICAL8138S0632 SS_CAP_2_2UFC3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555

10 C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541CAP, 2.2UF, 6.3V, 20%, 0402138S0632 SS_CAP_2_2UFCRITICAL

C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939 SS_CAP_2_2UF138S0632 CAP, 2.2UF, 6.3V, 20%, 040210 CRITICAL

138S0633 10 CRITICALMU_CAP_2_2UFC3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641CAP, 2.2UF, 6.3V, 20%, 0402

138S0633 C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616 MU_CAP_2_2UF10 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALC3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555 MU_CAP_2_2UF138S0633 8 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICAL

CRITICAL138S0633 CAP, 2.2UF, 6.3V, 20%, 0402 MU_CAP_2_2UFC3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C354110MU_CAP_2_2UF138S0633 C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C351610 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 MU_CAP_2_2UF138S0633 12 CRITICALC9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C993910 CRITICALCAP, 2.2UF, 6.3V, 20%, 0402138S0633 MU_CAP_2_2UF

MU_CAP_2_2UFC9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929CRITICAL10 CAP, 2.2UF, 6.3V, 20%, 0402138S0633

CAP, 2.2UF, 6.3V, 20%, 0402 MU_CAP_2_2UFC9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919CRITICAL10138S0633

CAP, 2.2UF, 6.3V, 20%, 0402 C1260,C1261,C1262,C1263,C1264,C1265,C1266,C12678 SS_CAP_2_2UF138S0632 CRITICAL10138S0633 CRITICALCAP, 2.2UF, 6.3V, 20%, 0402 MU_CAP_2_2UFC1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259

MU_CAP_2_2UFCRITICALC1260,C1261,C1262,C1263,C1264,C1265,C1266,C12678 CAP, 2.2UF, 6.3V, 20%, 0402138S0633

CRITICAL10 CAP, 2.2UF, 6.3V, 20%, 0402138S0633 MU_CAP_2_2UFC9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909

MU_CAP_2_2UF10 CRITICALCAP, 2.2UF, 6.3V, 20%, 0402138S0633 C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249

TY_CAP_2_2UF9 C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310138S0634 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICAL

138S0634 CAP, 2.2UF, 6.3V, 20%, 040210 TY_CAP_2_2UFC3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616CRITICALC3542,C3544,C3545,C3546,C3550,C3551,C3554,C35558138S0634 TY_CAP_2_2UFCAP, 2.2UF, 6.3V, 20%, 0402 CRITICAL

138S0634 10 TY_CAP_2_2UFC3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516CAP, 2.2UF, 6.3V, 20%, 0402 CRITICAL138S0634 12 C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 TY_CAP_2_2UFCAP, 2.2UF, 6.3V, 20%, 0402 CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402138S0634 10 C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939CRITICALTY_CAP_2_2UF138S0634 10 C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929CRITICALCAP, 2.2UF, 6.3V, 20%, 0402 TY_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 040210 C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919CRITICALTY_CAP_2_2UF138S0634

10 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALC1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259 TY_CAP_2_2UF138S0634

8 CAP, 2.2UF, 6.3V, 20%, 0402138S0634 CRITICALC1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267 TY_CAP_2_2UFC9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C990910 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALTY_CAP_2_2UF138S0634

CRITICAL10 CAP, 2.2UF, 6.3V, 20%, 0402C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 TY_CAP_2_2UF138S0634

C7203,C79802138S0630 CAP, 1UF, 6.3V, 10%, 0402 TY_CAP_1UFCRITICAL

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