Upload
gabriel-heath
View
219
Download
2
Embed Size (px)
Citation preview
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 1
Processor Data Paths -ALU and RegistersIncorporating the ALU into a Processor Data Path
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 2
L4 – Incorporint ALU into data path Building up the data path from the ALU Control of the data path Datapath Evolution
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 3
Have our multifunction ALU Will now
put an interface around the ALU and build up a data path
P0
P1
P2
P3
Pi
K0
K1
K2
K3
Ki
R0
R1
R2
R3
Ri
CiCi+1
Propagate Block
Kill Block
Carry Chain
Results Generator
Ai Bi
Ai Bi
Pi Ci
P0
P1
P2
P3
Pi
K0
K1
K2
K3
Ki
R0
R1
R2
R3
Ri
CiCi+1
Propagate Block
Kill Block
Carry Chain
Results Generator
Ai Bi
Ai Bi
Pi Ci
P0
P1
P2
P3
Pi
K0
K1
K2
K3
Ki
R0
R1
R2
R3
Ri
CiCi+1
Propagate Block
Kill Block
Carry Chain
Results Generator
Ai Bi
Ai Bi
Pi Ci
P0
P1
P2
P3
Pi
K0
K1
K2
K3
Ki
R0
R1
R2
R3
Ri
CiCi+1
Propagate Block
Kill Block
Carry Chain
Results Generator
Ai Bi
Ai Bi
Pi Ci
P0
P1
P2
P3
Pi
K0
K1
K2
K3
Ki
R0
R1
R2
R3
Ri
CiCi+1
Propagate Block
Kill Block
Carry Chain
Results Generator
Ai Bi
Ai Bi
Pi Ci
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 4
The wrapper Establish an interface
to the ALU slices Have the data inputs
(multibit) Have a Carry in Have control in (PKR) Produce
The result R A carry out
A B
CinCout
R
PctlKctl
Rctl
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 5
Build up step 1 – latches – busses Add input and output
latches/bus drivers Add 2 internal data
busses Add flag generation Inputs & control –
A,B,Cin,Pctl, Kctl, Rctl Outputs – Cout, R,
Nflag, Zflag
A
A B
CinCout
R
PctlKctl
Rctl
N flagZ flag
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 6
Build up step 2 Now add general
purpose registers These are dual ported
registers Loading or driving of
registers on the bus is controlled by the clock
Busses are tristate
ALU
A
A B
CinCout
R
PctlKctl
Rctl
N flagZ flag
R0R1…
R(n)
ClkClk
Dir ABUS Dir BBUSAreg # Breg #
ALU B LatchALU A Latch
ALU B Drive
BBUSABUS
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 7
Dual Ported Registers Register are dual ported
Registers can be loaded from or drive a value onto both the A Bus and B Bus simultaneously
Possible combinations on same cycle Drive both the A Bus and B Bus – may or may not be
possible for it to be the same register. Load from both the A Bus and B Bus
Must be different registers!!!!!!!!! Register bank does not check for this – responsibility of
the controller Load from one Bus and drive the other
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 8
Now add the controller Control unit
contains Instruction Register Flags register Finite state machine
Control unit generates control signals
ALU
A
A B
CinCout
R
PctlKctl
Rctl
N flagZ flag
R0R1…
R(n)
ClkClk
Dir ABUS Dir BBUSAreg # Breg #
ALU B LatchALU A Latch
ALU B Drive
BBUSABUS
CO
NT
RO
LL
ER
IRF
lags
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 9
Program Counter and MDR, MAR MDR – Memory Data
Register MAR – Memory
Address Register Program Counter
Register increment and offset
integrated into register design
ALU
A
A B
CinCout
R
PctlKctl
Rctl
N flagZ flag
R0R1…
R(n)
ClkClk
Dir ABUS Dir BBUSAreg # Breg #
ALU B LatchALU A Latch
ALU B Drive
BBUSABUS
CO
NT
RO
LL
ER
IRF
lags
MDR
MDR dirMDRlatch
To/From Memory
Prog Cntr
MARMAR_Aload MAR_Bload
Offset adder +1PC Ctl sig
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 10
Other Functional Units May want to
incorporate Shifter Floating Point Units Index addressing
registers Etc.
ALU
A
A B
CinCout
R
PctlKctl
Rctl
N flagZ flag
R0R1…
R(n)
ClkClk
Dir ABUS Dir BBUSAreg # Breg #
ALU B LatchALU A Latch
ALU B Drive
BBUSABUS
CO
NT
RO
LL
ER
IRF
lags
MDR
MDR dirMDRlatch
To/From Memory
Prog Cntr
MARMAR_Aload MAR_Bload
Offset adder +1PC Ctl sig
ShifterDist
Shifter DriveShifter Load
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 11
General Operation of a Datapath Datapaths are generally synchronous Internal clock most likely higher than bus
clock Typical RTL of datapath
Cyc 1: Mem(PC) -> IR PC + 1 -> PC Cyc 2: RS1+RS2 -> ALUout Cyc 3: ALU out -> RS1
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 12
Datapath Control Evolution Finite State Machine (FSM)
Fixed and unvarying action of a datapath FSM implemented with PLA
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 13
Use of flags Here the current data can affect the action of
the controller
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 14
Load flags By loading a flags register can use them to
affect the controller only at specific points in the “program”
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 15
Data from memory used In addition to flags, data from memory can
affect the state and the datapaths action
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 16
Instruction Reg Have now progressed to a “stored” program
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 17
Alternative form Here use a ROM rather than a PLA finite state
machine
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 18
Another alternative Use a microprogram counter
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 19
A different slice Just a different visualization
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 20
Operation Shows steps the
controller would go through to execute the instructions
1/8/2007 - Data Path Design & Control
Copyright 2006 - Joanne DeGroat, ECE, OSU 21
Operation Examples – ALU op