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9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 1
More Sequential Circuits
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 2
Class 23-More Sequential Circuits An up/down counter A loadable down counter with signal
Material from section 5-5 of text
Design of and up/down counter Problem Statement: Design a 3 bit binary
clocked counter that counts up when the input C = 1 and counts down when the input C = 0. When the counter gets to 111 (000) it rolls over to 000 (111).
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 3
Problem Formulation Will use a state table for this problem
C=0 down C=1 up Present State Next State Next State 000 111 001 001 000 010 010 001 011 011 010 100 100 011 101 101 100 110 110 101 111 111 110 000
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 4
State Assignment As this design involves a counter it already
has binary values assigned to the states. So we can move straight to creation of the
next state generation. The system will use D Flip-flops.
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 5
Next State Generation In the table the Present State will be denoted
by the 3-bit binary value as seen in the state table. The binary value is Q2Q1Q0.
First the generation of Q0.
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 6
Next State Generation D1
Generate the next state equation for D1
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 7
D1 = C’Q1’Q0’+C’Q1Q0+CQ1’Q0+CQ1Q0’ = C’(Q1’Q0’+Q1Q0) +C(Q1’Q0+Q1Q0’) = C’ (Q1Q0) + C (Q1Q0)
Next State Generation D2
Generate the next state equation for D2
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 8
D2=C’Q2’Q1’Q0’+CQ2’Q1Q0+CQ2Q1’+ C’Q2Q0+Q2Q1Q0’
Output Generation Output generation is easy as it just the current
state.
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 9
Verification via HDL The models
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Copyright 2009 - Joanne DeGroat, ECE, OSU 10
ENTITY DFF IS PORT (D,CLK : IN BIT; Q,Q_bar : OUT BIT); END DFF; ARCHITECTURE beh OF DFF IS BEGIN PROCESS BEGIN Q <= D; Q_bar <= NOT D; WAIT UNTIL CLK='1' and CLK'EVENT; END PROCESS; END beh;
The counter model Uses the D FF
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 11
ENTITY UDCNTR IS PORT (C,CLK : IN BIT; Q : OUT BIT_VECTOR(2 DOWNTO 0)); END UDCNTR; ARCHITECTURE one OF UDCNTR IS SIGNAL D0,D1,D2,Q0,Q1,Q2 : BIT; SIGNAL Q0_bar,Q1_bar,Q2_bar : BIT; COMPONENT DFF PORT (D,CLK : IN BIT; Q,Q_bar : OUT BIT); END COMPONENT; FOR ALL : DFF USE ENTITY work.dff(beh); BEGIN -- invoke FFs FF0 : DFF PORT MAP(D0,CLK,Q0,Q0_bar); FF1 : DFF PORT MAP(D1,CLK,Q1,Q1_bar); FF2 : DFF PORT MAP(D2,CLK,Q2,Q2_bar); -- set up next state logic D0 <= NOT Q0; D1 <= (NOT C and (Q1 xnor Q0)) OR (C and (Q1 xor Q0)); D2 <= (NOT C and NOT Q2 and NOT Q1 and NOT Q0) OR (C and NOT Q2 and Q1 and Q0) OR (C and Q2 and NOT Q1) OR (NOT C and Q2 and Q0) OR (Q2 and Q1 and NOT Q0); -- generate outputs Q(0) <= Q0; Q(1) <= Q1; Q(2) <= Q2; END one;
The Testbench Need to apply stimulus and look at results.
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 12
ENTITY cntr_test IS END cntr_test; ARCHITECTURE one of cntr_test IS SIGNAL C,CLK : BIT; SIGNAL CNT : BIT_VECTOR(2 downto 0); COMPONENT UDCNTR PORT (C,CLK : IN BIT; Q : OUT BIT_VECTOR(2 downto 0)); END COMPONENT; FOR ALL : UDCNTR USE ENTITY work.UDCNTR(one); BEGIN -- set up the clock CLK <= not CLK after 5 ns; -- invoke the counter ctr0 : UDCNTR PORT MAP(C,CLK,CNT); -- set up the input C waveform PROCESS BEGIN C <= '1'; WAIT FOR 100 ns; C <= '0'; WAIT FOR 100 ns; C <= '1'; WAIT FOR 30 ns; C <= '0'; WAIT FOR 40 ns; WAIT; END PROCESS; END one;
Simultion Results The waveform for counting up
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 13
Simultion Results The waveform for counting down
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 14
Simulation Results Waveform for up again and back to down
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Copyright 2009 - Joanne DeGroat, ECE, OSU 15
Changing format to octal display For a more readable output
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Copyright 2009 - Joanne DeGroat, ECE, OSU 16
A Loadable countdown timer Specification: Design a loadable 3-bit
countdown timer the after loading counts down to 0 and then generates a signal Z which will stay asserted as long as the countdown is enabled.
When the counter reaches 0 it remains there until a new count is loaded.
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 17
The state table The state table showing both count enable and
load
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 18
K-maps The K-maps for the circuit are.
9/15/09 - L23 More Sequential Circuits
Copyright 2009 - Joanne DeGroat, ECE, OSU 19
The output The output signal Z is
asserted when state 000 is reached. It stays asserted as long as C is asserted.
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Copyright 2009 - Joanne DeGroat, ECE, OSU 20
The circuit Has 3 FFs
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Copyright 2009 - Joanne DeGroat, ECE, OSU 21
Class 23 assignment Covered sections 5-5 Problems for hand in
Nothing new Problems for practice
Nothing new
Reading for next class: 5-6
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Copyright 2009 - Joanne DeGroat, ECE, OSU 22