16.482 / 16.561Computer Architecture

and DesignInstructor: Dr. Michael Geiger

Summer 2014

Lecture 6:Speculation

Lecture outline Announcements/reminders

HW 5 to be posted; due 6/13

Today’s lecture Speculation

04/18/23 Computer Architecture Lecture 6 2

04/18/23 Computer Architecture Lecture 6 3

Review: Dynamic scheduling Dynamic scheduling - hardware rearranges the

instruction execution to reduce stalls while maintaining data flow and exception behavior Key idea: Allow instructions behind stall to proceed Allow out-of-order execution and out-of-order completion We use Tomasulo’s Algorithm Decode stage now handles:

Issue—check for structural hazards and assign instruction to functional unit (via reservation station) Check for register values

Reservation stations implicitly perform register renaming Resolves potential WAW, WAR hazards

Results broadcast over common data bus

04/18/23 Computer Architecture Lecture 6 4

Speculation to greater ILP 3 components of HW-based speculation:1. Dynamic branch prediction

Need BTB to get target in 1 cycle2. Ability to speculate past branches3. Dynamic scheduling In Tomasulo’s algorithm, separate

instruction completion from commit Once instruction is non-speculative, it can

update registers/memory Reorder buffer tracks program order

Head of ROB can commit when ready ROB supplies data between complete and commit

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Reorder Buffer Entry Each entry in the ROB contains four fields: 1. Instruction type

• a branch (has no destination result), a store (has a memory address destination), or a register operation (ALU operation or load, which has register destinations)

2. Destination• Register number (for loads and ALU operations) or

memory address (for stores) where the instruction result should be written

3. Value• Value of instruction result until the instruction commits

4. Ready• Indicates that instruction has completed execution, and

the value is ready

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Speculative Tomasulo’s Algorithm1. Instruction fetch--get instruction from memory; place in Op Queue2. Issue—get instruction from FP Op Queue

If reservation station and reorder buffer slot free, issue instr & send operands & reorder buffer no. for destination (this stage sometimes called “dispatch”)

3. Execution—operate on operands (EX) When both operands ready then execute; if not ready,

watch CDB for result; when both in reservation station, execute; checks RAW (sometimes called “issue”)

4. Memory access--if needed (MEM) NOTE: Stores update memory at commit, not MEM

5. Write result—finish execution (WB) Write on Common Data Bus to all awaiting FUs

& reorder buffer; mark reservation station available.6. Commit—update register with reorder result

When instr. at head of reorder buffer & result present, update register with result (or store to memory) and remove instr from reorder buffer. Mispredicted branch flushes reorder buffer (sometimes called “graduation”)

04/18/23 Computer Architecture Lecture 6 7

Tomasulo’s With Reorder buffer:

ToMemory

FP addersFP adders FP multipliersFP multipliers

Reservation Stations

FP OpQueue

ROB7

ROB6

ROB5

ROB4

ROB3

ROB2

ROB1F0F0 LD F0,10(R2)LD F0,10(R2) NN

Done?

DestDest

Oldest

Newest

from Memory

1 10+R21 10+R2Dest

Reorder Buffer

Registers

Revisiting stores with speculation With ROB, store buffers eliminated Why?

Can’t write memory until you know value is non-speculative

Once address is calculated, store in “destination” field of ROB entry

Need additional field in ROB for stores: equivalent to “Q” fields in reservation stations Indicates what instruction is writing value to be stored

04/18/23 Computer Architecture Lecture 6 8

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Reorder buffer example Given the following code:

Loop: L.D F0, 0(R1)

MUL.D F4, F0, F2

S.D F4, 0(R1)

DADDIU R1, R1, #-8

BNE R1, R2, Loop Walk through two iterations of the loop Assume

2 cycles for add, load 1 cycle for address calculation 6 cycles for multiply Forwarding via CDB

Reorder buffer example: key points Execution stages

Fetch & issue: always in order Execution & completion: may be out of order Commit: always in order

Hardware Reservation stations

Occupied from IS to WB Reorder buffer

Occupied from IS to C Used to

Maintain program order for in-order commit Supply register values between WB and C

Register result status Rename registers based on ROB entries

04/18/23 Computer Architecture Lecture 6 10

Memory hazards, exceptions Reorder buffer helps limit memory hazards

With additional logic for disambiguation (determine if addresses match)

WAW / WAR automatically removed RAW maintained by

Stalling loads if store with same address is in flight Ensuring that effective addresses are computed in order

Precise exceptions logical extension of ROB If instruction causes exception, flag in ROB Handle exception when instruction commits

04/18/23 Computer Architecture Lecture 6 11

Getting CPI below 1 CPI ≥ 1 if issue only 1 instruction every clock

cycle Multiple-issue processors come in 3 flavors:

statically-scheduled superscalar processors, dynamically-scheduled superscalar processors, and VLIW (very long instruction word) processors

2 types of superscalar processors issue varying numbers of instructions per clock use in-order execution if they are statically scheduled,

or out-of-order execution if they are dynamically

scheduled

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Performance beyond single thread ILP There can be much higher natural parallelism in

some applications (e.g., Database or Scientific codes)

Explicit Thread Level Parallelism or Data Level Parallelism

Thread: process with own instructions and data thread may be a process part of a parallel program of

multiple processes, or it may be an independent program Each thread has all the state (instructions, data, PC,

register state, and so on) necessary to allow it to execute Data Level Parallelism: Perform identical operations

on data, and lots of data

04/18/23 Computer Architecture Lecture 6 14

Thread Level Parallelism (TLP) ILP exploits implicit parallel operations within

a loop or straight-line code segment TLP explicitly represented by the use of

multiple threads of execution that are inherently parallel

Goal: Use multiple instruction streams to improve Throughput of computers that run many programs Execution time of multi-threaded programs

TLP could be more cost-effective to exploit than ILP

04/18/23 Computer Architecture Lecture 6 15

New Approach: Mulithreaded Execution Multithreading: multiple threads to share the

functional units of 1 processor via overlapping processor must duplicate independent state of each thread

e.g., a separate copy of register file, a separate PC, and for running independent programs, a separate page table

memory shared through the virtual memory mechanisms, which already support multiple processes

HW for fast thread switch; much faster than full process switch 100s to 1000s of clocks

When switch? Alternate instruction per thread (fine grain) When a thread is stalled, perhaps for a cache miss,

another thread can be executed (coarse grain)

Fine-Grained Multithreading Switch on each instruction Usually done in a round-robin fashion,

skipping any stalled threads CPU must be able to switch threads every

clock Advantage: Hide both short/long stalls Disadvantage: slows individual threads

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Coarse-Grained Multithreading Switches only on costly stalls, such as L2 cache

misses Advantages

Relieves need to have very fast thread-switching Doesn’t slow down individual thread

Disadvantage: hard to overcome throughput losses on shorter stalls, due to pipeline start-up costs Since CPU issues instructions from 1 thread, when a stall

occurs, the pipeline must be emptied or frozen New thread must fill pipeline before instructions can

complete Because of this start-up overhead, coarse-grained

multithreading is better for reducing penalty of high cost stalls, where pipeline refill << stall time

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Do both ILP and TLP? TLP and ILP exploit two different kinds of parallel

structure in a program Could a processor oriented at ILP exploit TLP?

Functional units are often idle in data path designed for ILP because of either stalls or dependences in the code

Could the TLP be used as a source of independent instructions that might keep the processor busy during stalls?

Could TLP be used to employ the functional units that would otherwise lie idle when insufficient ILP exists?

04/18/23 Computer Architecture Lecture 6 19

Simultaneous Multi-threading ...

1

2

3

4

5

6

7

8

9

M M FX FX FP FP BR CCCycleOne thread, 8 units

M = Load/Store, FX = Fixed Point, FP = Floating Point, BR = Branch, CC = Condition Codes

1

2

3

4

5

6

7

8

9

M M FX FX FP FP BR CCCycleTwo threads, 8 units

04/18/23 Computer Architecture Lecture 6 20

Simultaneous Multithreading (SMT) Simultaneous multithreading (SMT): insight that

dynamically scheduled processor already has many HW mechanisms to support multithreading Large set of virtual registers that can be used to hold the

register sets of independent threads Register renaming provides unique register identifiers, so

instructions from multiple threads can be mixed in datapath without confusing sources and destinations across threads

Out-of-order completion allows the threads to execute out of order, and get better utilization of the HW

Just adding a per thread renaming table and keeping separate PCs Independent commitment can be supported by logically

keeping a separate reorder buffer for each threadSource: Microprocessor Report, December 6, 1999

“Compaq Chooses SMT for Alpha”

04/18/23 Computer Architecture Lecture 6 21

Multithreaded CategoriesTi

me

(pro

cess

or

cycle

)Superscalar Fine-Grained Coarse-Grained Multiprocessing

SimultaneousMultithreading

Thread 1

Thread 2Thread 3Thread 4

Thread 5Idle slot

04/18/23 Computer Architecture Lecture 6 22

Design Challenges in SMT Since SMT makes sense only with fine-grained implementation,

impact of fine-grained scheduling on single thread performance? A preferred thread approach sacrifices neither throughput nor

single-thread performance (?) Unfortunately, with a preferred thread, the processor is likely to

sacrifice some throughput, when preferred thread stalls Larger register file needed to hold multiple contexts Not affecting clock cycle time, especially in

Instruction issue - more candidate instructions need to be considered

Instruction completion - choosing which instructions to commit may be challenging

Ensuring that cache and TLB conflicts generated by SMT do not degrade performance

Multithreading examples Assume processor with following characteristics

4 functional units 2 ALU 1 memory port (either load or store) 1 branch

In-order scheduling Given 3 threads, show execution using

Fine-grained multithreading Coarse-grained multithreading

Assume any stall longer than 2 cycles causes switch Simultaneous multithreading

Thread 1 is preferred, followed by Thread 2 & Thread 3 Assume any two instructions without stalls between

them are independent

04/18/23 Computer Architecture Lecture 6 23

Final notes Next time

Memory hierarchies Reminders

HW 5 to be posted; due 6/13

04/18/23 Computer Architecture Lecture 6 24