8/22/2019 14nm Gate Length MOSFET
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14nm gate length MOSFET
It is an electrically variable shallow junction MOSFET
(EJMOSFET) with an ultra
shallow source /drain junction has been fabricated to study the
transistor charc &
physical phenomena in ultra fine gate MOSFET.
The lower gate is the same as the gate in conventional MOSFETs
controlsdrain current.
Positive upper gate bias induces source/ drain regions at the
silicon surface cozthe source / drain regions are extremely
shallow.
EJ-MOSFET fabricated in the same way as conventional MOSFET. A
high concentration of boron of 2x10^18 cm^-3 was used within the
substrate to
suppress short channel effects caused by the lateral expansion
of the depletion
layers.
The boron conc. Was controlled by means of boron ion
implantation & thethermal drive in .
n+ regions were formed by arsenic ion implantation. A gate oxide
was formed by thermal oxidation & a 40nm thick poly silicon
was
grown by CVD . Phosphorous was doped into the polysilicon flim
in a POCl3 atm . The ultra high resolution EB resist was spin
coated onto the poly silicon film &
EB direct writing with a 5nm beam dia & a 50kV acc energy
was performed.
After developing procedure, the resis t pattern was transferred
to the poly siliconfilm by reactive ion etching with CF4 gas.
