1382 IEEEJOURNALOFSOLID …nel003.ee.nthu.edu.tw/nel/File/1dd3ade9ab23f32d5dbc9e... · 2016. 2. 9. · 1386 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.50,NO.6,JUNE2015 TABLEI COMPARISONOFERRORTOLERANCETECHNIQUES

1382 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

A 0.003 mm 10 b 240 MS/s 0.7 mW SAR ADCin 28 nm CMOS With Digital Error Correction and

Correlated-Reversed SwitchingJen-Huan Tsai, Hui-Huan Wang, Yang-Chi Yen, Chang-Ming Lai, Yen-Ju Chen,

Po-Chuin Huang, Ping-Hsuan Hsieh, Hsin Chen, and Chao-Cheng Lee

Abstract—This paper describes a single-channel, calibra-tion-free Successive-Approximation-Register (SAR) ADC with aresolution of 10 bits at 240 MS/s. A DAC switching technique andan addition-only digital error correction technique based on thenon-binary search are proposed to tackle the static and dynamicnon-idealities attributed to capacitor mismatch and insufficientDAC settling. The conversion speed is enhanced, and the powerand area of the DAC are also reduced by 40% as a result. Inaddition, a switching scheme lifting the input common mode of thecomparator is proposed to further enhance the speed. Moreover,the comparator employs multiple feedback paths for an enhancedregeneration strength to alleviate the metastable problem. Occu-pying an active area of 0.003 mm and dissipating 0.68 mW from1 V supply at 240 MS/s in 28 nm CMOS, the proposed designachieves an SNDR of 57 dB with low-frequency inputs and 53 dBat the Nyquist input. This corresponds to a conversion efficiencyof 4.8 fJ/c.-s. and 7.8 fJ/c.-s. respectively. The DAC switchingtechnique improves the INL and DNL from +1.15/-1.01 LSB and+0.92/-0.28 LSB to within +0.55/-0.45 LSB and +0.45/-0.23 LSB,respectively. This ADC is at least 80% smaller and 32% morepower efficient than reported state-of-the-art ADCs of similarresolutions and Nyquist bandwidths larger than 75 MHz.Index Terms—Capacitor mismatch, DAC settling, digital

error correction, dynamic comparator, metastability, SAR ADC,switching scheme.

I. INTRODUCTION

S UCCESSIVE-APPROXIMATION-REGISTER (SAR)ADCs with capacitive DAC are renowned for their promi-nent energy efficiency, and have recently been widely used insensor networks, biomedical ASICs, video and many generalpurpose applications [1] as the process technology progres-sively advances. In the past decade, significant efforts have beeninvested in the quest for ever-improving the figures-of-merits(FOM)1 and speed of SAR converters. Fig. 1 shows the per-formance summary of state-of-the-art SAR ADCs. Excellent

Manuscript received August 08, 2014; revised November 07, 2014; acceptedMarch 07, 2015. Date of publication April 22, 2015; date of current versionMay22, 2015. This paper was approved by Associate Editor Boris Murmann.J.-H. Tsai is with National Tsing Hua University, Hsinchu, Taiwan (e-mail:

[email protected]).H.-H. Wang, Y.-C. Yen, C.-M. Lai, Y.-J. Chen, P.-C. Huang, P.-H. Hsieh,

and H. Chen are with National Tsing Hua University, Hsinchu, Taiwan.C.-C. Lee is with Realtek Semiconductor Corporation, Hsinchu, Taiwan.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2015.2413850

1The (Walden) FOM for Nyquist ADCs is defined as:

Fig. 1. Performance comparison of with all SAR ADCs from ISSCC/VLSI 1997 ~ 2013.

FOMs of less than 3 fJ/conversion-step (fJ/c.-s.) are recentlyachieved in [2]–[4] at a speed lower than 4 MS/s by introducingenergy-efficient DAC switching methods and suppressing thecomparator noise. For SAR ADCs, higher sampling rate above100 MS/s is conventionally realized by employing time-inter-leaving, pipelining operations [5]–[11], hybrid architectureswith a fast coarse ADC [5]–[7]. Among these architecturalapproaches, the dynamic pipelined SAR architecture withtime-interleaving (TI) [9], [10] outstands with the best energyefficiency, as revealed in Fig. 1. In [10], the 410 MS/s 2 TIpipelined SAR ADC reports an SNDR of 59.8 dB with an FOMof 11.4 fJ/c.-s. However, it occupies an area of mm inthe 28 nm CMOS process and requires calibration. Moreover,the speed of the constituent single-channel ADC is still limitedto 205 MS/s in spite of being pipelined. Another method toachieve high speed is to convert more bits at a time, as shownwith the 9 bit 900 MS/s 2 TI SAR ADC in [11]. However,the overhead of the extra comparators and DACs for referencegeneration leads to an area of mm and an FOM of40.5 fJ/c.-s. in the 45 nm process. In summary, prior NyquistADCs of all kinds with the resolution above 8 bits and speedhigher than 160 MS/s exhibit an FOM greater than 11.4 fJ/c.-s.[9] and an area larger than mm [12]. In particular, the

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TSAI et al.: A 0.003 mm 10 b 240 MS/s 0.7 mW SAR ADC IN 28 nm CMOS WITH DIGITAL ERROR CORRECTION AND CORRELATED-REVERSED SWITCHING 1383

Fig. 2. Search processes of a 4 bit SAR ADC employing various algorithms. (a) Conventional binary search :(Cap. array: , 2, 1) (b) Extended binary search :(Cap. array: , 2, 1, ) (c) Sub-radix-2 : (e.g., Cap. array: , , , for radix- ).

sampling rate of a single-channel SAR ADC with a resolutiongreater than 9 bits remains below 220 MS/s [12]. In order tofurther improve the performance of the SAR-based ADCs, thefundamental design issues are carefully analyzed.The performance indexes of a SAR ADC, including the

power, speed, area and input impedance, are closely relatedto its DAC, whose total capacitance hinges upon either the

noise or the matching requirement for linearity.Premised on achieving an ENOB above 9 bits and the maximumDNL/INL smaller than 1/2 LSB with a yield greater than 99.7%( coverage) [13], [14], the overall performance is usuallylimited by the large capacitance of the DAC for sufficientmatching. Traditionally, calibration techniques are utilized totrim the static DAC non-ideality in either an analog [15] ora digital [16] manner, but the overheads are non-negligible.On the other hand, as incomplete DAC settling also degradeslinearity, high-speed SAR conversion dictates a prohibitivelyhigh bandwidth, and hence high power consumption for the ref-erence generation. For example, the DAC in a 10 bit 240 MS/sSAR ADC has to settle down with 10 bit accuracy within0.2 ns, given that leaving equal amount of time for samplingand conversion.

As surveyed exhaustively in [17], various redundancy tech-niques have been proposed to relax the settling issue, speed upthe conversion and reduce the power of the peripheral buffers.The robustness of high-speed conversion is also improved sinceincomplete DAC settling might as well be resulted from PVTvariations, or other dynamic interferences such as the power/ground bouncing. In [18], B. Murmann reviews prior designswith redundancy: R. Vitek re-introduces the prevalent 1.5 bitconcept in pipeline ADCs to the SAR ADC [12]. Some extendthe searching beyond binary levels by adding redundant (binary)search levels [19], [20]. The others resort to the sub-radix-2 al-gorithm with either a fixed radix [16], [21]–[23] or non-fixedradixes of less than two [24]. Fig. 2(a) reveals how the con-ventional binary search is vulnerable to intermediate errors. Aseach quantization level has only one unique search trajectory,decision errors are irrevocable. In contrast, Fig. 2(b)–(c) illus-trate the later two types of non-binary techniques. Overlappedsearching paths provide bounded tolerance to errors in the sensethat multiple bit patterns B can lead to the same approxima-tion D (within LSB to the input ) after multiplying Bwith proper bit-weights W (i.e., ) and eliminatingthe coding offset.


Fig. 3. The half circuit of the proposed 10 bit differential SAR ADC with the SC-ADEC technique (DAC at the sampling phase, and FA stands for a full adder).

This paper describes a 10 bit 240 MS/s SAR ADC withoutinterleaving nor pipelining. Several techniques are exploited toimprove the power, speed and area efficiency, seeking to breakbeyond the performance barrier of a single-channel SAR ADCas outlined in Fig. 1. An addition-only digital error correction(DEC) technique based on splitting capacitors is proposed toprovide a wide error-tolerance range without requiring redun-dant capacitors beyond the binary levels. Design guidelines foroptimizing speed and DEC logic are also given. In addition, aDAC switching technique called correlated-reversed switching(CRS) is proposed to suppress the DAC non-linearity due to ca-pacitor mismatch, allowing an equivalent 1 bit improvement ofthe DAC linearity. Furthermore, other circuit implementationtechniques are proposed for high-speed operation. Adopting allthese techniques, this work overcomes the performance bottle-neck, reporting an FOM of 4.6 7.8 fJ/c.-s. across the Nyquistband and an area of mm without any calibration in place.The rest of this paper is organized as the following. After an ar-chitecture overview, Section II explains the two techniques ad-dressing the dynamic and static non-idealities, respectively. Thecircuit implementations are detailed in Section III. Themeasure-ment results are discussed in Section IV. Finally, Section V con-cludes the contribution.

II. ARCHITECTURE OVERVIEW AND THE PROPOSEDTECHNIQUES

Fig. 3 shows the half circuit of the 10 bit differential SARADC. It highlights the initial DAC arrangement for redundancy.TheADC consists of a top-plate-sampling DAC, a comparator, acontroller, and a DEC logic that converts raw 13 bit output codesto error-corrected 10 bit codes . The differential realization

reduces the hardware of DAC to 9 bits.

A. Redundancy Based on Split-Capacitor With Addition-OnlyDEC (SC-ADEC)As illustrated in Fig. 4, the proposed SC-ADEC technique

splits the original MSB capacitor to several sub-ca-pacitors, which are either inserted in between or added to theoriginal binary capacitors. Conceptually, this is analogous

Fig. 4. The proposed SC-ADEC technique and the DAC switching sequence.

to the combination of the fore-mentioned sub-radix-2 andsearch-range extension techniques (Fig. 2(b)–(c)). As revealedin Fig. 5, postponing the search with the split capacitors tolater steps generates overlapped searching pathes, while thetotal number of DAC capacitors is unchanged. Applying thisapproach to this work, the original of is split intofour capacitors ofrespectively, as shown earlier in Fig. 3 where C is the unitcapacitor. These four capacitors are interleaved and sortedmonotonically with the binary LSB capacitors . Sincethe split capacitors are redundant to the binaryLSB DAC, they extend the search ranges for the LSB steps.Meanwhile, the MSB searching becomes less aggressive witha smaller , analogous to the sub-radix-2 algorithm. Thisarrangement tolerates at least 14.3% of settling errors in eachcycle.As also shown in Fig. 3, the DEC logic consists of only eight

full-adders (FA). It converts the raw output codes B with bit-weights of W into the error-corrected codes D by ,as depicted in Fig. 6. In order to let the elements of W be digi-tally representable without extra quantization error, every splitcapacitor has the form of either or .The splitting design keeps the total DAC capacitance unchangedsuch that the DEC computes with “addition” only without over-flowing. Moreover, since an FA takes three inputs in maximum,


Fig. 5. Proposed approach for redundancy generation with Cap. array: - , , , . (In this example, ).

Fig. 6. Arithmetic table illustrating the constrained splitting for simpler DEC logics.

the following constraint can be enacted to minimize the numberof FAs : Any two split capacitors contain no identical binary ca-pacitor components. As highlighted in Fig. 6, each bit-weightcolumn contains two “1”s in maximum except for whosesubsequent column never has carries. The hardware forDEC as well as the conversion latency are thus minimized.In the choice of the amount of the capacitors being split out

and additional bit-cycles, this design aims at a tolerance rangelarger than 12.5% as in [19], [22] for all cycles to mainly coverthe DAC settling error and possible process variations. We wantall cycles covered by redundancy since the robustness of theLSB section is equally important for an accurate conversion.Considering an -bit differential SAR ADC with a bi-

nary-scaled DAC and an MSB capacitor of ,a redundancy of of the full scale can be ob-tained by adding a geometric capacitor series ,

to extend the searching range coveragebased on the principle in Fig. 2(b). Instead of using extraredundant capacitors, the proposed SC-ADEC borrows thesearch-extending capacitors from the original . Thenew reduces to about after thesplitting. The amount of additional cycles is thus estimatedas: .Apply for a redundancy of at least of the previousdecision range. Three extra cycles are used accordingly forthis design. Then, instead of splitting out only binary-scaled

capacitors withas the redundant capacitors, we adopt

to obtain larger redundancy in MSBs as more steps are post-poned, and a simpler DEC logic (by obeying the enactedconstraint), and facilitates the combination with the CRS tech-nique (Section II-B). Since the last redundancy step adds only1 LSB in redundancy and still costs a complete cycle, it couldbe removed at the cost of a reduced code range if the robustnessof LSBs is not a concern.On the other hand, redundancy also elevates the conver-

sion speed as inaccurate settling is tolerable. By assumingthe time required for each cycle is the same and confinedby the longest cycle, the total conversion time can be esti-mated by taking into account the time penalty, denoted as

, for each comparator decision. For simplicity, we definea parameter , where is the timeconstant of the DAC. As derived in the Appendix, the op-timal solution maximizing the speed requires a redundancy of

for the SC-ADEC and search-rangeextension techniques [19]. For , choosing threeredundant cycles maximizes the speed. Note that the proposedSC-ADEC technique can also be realized by other decentdecompositions for different considerations, and hence notnecessarily following the presented design step. For instance,selecting optimizes


TABLE ICOMPARISON OF ERROR TOLERANCE TECHNIQUES

Fig. 7. DNL-free error tolerance range in each switching cycle .

the redundancy and DEC logics (gate counts and latency)concurrently.Fig. 7 compares the error tolerance capability of this and

the other designs [1], [19], [22], [24]. This work achieves awide redundancy coverage. Table I further compares the costand performance of these different non-binary designs. Priorsub-radix-2 designs entail complex arithmetical units [22], [24].Over-/under-flow removals are typically employed for designsthat use extra redundant capacitors [19]–[21], [24]. They alsosuffer from reduced conversion gains as the LSB level becomessmaller. The extended range (e.g., 10.2 bit range in [19]) is

hardly usable because it generally gets truncated to accom-modate an integer-bit binary coding unless the over-range isresided in a pipelined SAR stage as in [25]. In comparison, thisdesign achieves comparable tolerance and speed improvementwith minimal circuit overheads. In particular, as in [1], [22] theamount of total DAC capacitors (loading) is maintained on parwith that in conventional binary-weighted designs [26] withoutredundancy.In principle, all non-binary techniques for redundancy are

based on the -expansion for real numbers [18], [27], and differin the radix and DAC selections. The DACs are mostly realizedby an integer amount of unit capacitors for better matching. Ex-tended beyond by the discussions in [18], [28], Table II sum-marizes the non-binary techniques. Note that outputs thefirst integer larger than the real number . The redundancy re-sides in the flexibility of multiple sets of code in constructingthe same ADC input (normalized to the full-scale range). Theproposed SC-ADECmethod guarantees a unity conversion gain

and provides more flexibility in tweaking the redundancyvia the relaxed constraint for DAC's radix (i.e., ). Inpractice, redundancy can be used to repair errors from differentnon-idealities and hence can be optimized in different ways andthrough various dedicated (referred) design strategies. The pre-sented DAC design takes the redundancy coverage, speed andcircuit overhead into accounts. As to be seen soon, the com-patible CRS technique further reduces the unit capacitance forhigher speed.

B. Correlated Reversed Switching (CRS) for CapacitorMismatch CompensationWith an inherently-linear, 1 bit quantizer in the SAR feed-

back loop, the maximum achievable linearity is limited by theDAC.While the applied redundancy technique absorbs dynamic


TABLE IIEXPRESSING A/D CONVERSION BASED ON BETA-EXPANSION

Fig. 8. The final DAC arrangement for both the SC-ADEC and CRS techniques (sampling phase).

errors, static DAC nonlinearity caused by capacitor mismatchremains untackled. Therefore, the CRS technique is proposedto mitigate such static errors. The main idea of the CRS is tocompensate for the errors introduced in the preceding bit-cyclesby the subsequent DAC switching processes. Instead of alwaysswitching new capacitors for each new bit-cycle as in the con-ventional designs, the CRS tries to reuse the prior switched ca-pacitors, from which the errors (voltage) are induced at the firstplace, and switches them in a reversed direction to suppress theaccumulated error.Fig. 8 shows the finalized capacitor array in this work. After

splitting to , and for redundancy,, and are further decomposed into sub-capac-

itors to implement the capacitor reusing forthe CRS technique. As indicated by dashed lines, the matchedcapacitors of same capacitance are paired for reusing (e.g.,

is with and is with ). Fig. 9 illustrates theoperations in the first two bit-cycles, and Fig. 9(b) marks the“reusing” events. The MSB capacitor comprising of

and is switched after is decided. During thesecond bit-cycle, if , of 128 C is switched as shownin the upper- and lower-most switching paths. When ,

instead of is switched as is able to transfer thesame amount of charge as (both are of 128 C and connectedto after the MSB cycle). The DAC now always tries

to switch used capacitors instead of new ones. Similarly, theswitchings of can be replaced by the switching ofthe corresponding decomposed sub-capacitors with the samecapacitance and connections when their matched sub-capaci-tors have switched previously. As illustrated in Fig. 9(c), byreversely switching the previously-switched capacitors, thecorrelated errors are cancelled in situ. A stronger correlationleads to a better compensated result. With such switchingmethod, the ADC shows better linearity, while the number ofbit-cycles and the DEC logic remain unchanged.The theoretical effectiveness of the CRS is summarized in

Table III, based on similar calculations in [29], [30]. The thDAC capacitance can be expressed as ,where corresponds to th bit numerated from the MSB,

the mismatch error term assumed independentand identically distributed Gaussian random, ,

, and is the variance for an unit . Letbe the cumulative error voltage (normalized to 1 LSB)

of the DAC for a specific code set . Conventionally,reaches maximum for the half full-scaled code , i.e.,

or . By the definition of DNL, wehave , where de-pends on the DAC switching scheme, and the zero term is owingto the mismatch-free MSB decision. For the switching schemein Fig. 9,


Fig. 9. (a) The first 2 bit-cycles of the 10 bit SAR ADC with the CRS (b) the reusing activities in this work (c) Error suppression mechanism.

TABLE IIITHEORETICAL EFFECTIVENESS OF THE CRS

, where . The subscript indicate theerror from the p-/n-side DAC. According to , each switchedcapacitor brings an error . As for the MCS [31],

. Without applying theCRS, all mismatch error fully accumulate to the due errorpower .In contrast, reusing (i.e., results in

and . Then, if , the th error termdirectly cancels the correlated error terms contained in

before calculating the . Similarly, the same story applies

to (Appendix). The compensated error profile is illustratedin Fig. 10. The maximum 2 and are reducedby a factor of (at least) because the error power is halved bythe compensation in the worst case. Hence, is also re-duced by approximately two times [14]. For the MCS switching[31] ( -based type classified in Table III), the improvementby employing the CRS is even more eminent due to the pointsymmetry of the reduced INLwith respect to themid-code. Nev-

2Note that the best-fit INL yields the best repeatability, and it serves as a truerepresentation of linearity.


Fig. 10. RMS DNL/INL profiles for (a) bidirectional switching (Section II-C), (b) MCS switching (1% mismatch).

Fig. 11. ENOB histogram with random capacitor mismatch (w/i and w/o enabling CRS). (a) Bidirectional switching. (b) MCS switching.

Fig. 12. ENOB improvement by CRS. (a) Proposed bidirectional switching. (b) MCS switching.

ertheless, since -based switchings require an extra refer-ence voltage and compromise the speed seriously, this work em-ploys a bidirectional, power-rails-based DAC switching scheme(Section II-C). In Figs. 11 and 12, Monte-Carlo simulationsshow the ENOB improvement as a result of the CRS. Intuitively,

INL is reduced because some errors are cancelled rather thanaccumulated to induce significant non-linearity. This leads toa more linear A-to-D transfer curve statistically. Moreover, al-though the effectiveness of the CRS depends on the actual errorprofile, the mismatch errors are completely cancelled for the


Fig. 13. Comparison of switching energies.

worst mid-code since the fully-reversed DAC switching guaran-tees that the total net (error-) charge transfer is zero. The domi-nant mid-code DNLs are thus always suppressed to be nearlyzero, ensuring continuity near middle codes as in [32]. Thisproperty is especially beneficial for converting small input sig-nals.The revealed perspectives can also explain the enhanced

INLs or DNLs in [29], [30], [32], [33]. Basically, they sharethe same nature of a reduced amount of total mismatch errors.In conventional designs, a thermometer-coded MSB DAC isoften adopted to reduce DNL, as binary-weighted DACs sufferfrom more severe DNL than INL. However, a coarse sub-ADCmight be needed for resolving the MSBs first [33], or the ADChas to switch the same DAC for the MSB binary search. Ineither case, the MSB DACs have to adjust their switchings tofit the thermometer profile after decoding the binary MSBs.The DAC needs up to 3 bit thermometer MSB and 6 bit binaryLSB segmentation to achieve a similar as in this work(see Appendix), and the mid-code DNLs still remain non-zero.Additionally, further segmentation is futile for linearity asmismatch errors have already corrupted the MSB decisions.As a result, the CRS always achieves better linearity with lesspower and area overhead than a thermometer-coded DAC.

C. Bidirectional, Rail-to-Rail Switching

As the CRS and the SC-ADEC techniques are generally ap-plicable to various DAC switching schemes, a design freedom isremained to leverage for the best benefit. A wealth of switchingschemes have been reported in prior literatures in which thefocuses are mostly on lowering the mean switching energy.Fig. 13 compares the energy consumption of several majorschemes and the bidirectional rail-to-rail switching proposed inthis work. Due to the capacitor reusing in the CRS, the energyat the reset phase is spared code-dependently. As a result,this work dissipates 18% less power than the charge-averageswitching [3]. In addition, the direct switching between powerrails facilitates faster and easier DAC control as in the mono-tonic switching [26] whose DAC is directly driven by inverters

without the need for voltage-boosted controls in -involvedswitchings [3], [31]. Compared to [26], the proposed schemedrains at least 50% smaller peak dynamic current from thereference. It is also notable that, for low-speed operation, theMCS in [31] combined with the CRS is a good alternative toachieve an even lower switching energy and better linearity, asshown by Fig. 13 and Table III. The achieved linearity is (oneof) the best among all prior binary switching schemes to theauthor's knowledge, which potentially yields the smallest DACarea. The Enhanced-MCS [32] reports the same best linearity,but at the cost of complicated control and 27% larger power(Fig. 13) due to non-minimal DAC switching.In addition, the proposed bidirectional switching scheme lifts

the input common mode of the comparator to expedite its deci-sion. This is achieved by switching only the p-side or n-side ofthe DAC at every cycle. For example, in Fig. 9, if , onlythe p-side is switched to , while the n-side DAC re-mains unchanged. The common mode is therefore shifted up.

III. CIRCUIT IMPLEMENTATION

A. Dynamic ComparatorFig. 14(a) depicts the proposed dynamic comparator, modi-

fied from the one in [34]. A preamplifier cascaded by a latch pro-vides fast decisions. The dynamic preamplifier uses the NMOSinput pair to obtain higher transconductance as they dom-inates 70% of the noise . Since the static comparator offsetdoes not degrade the linearity and is easily removable by digitalprocessing, the comparator is optimized for the tradeoff betweenthe speed and noise. Low noise is preferable for LSB accuracy(typically, ), while high speed is prefer-able for the MSB decision to avoid the output glitch or latchcontention shown in Fig. 14(c). Some design intuitions for thecomparator are summarized in Table IV, derived based upon[34] and [35].With redundancy, the comparator needs not to be accurate and

fast simultaneously. As the speed and noise of the comparatorwith a clocked switch tail instead of a current source are de-pendent on its common-mode input voltage , which can


TABLE IVCOMPARATOR DESIGN INTUITION

Fig. 14. (a) Schematic of the proposed comparator. (b) Comparator transient common-mode levels [TT corner]. (c) Latch contention and output glitch due to anunsettled DAC.

be inferred3 from Table IV, an adaptive biasing scheme is fur-ther proposed. During MSB conversions, is intentionallylifted by the asymmetric DAC switching to enhance the speedof the comparator by 12% in maximum. The then returnsto its initial value to minimize the noise during LSB cycles, assummarized in Fig. 14(b). The power consumption of the com-parator remains fairly constant at the high-speed biasing as thepreamplifier consumes only the same dynamic precharging en-ergy (proportional to the loading capacitor ). As also revealedin Table IV, adjusting the overdrive of the input pair brings asimilar level of tradeoff as compared to adjusting the loading ca-pacitor [20]. Although the adaptive could induce dy-namic offsets and extra noise, these non-idealities during MSBdecisions can be corrected by the redundancy as MSB decisionerrors due to an unsettled DAC or noise are indistinguishable.4Overall, an extra 80 ps is gained for signal tracking in the worstprocess corner.

3Higher results in a faster speed since the dynamic current dis-charging increases, but a lower average ratio of and , hencelarge noise, due to a shorter time the input pair stays in saturation.

4A low-noise LSB decision is still required since errors due to unsettled DACeventually subside whereas noise is restless.

In addition, the comparator in this work contains positivefeedback loops with enhanced regeneration strength. In casethe main latch consisted of M3~M8 is metastable, the addi-tional positive feedback, borrowed from the output buffers,from to the sources of M4/M7 helps to escape themetastability since the equivalent latch for regenerationincreases.

B. Asynchronous SAR ControllerThe ADC is controlled asynchronously [23] to avoid GHz

clock generation. The digital controller and its operation (seeFig. 15) is similar to that in [26], except that the adopted DACcontroller is actually a differential circuit based on [36], whichprovides fast speed, common-mode rejection for comparatoroutputs and reduced metastability. Further in this work, inorder to reuse and reversely switch prior capacitors accordingto the CRS, the corresponding DAC control is immediatelyreset once the capacitor it driven is detected reusable (by theXOR gates with negligible area and latency). This minimizescircuit switchings (loss) since both the controllers and the DACare required to reset anyhow before the next conversion inconventional designs.


Fig. 15. The asynchronous DAC controller (logic overhead for deactivating CRS not shown).

Fig. 16. Schematic of the bootstrapped sampling switches.

C. Bootstrapped Sampling Switch

Fig. 16 shows the sampling circuit, analogous to that in[37]. The sampling switches receive boosted gatevoltages to have a nearly constant . Two gate-groundedreplica switches compensate for high-frequency

couplings from the drains to the sources of and . Inaddition, dummy capacitors realized by routing parasiticsalong with replica poly gates adjacent to the sources of and

, mitigate the signal-dependent charge injection via .Moreover, the input-tracking time of the ADC is controlledasynchronously by the event-driven manner [1], [38]. As soonas each conversion is complete, the sampling switch turnson to gain extra time for settling, as shown in Fig. 15. Thisalleviates the required bandwidth and slew-rate for the inputbuffer, and tolerates the duty cycle distortion of the receivedADC clocking.

D. Capacitive DAC

Fig. 17(a) shows the customized MOM unit capacitor forthe DAC. Although minimal metal spacing is preferable fora high capacitance density, a smaller capacitor inevitably ex-hibits larger random variations due to the augmented line edgeroughness effect [39]. An unit capacitor of 0.6 fF is sufficientfor an SNR of 60 dB with a full-scaled differential input rangeof 1.6Vpp in this work, but it would take 1 fF to achieve thetarget linearity. Nevertheless, by the merit of the CRS, 0.6 fFrather than 1 fF is used. This reduces the power and area of theDAC by 40%, and relaxes the DAC drivers as well. Note thatthe overheads for splitting and decomposing capacitors in theSC-ADEC and CRS are trivial since all capacitors are realizedby an integer amount of unit capacitors. The matching prop-erty is also preserved the same as that in the binary-weightedcase. The DAC was carefully shielded and checked by 3-DRC extractions to prevent systematic errors, and the CRS tech-nique will compensate for the rest uncontrollable fabricationerrors.


Fig. 17. The layout plan and chip photograph. (a) Aerial and cross-section views of the unit DAC capacitor. (b) The die photograph of the prototype SAR ADC.

Fig. 18. Measured (a) DNL and (b) INL w/i and w/o enabling CRS.

IV. MEASUREMENT RESULTS

Fig. 17(b) shows the ADC fabricated in the UMC 28 nm high-performance low-power (HLP) (Poly/SiON) CMOS process.5The circuit area including MOS decoupling capacitor of 8.4 pFunder the DAC is . The 10 bit ADC operating at240 MS/s and under an 1 V supply consumes only 0.68 mW,41% of which is consumed by the comparator, 22% by the DACand 37% by the controller and the S/H. The reported power andarea exclude those of the ADC peripheral circuits. The DEClogic is carried out off-chip in this prototype. It would contributeanother (1.9% of power) and (1% of area)if implemented on chip.Fig. 18 shows the measured INL and DNL. The CRS im-

proves the INL and DNL by more than one LSB and 0.5 LSB,

5Not the High Performance for Mobile (HPM) process with high-K metalgates and faster speed.

Fig. 19. Measured (a) DNL and (b) INL with and without enabling the CRStechnique.

Fig. 20. Measured mid-code DNLs w/i and w/o enabling CRS.

respectively.6 The originally dominant mid-code DNL is sup-pressed to near zero as expected. To verify that the mismatchcompensation is effective, the maximum DNLs/INLs of 17chips are measured and shown in Fig. 19. Although chips#6, #11, and #14 suffer from relatively poorer linearity, the

6Extra AND gates are added before the reset signal to disable or enable theCRS (not shown in Fig. 15), just for the testing purpose. When the CRS is deac-tivated, the DAC is reconfigured as that in Fig. 3 to allow a sequential switchingwithout reusing.


Fig. 21. The output spectrum. (a) At a low-frequency input. (b) At a near-Nyquist input.

improvement introduced by CRS is more evident for thesechips. This property enhances the yield of ADCs. The worststandard deviations of INL/DNL are reduced by 85% and 68%,respectively, by activating the CRS. Moreover, Fig. 20 revealsthe mid-code DNLs for the 17 chips are all suppressed from

to well below LSB. Good linearity isthus preserved even for smaller inputs ( SFDR at a

input). The INLs of all ADCs are all smaller thanafter the mismatch compensation. The SNDR becomes limitedby the noise rather than the capacitor mismatch. The maximumSNDRs at 50 MS/s and 240 MS/s are 58 dB and 57.1 dB,respectively, as shown in Fig. 21(a). The SNDR degrades to53 dB at the Nyquist frequency, as shown by Fig. 21(b). TheSNDRs and SFDRs at 240 MS/s and 50 MS/s for input signalswith different frequencies are measured and shown in Fig. 22.The SFDR is 73 dB at low input frequencies, and 63 dB atthe Nyquist input. With the CRS, the low-frequency SFDR isimproved by about 7 dB.Compared to the with state-of-the-art ADCs with a similar

resolution and a comparable speed [5]–[8], [11], [12], [25], [40],[41], the proposed ADC consumes at least 80% less area and32% less power as indicated by Table V. Other ADCs withcomparable speed employ either pipelined architecture or mul-tiple comparators, thus costing more power and area. To furthercompare the performance in terms of energy efficiency, bothWalden FOM and Schreier FOM [42] areplotted versus speed in Figs. 1 and 23(a), respectively, for allstate-of-the-art SAR ADCs [42]. Fig. 1 reveals that the pre-sented ADC achieves the best energy efficiency of 7.8 fJ/c.-s.as compared to all SAR ADCs with a bandwidth greater than2 MHz. The improvement is even more pronounced as com-pared to other single-channel SAR ADCs. Fig. 23(a) furthershows that the proposed ADC achieves an of 165.4 dB.For broadband converters whose performance at the Nyquistfrequency is not crucial for applications with an OSR greaterthan one (e.g., serial links), the ENOBs for lower-frequency in-puts are compared. In this context, the proposed ADC reportsan of 4.8 fJ/c.-s. and an of 169.6 dB. Finally,Fig. 23(b) compares the normalized areas versus speed for SARADCs with a resolution of 5~12 bits. SAR-related architecturesare singled out as they generally exhibit smaller areas than thepipeline counterparts. This SAR ADC achieves a higher speedand a better resolution with comparable area efficiency. It sur-vives well in the 28 nm CMOS process node of a low intrinsicdevice gain.

Fig. 22. The measured SNDR/SFDR vs. input frequencies at 50 MS/s and240 MS/s.

V. CONCLUSIONThis paper presents a single-channel, calibration-free 10 bit

240 MS/s SAR ADC. The proposed DAC switching methodsuppresses static DAC non-idealities, such that the unit ca-pacitor is noise-bounded and a minimal circuit circuit areais achieved. In addition, an efficient redundancy generationmethod via splitting the MSB capacitor is presented. Bit er-rors are tolerable within a certain bound, while the total DACcapacitors remain unchanged. Systematic design guidelinescatering to various optimization goals are also discussed. Theproposed ADC is energy- and area-efficient than most contem-porary ADCs and have a low input capacitive load. It offers apromising choice for low-cost data conversion or interleavingto a higher speed.

APPENDIX

Speed Optimization and the Precise Redundancy Equations:For an bit conventional SAR ADC, the DAC settling

time is bounded by , where is thetime constant of the DAC. Similarly, with a redundancy of

, and the added extra cycleas derived in Section II-A. To optimize speed,

assume is the time penalty for an extra cycle, and define aparameter for simplicity. The total conver-sion time is expressed as

. Let, then . Hence, a redundancy

of maxmizes the speed.With redundancy, the tolerable settling error

,for th cycle, where is the capacitance switched in the thcycle, and equals 0.5 for DNL . The equation is


Fig. 23. SAR ADCs from ISSCC/VLSI 1997–2013. (a) Performance comparison of . (b) Normalized area vs. speed.

TABLE VPERFORMANCE SUMMARY AND COMPARISON

self-explained by revisiting Fig. 5,7 and can be rewrittento . Values reported in Fig. 7 and Table II arecalculated by the above equations.

INL Reduction by the CRS:Traditionally, the worst (end-point) INL is estimated by

7When the voltage shift due to fails to settle in time, is erroneous.then switches incorrectly. The rest capacitors will try to com-

pensate for such error. The extra term accounts for a settling-error-freeLSB step and the DNL.

(Equations in [30] are not all correct.) The CRS ensures that. For the MCS combined with the CRS,

. The -term is due to thepoint-symmetry nature of the MCS, while the second nulledterm is as the result of the CRS. The shifts fromto and . All calculated results are summarized inTable III.

Segmented DAC:

The INL/DNLs of an bit segmented DAC are summarizedin Fig. 24. For an bit top-sampling differential SAR ADC, an


Fig. 24. INL and DNL profiles of segmented DAC.

bit DAC is used. The achieved INL/DNL profiles of theMCS scheme with a segmented DAC are also shown inFig. 24 (MCS gains extra DNL reduction by nature). Note thatthe obtained INL/DNLs are worse than that applying the CRSas the segmented MSB DACs still respond to the binary MSBscontaminated by the mismatch.

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Jen-Huan Tsai received the B.S., M.S and Ph.D.degree from Electrical Engineering of NationalTsing Hua University, Taiwan in 2009, 2010, 2014respectively.Since 2014, he has been an Engineer in Mediatek

HsinChu Taiwan, where he has been engaged in re-search and development of wireless communicationsystems. His research interests include analog andmixed-signal integrated circuits design. He was therecipient of the Novatek followship in 2013, andwon the distinguished design award in ASSCC 2014.

Hui-Huan Wang was born in Tainan, Taiwan,R.O.C., in 1990. He received the B.S degrees fromElectrical Engineering Department of NationalTsin-Hua University, Hsinchu, Taiwan in 2012,where he is currently working toward the M.S de-gree. His current research interest is high-resolutionanalog-to-digital converter.

Yang-Chi Yenwas born in Hsinchu, Taiwan, R.O.C.,in 1989. He received the B.S degrees from ElectricalEngineering Department of National Tsin-Hua Uni-versity, Hsinchu, Taiwan in 2012, where he is cur-rently working toward theM.S degree. His current re-search interests are analog circuit and MEMS sensordesign.

Chang-Ming Lai received the B.S., M.S and Ph.D.degree from Electrical Engineering of NationalTsing Hua University, Taiwan in 2003, 2005, 2013respectively.Since 2013, he has been an Engineer in Mediatek

HsinChu Taiwan, where he has been engaged in re-search and development of wireless communicationsystems. His research interests include CMOS RF,analog and mixed-signal integrated circuits design.

Yen-Ju Chen received the B.S. degree in ElectricalEngineering from the National Tsing Hua University,Hsinchu, Taiwan, in 2010. She is currently workingtoward the Ph.D. degree at the Department of Elec-trical Engineering at the National Tsing Hua Univer-sity, Hsinchu, Taiwan. Her research interest is mainlyfocused on the silicon-based RF, mixed-mode inte-grated circuit (PLL/ADC) and system design.

Po-Chiun Huang received the B.S. and Ph.D.degrees in electrical engineering from NationalCentral University, Hsinchu, Taiwan, in 1992 and1998, respectively. During the summers of 1992and 1996, he was an Intern with the Computer andCommunication Research Laboratory, ITRI, and Lu-cent Technology, during which time he investigateddesign techniques for optical and RF communicationsystems. From 2000 to 2002, he was with MediaTekInc., where he was involved with chipset design foroptical storage products. In 2002, he joined National

Tsing Hua University, Hsinchu, Taiwan.

Ping-Hsuan Hsieh was born in Taipei, Taiwan.She received the B.S. degree from National TaiwanUniversity, Taipei, Taiwan, in 2001, and the M.S.and Ph.D. degrees from the University of California,Los Angeles, in 2004 and 2009, respectively, all inelectrical engineering. She was an Intern with TexasInstruments, Dallas, TX, in the summers 20042006.From 2009 to 2011, she was with the IBM T.J.Watson Research Center, Yorktown Heights, NY,where she worked on the design of mixed-signalintegrated circuits for high-speed serial data com-

munication. In 2011, she joined the Electrical Engineer- ing Department ofNational Tsing Hua University, Hsinchu, Taiwan, where she is currently anAssistant Professor. Her research interests focus on mixed- signal integratedcircuit designs for high-speed electrical data communications, clocking andsynchronization systems, and energy-harvesting systems for wireless sensornetworks and machine-to-machine applications.


Hsin Chen was born in 1974 in Taiwan. He receivedthe B.S. and M.S. degrees in electrical engineeringin 1996 and 1998, respectively, from NationalTsing-Hwa University (NTHU), Taiwan. After obli-gating two years' military service in the Taiwan AirForce, he received the Ph.D. degree in electronics in2004 from Edinburgh University, Edinburgh, U.K.Since then, he was appointed Assistant Professorwith the Department of Electrical Engineering,NTHU. His electrical engineering expertise lies inanalog- and mixed-mode VLSI design.

Chao-Cheng Lee received the B.S. degree fromNational Chiao-Tung University in 1988 in electricalengineering. He received the M.S. degree fromNational Taiwan University in 1990 in physics.He joined Realtek Semiconductor in 1992 and iscurrently the Senior Vice President of Engineeringin Realtek. His research interests includes PLL,filter, high speed ADC/DAC , Serdes, and mismatchcalibration. He has more than 30 U.S. patents grantedor pending. He is the winner of 18th IndustrialTechnology Advancement Award, Taiwan.

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