V1.1 | 2021-06-11

Supported by Embedded Software

10BASE-T1S Learn To Run

2

1. All IP Car

2. Extensions in AUTOSAR

3. Areas of Investigation

4. Evaluation SW Setup Based on the Infineon Evaluation Kit

Agenda

3

10BASE-T1S as Replacement for Lower Bandwidth NetworksAll IP Car

IP as

well-known common “language”

proven in use technology

enabler for E/E architecture trends and service-based communication

and Ethernet is the naturally associated Network Access Layer

4

It’s more than just physical layer compliance

Introducing an Additional Network Access LayerAll IP Car

The digital eco-system must be “ready” Tools, data models and databases SW AUTOSAR …

5

10BASE-T1S was introduced as new concept in R20-11

Further refinement is currently ongoing within AUTOSAR It’s Ethernet the upper layer stack remains untouched

Utilize the benefits of the strictly layered architecture

Encapsulate the changes in the MCAL layer

10BASE-T1S Within AUTOSAR Classic PlatformExtensions in AUTOSAR

 Ethernet Switch Driver

 Ethernet Driver

 Ethernet Transceiver

Driver

EthTrcv

EthEthSwt

6

 Ethernet Driver

10BASE-T1S specific initializations Depending on actual Transceiver device Timeline is depending on documentation and

device availability

Diagnostic Interface

Extension of the Existing MICROSAR SolutionAreas of Investigation

 Error and State Management  Transmit Buffer Management

 Ethernet Transceiver Driver

7

Fixed Compile Environment Infineon TriBoard TC377

plus specific 10BASE-T1S transceiver

Subset of available MICROSAR components Tools

Necessary extensions to specific MICROSAR components

Used for internal investigations

SIP available on demand

Specific SIP – Software Integration PackageEvaluation SW Setup Based on the Infineon Evaluation Kit

10BASE-T1S Learn To Run – Supported by Embedded Software

Vector Automotive Ethernet Symposium 2021

Josef Nöbauer, Harald Zweck

o Microcontroller board• Controller AURIX™ TC377TX• 2 x Ethernet MAC• CAN• FlexRay

o PHY board• 10BT1S Transceiver• PoDL* logic• Connector for wire

oAutoSAR SWo See Vector

o Cable & connectors

Evaluation Kit 10Base-T1SBuilding Blocks at Board Level

22021-06-15

*PoDL: Power over Data Line

o Interface optionso Option MII

• Microcontroller provides− Ethernet MAC

• PHY provides− PLCA logic− analog Front End (FE)

o Option SPI• PHY provides− Ethernet MAC− PLCA logic− Analog Front End (FE)

o Option 3-Pin interface• Microcontroller provides− Ethernet MAC, PLCA logic• PHY provides− Analog Front End (FE)

Evaluation Kit 10Base-T1SSystem Configuration Options

3

Controller Board

CANFlexRayEthernet

Connector

AURIX™

SPI

Controller Board

CANFlexRayEthernet

Connector

AURIX™

MII

Controller Board

CANFlexRayEthernet

Connector

AURIX™

3-Pin

wiresP

HY

Board

ConnectorMII

PLCAAnalog FE

PH

Y

DiscretesConnector

wires

PH

Y B

oardConnector

MII

PLCAAnalog FE

PH

Y

DiscretesConnector

ETH MAC

wires

PH

Y B

oard

ConnectorMII

Analog FEPH

Y

DiscretesConnector

Option MII Option SPI Option 3-Pin

2021-06-15

o Interface optionso Option MII

• Microcontroller provides− Ethernet MAC

• PHY provides− PLCA logic− analog Front End

o Option SPI• PHY provides− Ethernet MAC− PLCA logic− Analog Front End

o Option 3-Pin interface• Microcontroller provides− Ethernet MAC, PLCA logic• PHY provides− Analog Front End

Evaluation Kit 10Base-T1SSystem Configuration Options

4

Controller Board

CANFlexRayEthernet

Connector

AURIX™

SPI

Controller Board

CANFlexRayEthernet

Connector

AURIX™

MII

Controller Board

CANFlexRayEthernet

Connector

AURIX™

3-Pin

wiresP

HY

Board

ConnectorMII

PLCAAnalog FE

PH

Y

DiscretesConnector

wires

PH

Y B

oardConnector

MII

PLCAAnalog FE

PH

Y

DiscretesConnector

ETH MAC

wires

PH

Y B

oard

ConnectorMII

Analog FEPH

Y

DiscretesConnector

Option MII Option SPI Option 3-Pin

2021-06-15

Evaluation Kit 10Base-T1SBuilding Blocks at Functional Level

5

Ethernet MACTransmit

DMAs/QueuesCredit Based

Shaper

802.1AS

ReceiveDMAs/QueuesAddress & Tag

Filters

802.1AS

AURIX™ Microcontroller

MII

CPU & RAM

Ethernet Stack

o Controller cores & SW Stack(s)• CPUs• RAM• Flash

o Ethernet MAC (10MBaud / 100MBaud / 1GBaud)• Queues for sending & receiving• Shapers in the transmit path• Filters in the receive path• Time stamping units for 802.1AS

o MII interface to / from PHY• MII interface for data transfer• MDC/MDIO interface for PHY control & status

o PHY• PCS/PMA logic (IEEE 802.3)• PLCA collision avoidance• Analog front end

MIIPLCAPCS/PMA PCS/PMA

Analog FE10Base-T1S PHY

2021-06-15

PCS: Physical Coding SublayerPMA: Physical Medium AttachmentPLCA: Physical Layer Collision Avoidance

Evaluation Kit 10Base-T1SBuilding Blocks at Functional Level

6

Ethernet MACTransmit

DMAs/QueuesCredit Based

Shaper

802.1AS

ReceiveDMAs/QueuesAddress & Tag

Filters

802.1AS

AURIX™ Microcontroller

MII

CPU & RAM

Ethernet Stack

o Controller cores & SW Stack(s)• CPUs• RAM• Flash

o Ethernet MAC (10MBaud / 100MBaud / 1GBaud)• Queues for sending & receiving• Shapers in the transmit path• Filters in the receive path• Time stamping units for 802.1AS

o MII interface to / from PHY• MII interface for data transfer• MDC/MDIO interface for PHY control & status

o PHY• PCS/PMA logic (IEEE 802.3)• PLCA collision avoidance• Analog front end

MIIPLCAPCS/PMA PCS/PMA

Analog FE10Base-T1S PHY

2021-06-15

PCS: Physical Coding SublayerPMA: Physical Medium AttachmentPLCA: Physical Layer Collision Avoidance

Evaluation Kit 10Base-T1SBuilding Blocks at Functional Level

7

Ethernet MACTransmit

DMAs/QueuesCredit Based

Shaper

802.1AS

ReceiveDMAs/QueuesAddress & Tag

Filters

802.1AS

AURIX™ Microcontroller

MII

CPU & RAM

Ethernet Stack

o Controller cores & SW Stack(s)• CPUs• RAM• Flash

o Ethernet MAC (10MBaud / 100MBaud / 1GBaud)• Queues for sending & receiving• Shapers in the transmit path• Filters in the receive path• Time stamping units for 802.1AS

o MII interface to / from PHY• MII interface for data transfer• MDC/MDIO interface for PHY control & status

o PHY• PCS/PMA logic (IEEE 802.3)• PLCA collision avoidance• Analog front end

MIIPLCAPCS/PMA PCS/PMA

Analog FE10Base-T1S PHY

2021-06-15

PCS: Physical Coding SublayerPMA: Physical Medium AttachmentPLCA: Physical Layer Collision Avoidance

Evaluation Kit 10Base-T1SBuilding Blocks at Functional Level

8

Ethernet MACTransmit

DMAs/QueuesCredit Based

Shaper

802.1AS

ReceiveDMAs/QueuesAddress & Tag

Filters

802.1AS

AURIX™ Microcontroller

MII

CPU & RAM

Ethernet Stack

o Controller cores & SW Stack(s)• CPUs• RAM• Flash

o Ethernet MAC (10MBaud / 100MBaud / 1GBaud)• Queues for sending & receiving• Shapers in the transmit path• Filters in the receive path• Time stamping units for 802.1AS

o MII interface to / from PHY• MII interface for data transfer• MDC/MDIO interface for PHY control & status

o PHY• PCS/PMA logic (IEEE 802.3)• PLCA collision avoidance• Analog front end

MIIPLCAPCS/PMA PCS/PMA

Analog FE10Base-T1S PHY

2021-06-15

PCS: Physical Coding SublayerPMA: Physical Medium AttachmentPLCA: Physical Layer Collision Avoidance

Evaluation Kit 10Base-T1SBuilding Blocks at Functional Level

9

Ethernet MACTransmit

DMAs/QueuesCredit Based

Shaper

802.1AS

ReceiveDMAs/QueuesAddress & Tag

Filters

802.1AS

AURIX™ Microcontroller

MII

CPU & RAM

Ethernet Stack

o Controller cores & SW Stack(s)• CPUs• RAM• Flash

o Ethernet MAC (10MBaud / 100MBaud / 1GBaud)• Queues for sending & receiving• Shapers in the transmit path• Filters in the receive path• Time stamping units for 802.1AS

o MII interface to / from PHY• MII interface for data transfer• MDC/MDIO interface for PHY control & status

o PHY• PCS/PMA logic (IEEE 802.3)• PLCA collision avoidance• Analog front end

MIIPLCAPCS/PMA PCS/PMA

Analog FE10Base-T1S PHY

2021-06-15

PCS: Physical Coding SublayerPMA: Physical Medium AttachmentPLCA: Physical Layer Collision Avoidance

Evaluation Kit 10Base-T1SData Flow through Functional Building Blocks

102Et

her

net

MA

C

Queues

Shaper

802.1AS

Filters

802.1AS

AURIX™ Microcontroller

MII

o Ethernet MAC (10MBaud / 100MBaud / 1GBaud)• Queues for sending & receiving• Shapers in the transmit path• Filters in the receive path• Time stamping units for 802.1AS

o MII interface to / from PHY• MII interface for data transfer• MDC/MDIO interface for PHY control & status

o PHY• PCS/PMA logic (IEEE 802.3)• PLCA collision avoidance• Analog front end

MIIPLCAPCS/PMA PCS/PMAAnalog FE

10Base-T1S PHY

Queues

MDC/MDIO

DMAs DMAs

MICROSARTransceiver DriverEthernet Stack

Evaluation Kit 10Base-T1SData Flow through Functional Building Blocks

112Et

her

net

MA

C

Queues

Shaper

802.1AS

Filters

802.1AS

AURIX™ Microcontroller

MII

o Ethernet MAC (10MBaud / 100MBaud / 1GBaud)• Queues for sending & receiving• Shapers in the transmit path• Filters in the receive path• Time stamping units for 802.1AS

o MII interface to / from PHY• MII interface for data transfer• MDC/MDIO interface for PHY control & status

o PHY• PCS/PMA logic (IEEE 802.3)• PLCA collision avoidance• Analog front end

MIIPLCAPCS/PMA PCS/PMAAnalog FE

10Base-T1S PHY

Queues

MDC/MDIO

DMAs DMAs

MICROSARTransceiver DriverEthernet Stack

Evaluation Kit 10Base-T1SData Flow through Functional Building Blocks

122Et

her

net

MA

C

Queues

Shaper

802.1AS

Filters

802.1AS

AURIX™ Microcontroller

MII

o Ethernet MAC (10MBaud / 100MBaud / 1GBaud)• Queues for sending & receiving• Shapers in the transmit path• Filters in the receive path• Time stamping units for 802.1AS

o MII interface to / from PHY• MII interface for data transfer• MDC/MDIO interface for PHY control & status

o PHY• PCS/PMA logic (IEEE 802.3)• PLCA collision avoidance• Analog front end

MIIPLCAPCS/PMA PCS/PMAAnalog FE

10Base-T1S PHY

Queues

MDC/MDIO

DMAs DMAs

MICROSARTransceiver DriverEthernet Stack

Evaluation Kit 10Base-T1SData Flow through Functional Building Blocks

132Et

her

net

MA

C

Queues

Shaper

802.1AS

Filters

802.1AS

AURIX™ Microcontroller

MII

o Ethernet MAC (10MBaud / 100MBaud / 1GBaud)• Queues for sending & receiving• Shapers in the transmit path• Filters in the receive path• Time stamping units for 802.1AS

o MII interface to / from PHY• MII interface for data transfer• MDC/MDIO interface for PHY control & status

o PHY• PCS/PMA logic (IEEE 802.3)• PLCA collision avoidance• Analog front end

MIIPLCAPCS/PMA PCS/PMAAnalog FE

10Base-T1S PHY

Queues

MDC/MDIO

DMAs DMAs

MICROSARTransceiver DriverEthernet Stack

Evaluation Kit 10Base-T1SController / PHY Interface

14

Microcontroller

MII

MII

10Base-T1S PHY

TX_CLK TX_ENTX_ER TXD0..TXD3

o MII Transmit direction

• Data lines TXD• Transmit enable and error TX_EN, TX_ER• Transmit clock TX_CLK• For 10Base-T1S the transmit clock runs at 2.5MHz

o MII Receive direction

• Data lines RXD• Receive data available and error RX_DV, RX_ER• Reveive clock RX_CLK• For 10Base-T1S the receive clock runs at 2.5MHz

Microcontroller

MII

MII

10Base-T1S PHY

RX_CLK RX_DVRX_ER RXD0..RXD3

2021-06-15

Evaluation Kit 10Base-T1SController / PHY Interface

15

Microcontroller

MII

MII

10Base-T1S PHY

COL CRS

o Data flow control

• Half duplex signals COL & CRS• PHY pushes back MAC transmitting data if the media (cable) is not available

• For 10Base-T1S the PHY PLCA logic uses the signals to hold the MAC• The PHY PLCA logic releases the MAC if the transmit opportunity window is valid

2021-06-15

Evaluation Kit 10Base-T1SBuilding Blocks PHY Board

16

PH

Y B

oard

Connector to AURIX Board

MII

MIIPLCAPCS/PMA PCS/PMA

Analog FE

PH

Y

Connector to wires

Choke

PoDL

MD

CM

DIO

o Connectors

• Interface to AURIX controller• Interface to medium (wires)

o 10Base-T1S PHY

o Power over Data Line (PoDL)

o Capacitors for AC coupling

o Common mode choke

o Stubs

2021-06-15

Evaluation Kit 10Base-T1SBuilding Blocks PHY Board

17

PH

Y B

oard

Connector to AURIX Board

MII

MIIPLCAPCS/PMA PCS/PMA

Analog FE

PH

Y

Connector to wires

Choke

PoDL

MD

CM

DIO

2021-06-15

o Connectors

• Interface to AURIX controller• Interface to medium (wires)

o 10Base-T1S PHY

o Power over Data Line (PoDL)

o Capacitors for AC coupling

o Common mode choke

o Stubs

Evaluation Kit 10Base-T1SBuilding Blocks PHY Board

18

PH

Y B

oard

Connector to AURIX Board

MII

MIIPLCAPCS/PMA PCS/PMA

Analog FE

PH

Y

Connector to wires

Choke

PoDL

MD

CM

DIO

2021-06-15

o Connectors

• Interface to AURIX controller• Interface to medium (wires)

o 10Base-T1S PHY

o Power over Data Line (PoDL)

o Capacitors for AC coupling

o Common mode choke

o Stubs

Evaluation Kit 10Base-T1SBuilding Blocks PHY Board

19

PH

Y B

oard

Connector to AURIX Board

MII

MIIPLCAPCS/PMA PCS/PMA

Analog FE

PH

Y

Connector to wires

Choke

PoDL

MD

CM

DIO

2021-06-15

o Connectors

• Interface to AURIX controller• Interface to medium (wires)

o 10Base-T1S PHY

o Common mode choke

o Capacitors for AC coupling

o Power over Data Line (PoDL)

o Stubs

Evaluation Kit 10Base-T1SBuilding Blocks PHY Board

20

PH

Y B

oard

Connector to AURIX Board

MII

MIIPLCAPCS/PMA PCS/PMA

Analog FE

PH

Y

Connector to wires

Choke

PoDL

MD

CM

DIO

2021-06-15

o Connectors

• Interface to AURIX controller• Interface to medium (wires)

o 10Base-T1S PHY

o Common mode choke

o Capacitors for AC coupling

o Power over Data Line (PoDL)

o Stubs

Evaluation Kit 10Base-T1SBuilding Blocks PHY Board

21

PH

Y B

oard

Connector to AURIX Board

MII

MIIPLCAPCS/PMA PCS/PMA

Analog FE

PH

Y

Connector to wires

Choke

PoDL

MD

CM

DIO

2021-06-15

o Connectors

• Interface to AURIX controller• Interface to medium (wires)

o 10Base-T1S PHY

o Common mode choke

o Capacitors for AC coupling

o Power over Data Line (PoDL)

o Stubs

Evaluation Kit 10Base-T1SBuilding Blocks PHY Board

22

PH

Y B

oard

Connector to AURIX Board

MII

MIIPLCAPCS/PMA PCS/PMA

Analog FE

PH

Y

Connector to wires

Choke

PoDL

MD

CM

DIO

2021-06-15

o Connectors

• Interface to AURIX controller• Interface to medium (wires)

o 10Base-T1S PHY

o Common mode choke

o Capacitors for AC coupling

o Power over Data Line (PoDL)

o Stubs

Evaluation Kit 10Base-T1SSystem Configuration Example

23

o Daisy chain configuration

o Stubs location in the middle

o Power over Data Line (PoDL)

PHY BoardPHY

Con

nec

tor

PoDL

AURIX™ Board

Con

nector

AURIX™

MII

Con

nec

tor

PHY BoardPHY

Con

nec

tor

PoDL

AURIX™ BoardC

onn

ector

AURIX™

MII

Con

nec

tor

PHY BoardPHY

Con

nec

tor

PoDL

AURIX™ Board

Con

nector

AURIX™

MII

Con

nec

tor

Central power supply

Poweranddata

Poweranddata

2021-06-15

10Base-T1SStandardization Overview (as of begin of 2021)

IEEE 802.3cg

Ethernet10Base-T1S PHY

10Base-T1S

Interface

To / from Bus

IEEE 802.3cg

OPEN TC6 / TC14

OPEN TC14

Microcontroller

EthernetPLCA-MAC

Interface

EthernetDriver & StackAutoSAR

IEEE 802.3cg

› SW components for PLCA: AutoSAR

› PLCA: IEEE 802.3cg, Clause 148

› SPI interface MAC to PHY: OPEN TC6/TC14 JWG › Analog PHY interface MAC to PHY: OPEN TC14› MII interface: IEEE Standard

› 10Base-T1S: IEEE 802.3cg, Clause 147

› Test suite 10Base-T1S: OPEN TC14

› EPL*: IEEE 802.3cg, Clause 147

*EPL: Electrical Physical Layer *PLCA: Physical Layer Collision Avoidance

242021-06-15

› Extended functionalities (diagnosis etc.) OPEN TC14

8 © 2021. Vector Informatik GmbH. All rights reserved. Any distribution or copying is subject to prior written approval by Vector. V1.1 | 2021-06-11

Author:Nöbauer, JosefVector Germany

For more information about Vectorand our products please visit

www.vector.com

Zweck, HaraldInfineon