1 ERD 2010 ITRS Summer Conference – San Francisco – 14 July, 2010 ITRS Public Conference Emerging Research Devices Jim Hutchby – SRC July 14, 2010 2010

1 ERD 2010 ITRS Summer Conference – San Francisco – 14 July, 2010

ITRS Public ConferenceEmerging Research Devices

Jim Hutchby – SRCJuly 14, 2010

2010 ERD Chapter Emerging Research Memory Devices Emerging Research Logic Devices Emerging Research Architectures

2 ERD 2010 ITRS Summer Conference – San Francisco 14 July 2010

Hiroyugi Akinaga AIST Tetsuya Asai Hokkaido U. Yuji Awano Keio U. George Bourianoff Intel Michel Brillouet CEA/LETI Joe Brewer U. Florida John Carruthers PSU Ralph Cavin SRC An Chen AMD U-In Chung Samsung Byung Jin Cho KAIST Sung Woong Chung Hynix Luigi Colombo TI Shamik Das Mitre Erik DeBenedictis SNL Simon Deleonibus LETITetsuo Endoh Tohuku U. Paul Franzon NCSU Akira Fujiwara NTT Christian Gamrat CEA Mike Garner Intel Dan Hammerstrom PSU Wilfried Haensch IBM Tsuyoshi Hasegawa NIMS Shigenori Hayashi Panasonic Dan Herr SRC Toshiro Hiramoto U. Tokyo Mutsuo Hidaka ISTEC Jim Hutchby SRC Adrian Ionescu EPFL Kiyoshi Kawabata Renesas Tech Seiichiro Kawamura JST Rick Kiehl U.C. Davis Suhwan Kim Seoul Nation UHyoungioon Kim Samsung

HDae-Hong Ko Yonsei U. Hiroshi Kotaki Sharp Atsuhiro Kinoshita ToshibaZoran Krivokapic AMD Phil Kuekes HP Kee-Won Kwon Seong Kyun Kwan U. Jong-Ho Lee Kyungpook Nation U. Jong-Ho Lee Hanyang U. Kee-won Kwon Sungkyunkwan U. Lou Lome IDA Hiroshi Mizuta U. SouthamptonFerdinand Peper NICT Yaw Obeng NIST Dave Roberts Nantero Sadas Shankar IntelShintro Sato AISTAtsushi Shiota JSR MicroTakahiro Shinada Waseda U.Masayuki Shirane NEC Satoshi Sugahara Tokyo Tech Shin-ichi Takagi U. Tokyo Ken Uchida Tokyo Tech Thomas Vogelsang Rambus Yasuo Wada Toyo U. Rainer Waser RWTH A Jeff Welser NRI/IBM Franz Widdershoven NXP Philip Wong Stanford U. Dirk Wouters IMEC Kojiro Yagami Sony David Yeh SRC/TI In-Seok Yeo Samsung In-K Yoo SAIT Yuegang Zhang LLLab Victor Zhirnov SRC

Emerging Research Devices Working Group


year

Beyond CMOS

Elements

Existing technologies

New technologies

Evolution of Extended CMOS

More Than Moore

ERD-WG in Japan


2010-2011 ERD/ERM Workshops Workshop topic Date Location Meeting Assessment of Emerging Research Memory Devices

April 6-7 2010

Barza, Italy ITRS Spring meeting

Graphene Logic and STT Logic Devices

Sept. 17, 2010

Sevilles, Spain

ESSDERC

Materials for STT-MRAM and Redox RRAM

Nov. 30, 2010

Tsukuba, Japan

ITRS Winter meeting

III-V MOSFETs Dec.9, 2010

San Francisco, USA

IEDM

More than Moore Emerging Research Technologies

April 2011

Berlin, Germany

ITRS Spring meeting

Co-sponsored by the National Science Foundation


Increased Scope of Emerging Research Devices Chapter

Scope of Emerging Research Memory Devices increased in 2011 to include “Storage Class Memory” New More-than-Moore Section


2009 ERD Chapter Emerging Memory Devices

Emerging Logic Devices

Emerging Architectures


Resistive Memories

Memory Technology Entries

Redox Memory−Nanoionic memory−Electrochemical memory− Fuse/Antifuse memoryMolecular Memory

Electronic Effects Memory− Charge trapping− Metal-Insulator Transition− FE barrier effects

Spin Transfer Torque MRAMNanoelectromechanical Nanowire PCMMacromolecular (Polymer)


Resistive Memories

Memory Technology Entries

Redox Memory−Nanoionic memory−Electrochemical memory− Fuse/Antifuse memoryMolecular Memory

Electronic Effects Memory− Charge trapping− Metal-Insulator Transition− FE barrier effects

Spin Transfer Torque MRAMNanoelectromechanical Nanowire PCMMacromolecular (Polymer)

Capacitive MemoryFeFET Memory


ERD/ERM Memory Technology Assessment Workshop

Workshop (For each of eight technologies) (April 6)– Receive expert inputs (pro & con)– Clarify status, potential, and remaining challenges– Formulate discussion/decision points to be considered in the

Wednesday ERD/ERM meeting ERD/ERM Working Group Meeting (April 7)

– Discuss and reach approximate consensus on potential & challenges for each technology

– Determine whether any of the eight candidate memory technologies is sufficiently promising and mature to benefit from accelerated development (Scale beyond the 16nm generation)


ERD/ERM Memory Technology Assessment Workshop

ITRS ERD/ERM identified two emerging memory technologies for accelerated research & development:

1) STT-MRAM and 2) Redox Resistive RAM

Redox Memory Cell STT-Memory Cell


One Diode – One Resistor (1D1R) Memory Cell

H-S. P. Wong – Stanford U.

12 ERD 2010 ITRS Summer Conference – San Francisco 14 July 2010 12

Content changes for Emerging Research Memory Section

Include Storage Class Memory in Emerging Research Memory Section

Transfer Nano Wire Phase-Change Memory to Transition Table and to PIDS and FEP

Transfer Spin Transfer Torque Magnetic RAM (STT-MRAM) to Transition Table and to PIDS and FEP

Reorganize emerging research memory classifications – New category named “Redox” RRAM

.






Logic Technology Tables

Table 1 – MOSFETs:Extending MOSFETs

to the end of the roadmap

_____________

CNT FETsGraphene nanoribbon

FETsNanowire FETs

Table 2- UnconventionalFETS, Charge-based

Extended CMOS Devices

_______________

Tunnel FETI-MOS

Spin FETSpin MOSFETNEMS switchExcitonic FET

MottFET

Table 3 - Non-FET, Non Charge-based ‘Beyond

CMOS devices

_______________

Collective Magnetic DevicesSpin Transfer Torque Logic Moving domain wall devicesPseudo-spintronic DevicesNanomagnetic (M:QCA)

Molecular SwitchAtomic Switch


ERD/ERM TWG Recommendation

The ERD/ERM TWGs recommend to the International Roadmap Committee ---

Carbon-based Nanoelectronics to include carbon nanotubes and

graphene

For additional resources and detailed road mapping for ITRS as promising technologies targeting commercial demonstration in the 5-10 year horizon.


Graphene Electronics: Conventional & Non-conventional

Conventional Devices

Cheianov et al. Science (07)

Graphene Veselago lense

FETBand gap engineered Graphene nanoribbons

Nonconventional Devices

Trauzettel et al. Nature Phys. (07)

Graphene pseudospintronics

Son et al. Nature (07)

Graphene Spintronics

Graphene quantum dot

(Manchester group)

P. Kim – Columbia U.

17 ERD 2010 ITRS Summer Conference – San Francisco 14 July 2010 17

Content changes for Emerging Research Logic Section

Add a new section on More-than-More with a focus on wireless devices

Transfer III-V and Ge MOSFETs to PIDS & FEP

Complete transfer of unconventional geometry MOSFETs to PIDS & FEP

Transfer SET to More-than-Moore section

Add spin transfer torque (STT) majority gate logic

Add Mott FET device

.






Emerging Architectures Benchmarking Devices

Memory


Four Architectural Projections

1) Hardware Accelerators execute selected functions faster than software performing it on the CPU.

2) Alternative switches often exhibit emergent, idiosyncratic behavior. We should exploit them.

3) CMOS is not going away anytime soon.

4) New switches may improve high utilization accelerators


Matching Logic Functions & New Switch Behaviors

Single Spin

Spin Domain

Tunnel-FETs

NEMS

MQCA

Molecular

Bio-inspired

CMOL

Excitonics

?

Popular Accelerators New Switch Ideas

Encrypt / Decrypt

Compr / Decompr

Reg. Expression Scan

Discrete COS Trnsfrm

Bit Serial Operations

H.264 Std Filtering

DSP, A/D, D/A

Viterbi Algorithms

Image, Graphics

Example: Cryptography Hardware AccelerationOperations required: Rotate, Byte Alignment, EXORs, Multiply, Table LookupCircuits used in Accel: Transmission Gates (“T-Gates”)New Switch Opportunity: A number of new switches (i.e. T-FETs) don’t have

thermionic barriers: won’t suffer from CMOS Pass-gate VT drop, Body Effect, or Source-Follower delay.

Potential Opportunity: Replace 4 T-Gate MOSFETs with 1 low power switch.


Emerging Architectures Benchmarking

Memory


Preparing for re-write of 2011 ERD Chapter With ERM, conducting five FxF workshops co-sponsored by NSF

Memory Technology Assessment Workshop (April 2010) Graphene-based and spin-based logic devices (Sept. 2010) Materials issues with Redox-RRAM & STT-MRAM (Nov 2010) III- V MOSFETs: Performance assessment and gating issues (Dec.2010) More than Moore Workshop (April 2011)

Logic Devices Propose transfer of III-V MOSFET n-channel and Ge p-channel replacement materials

from ERD to PIDS and FEP in 2011 Propose transfer of non-conventional geometry MOSFETs to PIDS/FEP JN 2011

Memory Devices A new taxonomy for categorizing resistive memories introduced. An assessment of new memory devices was completed: STT-MRAM and Redox-RRAM

identified for accelerated research and development STT-M RAM & NW PCM proposed to fully transfer to PIDS and FEP in 2011 Will expand scope of memory section to include Storage Class Memory

Adding a new section for More-than-Moore Emerging Research Technologies Architecture

Architectural work for benchmarking “Beyond CMOS” devices continues Update Memory Architecture section

ERD – Key Messages

Documents

1 ERD 2010 ITRS Summer Conference – San Francisco – 14 July, 2010 ITRS Public Conference Emerging Research Devices Jim Hutchby – SRC July 14, 2010 2010