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Advanced Digital DesignAdvanced Digital DesignAsynchronous Design: Research ConceptAsynchronous Design: Research Concept
by A. Steininger and M. DelvaiVienna University of Technology
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Reference HardwareReference Hardware
Outcome: AspearOutcome: Aspear22 Four stage pipelineFour stage pipeline Configurable data path (16 / 32 bits)Configurable data path (16 / 32 bits) AMBA interfaceAMBA interface
Challenges: Challenges: Handle improved complexity Handle improved complexity Asynchronous AMBA interface Asynchronous AMBA interface Tools interface Tools interface
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Design Flow OptimizationDesign Flow Optimization
Current design flow requires an “FSL-based” VHDL Current design flow requires an “FSL-based” VHDL style code:style code: manual register placementmanual register placement
explicit handshake signal connectionexplicit handshake signal connection
stable functionstable function
Improved design flowImproved design flow use synchronous designs as starting pointuse synchronous designs as starting point
synthesize design using an AND-OR-INV librarysynthesize design using an AND-OR-INV library
replace standard gates with corresponding FSL gatesreplace standard gates with corresponding FSL gates
perform automatic handshake connections and phase inverter perform automatic handshake connections and phase inverter insertioninsertion
resynthesize the designresynthesize the design
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Design Flow OptimizationDesign Flow Optimization
Outcome Outcome
Automatic conversion of synchronous designs Automatic conversion of synchronous designs
to FSL circuitsto FSL circuits
Challenges:Challenges:
Identification of circuit structuresIdentification of circuit structures
Placement of phase-invertersPlacement of phase-inverters
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Research Concept Research Concept
FSL
Basic Gates Optimization(MA)
Design Flow Optimization(MA)
Reference Hardware(MA)
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Basic Gates OptimizationBasic Gates Optimization
Outcome: Efficient FSL gates forOutcome: Efficient FSL gates for FPGA technologiesFPGA technologies ASIC technologies ASIC technologies
Challenge: Challenge: Preserve delay insensitivityPreserve delay insensitivity Reduce size/transistor countReduce size/transistor count Limit the performance penaltyLimit the performance penalty
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Research Concept Research Concept
FSL
Fault Tolerance: RADIAL(Project)
Basic Gates Optimization(MA)
Design Flow Optimization(MA)
Reference Hardware(MA)
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Fault Tolerance: Fault Tolerance: RADIALRADIAL
Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to FSL circuits tolerate transient fault(s) due to
the inherent consistency checkthe inherent consistency check
Register
(00)(11)(11)(00)(00)
(00)(11)(11)(00)(00)
(10)(01)(10)(10)(10)
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Fault Tolerance : Fault Tolerance : RADIALRADIAL
Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to FSL circuits tolerate transient fault(s) due to
the inherent consistency checkthe inherent consistency check
Register
(00)(11)(11)(00)(00)
(11)(11)(00)(00)
(10)(01)(10)(10)(10)
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Fault Tolerance : Fault Tolerance : RADIALRADIAL
Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to FSL circuits tolerate transient fault(s) due to
the inherent consistency checkthe inherent consistency check
Register
(00)(11)(11)(00)(00)
(11)(11)
(00)
(10)
(10)
(01)(10)
(10)
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Fault Tolerance : Fault Tolerance : RADIALRADIAL
Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to FSL circuits tolerate transient fault(s) due to
the inherent consistency checkthe inherent consistency check
Register
(00)(11)(11)(00)(00)
(11)
(00)
(10)(01)
(10)(10)
(10)
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Fault Tolerance : Fault Tolerance : RADIALRADIAL
Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to FSL circuits tolerate transient fault(s) due to
the inherent consistency checkthe inherent consistency check
Register
(00)(11)(11)(00)(00)
(11)
(00)
(10)(00)
(10)(10)
(10)
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Fault Tolerance : Fault Tolerance : RADIALRADIAL
Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to FSL circuits tolerate transient fault(s) due to
the inherent consistency checkthe inherent consistency check
Register
(00)(11)(11)(00)(00)
(11)
(00)
(10)(01)
(10)(10)
(10)
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Fault Tolerance : Fault Tolerance : RADIALRADIAL
Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to FSL circuits tolerate transient fault(s) due to
the inherent consistency checkthe inherent consistency check
Register
(00)(11)(11)(00)(00)
(01)
(00)
(10)(01)
(10)(10)
(10)
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Fault Tolerance : Fault Tolerance : RADIALRADIAL
Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to FSL circuits tolerate transient fault(s) due to
the inherent consistency checkthe inherent consistency check
Register
(00)(11)(11)(00)(00)
(10)
(00)
(10)(01)
(10)(10)
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Fault Tolerance : Fault Tolerance : RADIALRADIAL
Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to FSL circuits tolerate transient fault(s) due to
the inherent consistency checkthe inherent consistency check
Register
(00)(11)(11)(00)(00)
(10)
(10)(01)
(10)(10)
(10)(01)(10)(10)(10)
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Fault Tolerance : Fault Tolerance : RADIALRADIAL
Also combinational logic masks transient faultsAlso combinational logic masks transient faults
FSL tolerates more than one transient fault at the same FSL tolerates more than one transient fault at the same
timetime
But: But:
If the critical path is affected, then the transient fault If the critical path is affected, then the transient fault
will not be maskedwill not be masked
However FSL shows still a higher robustness However FSL shows still a higher robustness
compared to synchronous logiccompared to synchronous logic
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Fault Tolerance : Fault Tolerance : RADIALRADIAL
Possible improvements:Possible improvements:
Hardware redundancyHardware redundancy
Duplication of the critical path only?Duplication of the critical path only?
Temporal redundancyTemporal redundancy
Two phases => stuck @ faults detectable Two phases => stuck @ faults detectable
Additional monitor for invalid transitions Additional monitor for invalid transitions
……
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Fault Tolerance : Fault Tolerance : RADIALRADIAL
OutcomeOutcome
Demonstrate, that FSL is able to tolerate multiple faultsDemonstrate, that FSL is able to tolerate multiple faults
Guarantee, that un-tolerated faults result in a deadlockGuarantee, that un-tolerated faults result in a deadlock
Challenges: Challenges:
Improve fault tolerance as far as possibleImprove fault tolerance as far as possible
Trade-off: Performance vs area overhead vs fault Trade-off: Performance vs area overhead vs fault
tolerancetolerance
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Research Concept Research Concept
FSL
Selfhealing FSL Circuits(PhD)
Fault Tolerance: RADIAL(Project)
Basic Gates Optimization(MA)
Design Flow Optimization(MA)
Reference Hardware(MA)
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Self-healing FSL CircuitsSelf-healing FSL Circuits
MotivationMotivation Increasing defect rate due to miniaturizationIncreasing defect rate due to miniaturization FSL drawbackFSL drawback
A single stuck at fault cause a deadlock A single stuck at fault cause a deadlock
Have to be “removed” in order to achieve high Have to be “removed” in order to achieve high reliable circuits reliable circuits
““Self-healing” is requiredSelf-healing” is required
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Selfhealing FSL CircuitsSelfhealing FSL Circuits
Task for self healingTask for self healing
1.1. Error detection Error detection
2.2. Error localizationError localization
3.3. Mitigate errorMitigate error
4.4. Recovery Recovery
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Detection and LocalizationDetection and Localization
Detection approachesDetection approaches Codes (Partity, CRC, …) Codes (Partity, CRC, …) Hardware redundancy (TMR, NMR, …) Hardware redundancy (TMR, NMR, …) Temporal redundancy Temporal redundancy
LocalizationLocalization Strongly related to the detection approachStrongly related to the detection approach Problem: granularity of the localizationProblem: granularity of the localization
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Detection and Localization Detection and Localization with with FSLFSL
Detection: (Permanent) fault causes a deadlock: Detection: (Permanent) fault causes a deadlock:
=> Can be recognized using a watchdog=> Can be recognized using a watchdog
Localization:Localization:
=> Can be done by identifying bubbles, when a deadlock => Can be done by identifying bubbles, when a deadlock occurredoccurred
Control Unit
LATCH
f(x) f(x)
LATCH
f(x) f(x)
LATCH
f(x) f(x)
LATCH
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MitigateMitigate
Options: Options: Rebuild the circuit: Rebuild the circuit:
Bitstream manipulationBitstream manipulation Runtime synthesisRuntime synthesis Pre-synthesized configurationsPre-synthesized configurations
Require FPGA based plattforms Require FPGA based plattforms
Self-healing cellsSelf-healing cells
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Self-healing CellsSelf-healing Cells
First approachFirst approach
AND
AND
MUX
Control
Problem: Also interconnects may be faultyProblem: Also interconnects may be faulty
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Self-healing CellsSelf-healing Cells Second approachSecond approach
AND
AND
ROUTER
Control
ROUTER
Control
Problem: Router must be fault tolerantProblem: Router must be fault tolerant
?
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RecoveryRecovery
1.1. Due to the deadlock no data will be overwrittenDue to the deadlock no data will be overwritten
2.2. Due to the deadlock no faulty data will be “stored” Due to the deadlock no faulty data will be “stored”
3.3. Each FSL gate preserves its internal state Each FSL gate preserves its internal state
After repair the circuit resumes the operation without After repair the circuit resumes the operation without
any additional recovery needed any additional recovery needed
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Self-healing FSL CircuitsSelf-healing FSL Circuits
Outcome Outcome
Generic approachGeneric approach
Ability to repair a large amount of faultsAbility to repair a large amount of faults
Self-healing procedure transparent for the application Self-healing procedure transparent for the application
Challenges:Challenges: Identify faulty componentIdentify faulty component Ensure losslessness Ensure losslessness Setup the watchdog timerSetup the watchdog timer
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Research Concept Research Concept
FSL
Temporal Behaviour: ARTS(Project)
Selfhealing FSL Circuits(PhD)
Fault Tolerance: RADIAL(Project)
Basic Gates Optimization(MA)
Design Flow Optimization(MA)
Reference Hardware(MA)
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Temporal Behaviour : Temporal Behaviour : ARTSARTS
Modelling of temporal behavior is required for: Modelling of temporal behavior is required for: WCET analysis WCET analysis Communicate with other componentsCommunicate with other components Trigger events at given points in timeTrigger events at given points in time
Synchronous design approachSynchronous design approach Clock provides an abstraction levelClock provides an abstraction level Clock provides a time baseClock provides a time base
Application
clock signal: well-defined & stable time base
all calculations are based on clock periods
jitter caused by hardware are masked
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Temporal Behaviour : Temporal Behaviour : ARTSARTS
Asynchronous designAsynchronous designEstablish a time base Establish a time base
Global circuit oscillationGlobal circuit oscillation Reduced speed and thus limited precision Reduced speed and thus limited precision
Self-Oscillating feedback loopSelf-Oscillating feedback loop Synchronisation with the remaining FSL circuitSynchronisation with the remaining FSL circuit
Modelling of execution timeModelling of execution time Environment (temperature, supply voltage, …) Environment (temperature, supply voltage, …) Processed data/operationProcessed data/operation Circuits implementation (MUX,e.g)Circuits implementation (MUX,e.g)
ApplicationApplication
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Temporal Behaviour : Temporal Behaviour : ARTSARTS
Outcome Outcome
Quantitative evaluation of jitter of FSL circuitsQuantitative evaluation of jitter of FSL circuits
Running FSL TTP/C ControllerRunning FSL TTP/C Controller
Challenges: Challenges:
Generation of a “stable” time baseGeneration of a “stable” time base
Parameterize the temporal behavior of FSL Parameterize the temporal behavior of FSL
at gate level at gate level
at circuit level at circuit level
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Conclusion FSLConclusion FSL
Current research topics:Current research topics: Design flow optimzationDesign flow optimzation Reference hardwareReference hardware Efficient basic gatesEfficient basic gates Fault tolerant circuitsFault tolerant circuits Self healing circuitsSelf healing circuits Modelling of temporal behaviour Modelling of temporal behaviour
Different research fields should provide one Different research fields should provide one comprehensive picture of FSL comprehensive picture of FSL
Funded master thesis available Funded master thesis available
For more details see: For more details see: trac.ecs.tuwien.ac.at trac.ecs.tuwien.ac.at
FSL
Temporal Behaviour: ARTSSelfhealing FSL Circuits
Fault Tolerance: RADIAL Basic Gates Optimization
Design Flow Optimization
Reference Hardware