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Politecnico di Torino - ICT School

Analog and Telecommunication Electronics

A3 – BJT Amplifiers

» Biasing

» Output dynamic range

» Small signal analysis

» Voltage gain

» Frequency response

AY 2015-16

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Lesson A3: BJT Amplifiers

• Biasing– Output dynamic range

• Small signal analysis– Voltage gain

– Frequency response

• Amplifier design– Set operating point and use of small signal model

– Lab experiment 1: small signal measurements

• References: – D. Del Corso: Transistor circuits, sect. 1.1, 1.2

– Any texbook on Transistor Amplifiers

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Amplifiers or ….

• What matters in an amplifier– Gain

– Bandwidth

– Linearity (no distorsion)

– Noise (low)

• There is always some nonlinearity

– Reduce, counteract» Negative feedback, tuned circuits, …

– Exploit to build» VGA/dynamic compressor

» Mixers

» Oscillators

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Transistor models

• Small signal– MOS, MOS-FET, BJT

– Same linear model (gm or hybrid)

• Large signal: same method, different models– BJT: exponential large signal model (rather simple)

– MOS: lin/log/quad large signal model (complex !)

– analytic model for BJT

– heuristic models for MOS

– Similar effects

– Similar countermeasures

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Building the BJT amplifier

• Basic bias circuit– Ic depends on current gain

– Wide changes in current gain

• Collector feedback bias– R1 to Vc

– Less dependent on current gain

• Emitter feedback bias– Ic depends on temperature (Vbe)

VAL

Vi

R1 Rc

C1

VAL

Vi

R1 Rc

Re

C1

VAL

Vi

R1Rc

C1

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Final BJT amplifier CE circuit

• Final bias circuit– Stable Ic

» Versus current gain(emitter feedback)

» Versus temperature(Vb >> Vbe)

– Gain related with bias

• Independent bias / gain– Different AC / DC paths

– Same approach for CC, CB

VAL

Vi

R1

R2

Rc

Re2

C1

VAL

Vi

R1

R2

Rc

Re2

C1

Re1

Ce

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BJT reference circuit

• Common Emitter circuit

– Bias (DC)

• Add – Gain control

with feedback

– Bandwidth (BW) control

» HF: C feedbackand to GND

» LF: coupling C

RE1

RE2

vO ZL

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Amplifier features and analysis

• AC amplifier: BJT Common Emitter circuit

• Input and output AC coupling: C1, C2

• Emitter feedback– DC: stabilize the bias point (Re1 + Re2)

– AC control the gain (Re1 only)

• Analysis or design:– Select or identify the configuration

– Set or evaluate the Bias point

– AC passband gain (linear model)

– Cutoff frequency (frequency response)

– Nonlinear model analysis next section

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Analysis of BJT circuit: step 1

• CE amplifier with bipolar transistor (BJT)– Find bias point:

(IC, VCE)

– The bias pointmust be in the active region:

VCE > 0,2 VVCE

IC

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Analysis of BJT circuit: step 2

• CE amplifier with bipolar transistor (BJT)– Find bias point:

(IC, VCE)

– The bias pointmust be in the active region:

VCE > 0,2 V

– Compute small signalparameteres for the bias point:

hie, hfe, gm...

hie, hfe

VCE

IC

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BJT (simplified) models

• Simplified model for bias point analysis (to verify operation in active area)

• Simplified model for small signal analysis, CE configuration.Parametershfe iB or gm vBE

hie = VT * hfe/IC

gm = IC/VT

B C

E

IB IB

gm vBE

vBE

B C

E

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Bias point analysis

• DC bias point– Small signal parameters depend on IC and (to a lesser extent)

on VCE solve bias point first

– IC IE is fixed by Base-Emitter mesh

– VCE is related with Collector-Emitter mesh

• Step 1: compute IC– Equation on BE mesh

– First approximation: IB = 0 (hFE )

• Step 2: check VCE value; – Equation on CE mesh

– if > 0,2 V active area

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BE net

• Ic depends fromthese devices

– Ic depends only from Base-Emitter mesh

– Vcc, R1, R2are mapped to a unique mesh, with equivalent Theveninparameters

VBB, RB

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BE mesh

• BE equivalent circuit(hFE = β)

VBB

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Vce

CE net

• Vce depends fromdevices in the CEmesh

– Vce depends from Ic and devices at the Collectornode

– Vce =Vcc-IcRc-IeRe

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Design choices

• If hfe is large, – IB = (VBB – VB)/RB

– VB = VE + VBE ≈ β IB RE + VBE

• Design variables (for a given Ic)– VBB, RB/VB

• Large VBB

– Good stability vs ΔVBE (mainly due to temperature)

– Reduced output dynamic range (lower VCEmax)

• Small RB

– Good stability vs Δβ (mainly due to parameters spreading)

– High power consumption (RB = R1//R2)

VE

VB

VBE

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R1 120 kR2 82 kRe1 330 Re2 12 kRc 10 k

Vcc 12 Vhfe 100 (50300)

Vbb = Rb =

Ie =Vce = hie = gm =

VccR1

R2

Rc

Re2

Re1

C1

C3

Ce

Q1I1

Ie

Example A3-e1: bias, small sig. param.

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R1 120 kR2 82 kRe1 330 Re2 12 kRc 10 k

Vcc 12 Vhfe 100

Vbb = 12 * 82 / 202 = 4,9 V Rb = 48,7 k

Ie = 4,3 / (12,33 + 48,7/100) = 0,335 mAVce = 4,35 V hie = 7,76 k gm = 12,88 mA/V

VccR1

R2

Rc

Re2

Re1

C1

C3

Ce

Q1I1

Ie

Results (example A3-e1)

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Lesson A3: BJT Amplifiers

• Transistor amplifiers– Basic CE circuit

– Biasing

– Output dynamic range

• Small signal analysis– Voltage gain

– Frequency response

• Design of amplifiers– Specifications

– Set operating point

– Use of small signal model

– Lab experiment 1: small signal measurements

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BJT circuit: small signal analysis

• Parts related with in-band gain:

– From slide A3-7: C3 open, C1, C2, Ce shorted)

• Reminder: – In signal analysis

Vcc = 0

– R1, R2 are connected as parallel resistances to Vi

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• Compute the gain using the linear model

vO = - iC ZC; iC = iB hfe; vi = iB hie + iB(1+hfe) ZE

vO

ZC

vIR1//R2

iB hfeiB

hie

ZE

Gain analysis equivalent circuit

vI

iC

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Results with linear model

• Gain with linear model

• If hfe >> 1 – hie becomes negligible

with respect to ZE (hfe+1)

• If Ze = 0 Max gain

– Av = - (Zc hfe)/hie = VT hfe/IC

– Depends on device parameters (hfe)

(hfe+1)

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hie = 8,96khfe = 100gm = 12,9 mA/V

Rc 10 kRe1 330 RL 12 k

Total load on the Collector: Rc//RL

Av =

Vo

RL

ViR1//R2

Vbe

Rc

Re1

gm Vbe

hie

Example A3-e2 : gain with linear model

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hie = 8,96khfe = 100gm = 12,9 mA/V

Rc 10 kRe1 330 RL 12 k

Total load on the Collector: Rc//RL

Av = - (12k//10k)*100 / (8,96k + 330*100) = -13

- Evaluate gain change for hfe 50500- Compare with Re = 0

Vo

RL

ViR1//R2

Ib

Rc

Re1

hfe Ib

hie

Results (example A3-e2)

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hie = 8,96khfe = 100gm = 12,9 mA/V

Rc 12 kRe1 330 RL 10 k

Ri = ?

Ro = ?

Vo

RL

ViR1//R2

Ib

Rc

Re1

hfe Ib

hie

Example A3-e3: Ri and Ro

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Frequency response

• Wideband AC amplifier– Emitter/source feedback

» stabilize DC bias point and in-band AC gain |AV| ZC/ZE

• Lower band limit:– interstage series coupling capacitance

– ZE frequency behaviour

– transformer coupling (if any)

• Higher band limit– parallel capacitors towards ground

» designed capacitors

» wiring parasitic

» active device parasitic

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Wideband AC amplifier

f(Hz)

|Vu/Vi| (dB)

Low cutofffrequency(C1, C2, Ce)

High cutofffrequency(C3, Cp1, Cp2)

Band pass

1 10 100

Minimum required (specs)

Actual (tolerances)

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High Frequency: L and C parasitics

• Output Capacitance (load)– insert isolation stage (Common Collector/Drain)

• PCB parasitic L and C– Use SMD devices

– Careful PCB design

• Active device parasitic (CBC) – multiplied by Miller effect

– use HF devices with low CBC (GaAs, SiGe, ..)

– proper circuit configuration (Common Base, cascode)

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Cp1: Base-Collector parasitic (Cbc)C3: designed to set high cutoff frequency

Vcc

Vi

R1

R2

Rc

Re2

Re1

C1

C3

C2

Q1

Vo

RL

C4

Ie

Cp1 Cp2

Parasitic capacitances

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Miller effect

• Parasitic Base-Collector capacitance (CBC) is connected between two nodes with inverting gain –A

– Corrent Icond flowing in CBC:

– Icond = jωCBC (VB–VC) = jωCBC (VB+AVB) = jωCBC (A+1) VB

(multiplied by Miller effect)

– Admittance multiplied by (gain +1)

• Actual equivalent capacitance at Base node:– Cactual = CBC * (A+1)

• This capacitance limits the high frequency response

• Need for Miller free circuit configurations

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Other circuit configurations: CC

• Common Collector / Common Drain– high Zi

– low Zo

– No Miller effect (Av ≈ 1)

– Current gain

• Good for– Load separation

– Increasing Zi

– Lowering Zo

• Av ≈ 1

Vcc

ViRe Vo

Q1

Va

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Other circuit configurations: CB

• Common Base / Common Gate– low Zi,

– high Zo

– CBC connected to GND

no Miller effect

• Voltage gain– Av ≈ gm Rc

• Current gain Ai ≈ 1

• Combined with CEin the cascode stage

Vcc

Vi

Rc

Vo

Q2

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Cascode amplifier

Only basic circuit, no bias network

Vi VaQ1: CE stage, Low Zc low V gainGood current gain- Low ΔVce- Low Miller effect

Va VuQ2: CB stageGood voltage gain- No Miller effect

Vcc

Vi

Rc

Q2

VoRL

Q1

Va

Common Base: Ie VoVoltage gain

Common Emitter: Vi IcCurrent gain

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Cascode amplifier

• Common Base stage (CB)– CBC parasitic towards ground

– no Miller effect (C multiplier)

– provides voltage gain

• Common Emitter output to low-Z load– small voltage dynamic

– provides current gain

– minimum effect of CBC parasitic capacitance

• Overall result– higher gain at high frequency

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Lesson A3: BJT Amplifiers

• Transistor amplifiers– Basic CE circuit

– Biasing

– Output dynamic range

• Small signal analysis– Voltage gain

– Frequency response

• Design of amplifiers– Specifications

– Set operating point

– Use of small signal model

– Lab experiment 1: small signal measurements

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Lab 1 and lab 2

• Design an amplifier from the provided specs– A real design:

» Multiple solutions

» Some specs are implicit

» Devices have poorly defined parameters

• Simulate, build, measure– Homework: design, simulation

– In the lab: build, measure, debug

• Compare specs/simulation/measurements– Linear model lab 1

– Nonlinear model lab 2

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Amplifier design specs (2016)

• Single-Transistor Amplifier with:– Voltage gain |Vu/Vi| = 20 (nominal)

– Bandwidth -3 dB from 80 Hz to 200 kHz (minimum)

– Output dynamic at least 4 Vpp on 10 kΩ load (or higher)

– Supply voltage 12 V (nominal)

– 2N2222A Transistor (or almost equivalent)

• All features within +/-10%, at ambient temperature – Gain and output dynamic at band centre

• References:– Text: design procedure: Cap 1, 1.P1

– Lab procedures: Cap 1, 1.L1

– web guides: lab 1

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Design sequence

• Select the circuit: CE with Ze, bias network Vb/Re

• Choose a no-load dynamic (Vo), or Ve, or Rc– Stability/power/dynamic tradeoffs

• Compute Rc, or no-load dynamic , or Ve

• Compute Ic

• Design bias network to get Ic:– R1, R2, Re1+Re2

• Compute Re1 from gain specs

• Compute C1, C2, C3, C4 from frequency gain specs.

• Evaluate Pdmax (always, even if not requested!)

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Checks and measurements

• Passive devices (R and C) available only in normalized values

– Know what they are (E12, E24, …)

– Only E12 values available in the lab

– From computed to normalized values

• Transfer function modified by normalization / tolerances– Evaluate effects

• Component tolerances expand the Bode plot (a line) to a somewhat wide band

– Specs must lie within the strip

• Compare measurements with variations of Bode plot

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Theory and practice

f(Hz)

|Vu/Vi| (dB)

1 10 100 1k

Design specification

Design band, takinginto account deviceparameters tolerances

Measured values(with errors)

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Lesson A3: final questions

• Which different types of amplifiers can be found in a radio system?

• Draw three circuits which can be used to set the operating point of a BJT, discussing respective benefits and drawbacks.

• Write an approximate expression for Av of a CE amplifier.

• Which elements limit the bandwidth of amplifiers?

• Which are the best configurations for high bandwidth amplifiers?

• List the specifications for an amplifier (what you must know to select an amplifier from a catalogue).

• Outline the design procedure for a single transistor amplifier.

• Describe the lab procedures to measure the frequency response ofan amplifier.