Common Emitter BJT Amplifier Design Current Mirror Designese319/Lecture_Notes/Lec_8_CEDesig… · Q amp Q amp ac circuit overall circuit with bias. ESE319 Introduction to Microelectronics

ESE319 Introduction to Microelectronics

1Kenneth R. Laker, update 15Oct13 KRL

Common Emitter BJT Amplifier DesignCurrent Mirror Design



Design Example



Design Step 1 (Set RB and R

E)

Choose an RB >> 10RS:

RB=5000

must be ≥ 10RB:

≈100

RE=10⋅5000100

=500

Nearest standard size*: 470 Ω

RE=470

1RE

*RCA Lab: http://www.ese.upenn.edu/rca/components/passive/listcomponents.html#resistors

vs

vO

http://www.ese.upenn.edu/rca/components/passive/listcomponents.html#resistors



Design Step 2 (Set RC)

=100

RE=470

RB=R1∥R2=5 k

For a gain of Av = -10:

RC=10RE=4.7 k

470

Nearest standard size*:

RC=4.7k

SPEC: v s−max=0.1V pkvs

vO

For a gain of -10, the max ac collector voltage v

o-max swing is 1 V pk; hence,

the dc VRC

> 1 V.



Design Step 3 (Set bias point neglecting IB)

=100

RE=470

RB=5k

RC=4.7k

V RC=4.7V≈

V CC

3Thus:

I C=4.7 /4700=1mA.

And (ignoring IB):

V B=V BG≈ I C RE0.7=0.470.7=1.17V

470

4.7 k

vs

vO

Recall vsig-max

= 0.1 V pk and |Av| = 10

We have plenty of room - choose the dc collector-resistor voltage conservatively to allow for bias point changes with temperature – let's use:



Design Step 4 (Set R1 and R

2)

=100

RE=470

RB=5k

RC=4.7k

Recall:

RB=R1∥R2=R1

R2

R1R2=5 k

And:V B=

R2

R1R2V CC=1.17V

Or:R2

R1R2=

V B

V CC=1.1712

=0.098≈0.1

470

4.7 k

vs

vO



Design Step 4 cont. (Set R1 and R

2)

R1∥R2=R1

R2

R1R2=R1⋅0.1=5k

Substituting:

R1=50 k

Standard size: R1=47k R2

47 kR2=0.1Finally:

0.9 R2=0.147k⇒R2=5222Standard size: R2=5.1 k

470

4.7 k

Revised RB:

RB=R1∥R2=47 k 5.1 k52.1 k

=4.6 k

=100

RE=470

RB=4.6 k

RC=4.7k

NOTE: 1RE≈47k ≥ 10RB=46k

vs

vo



Design Step 5 (set Cin

) - Close to the Finish!

Estimate Rin:

RB∣∣rbg≈4.2 k

RB in parallel with rbg => RB dominates. Estimate as 4.2 k . Coupling capacitor reactance, then, should be about 420 Ω at f = fmin.

rbg=r1RE≈47.5 k

∣ 1j 2 f min C in∣=420

C in=1

420⋅220=1.19 ˙10−4

2≈19F

470

4.7 k47 k

5.1 k

Using the RCA Lab Component List

C in=10

2 f min420

Cin = 22 µF

I C=1mA=100r=2.5k

vs

voC in

RB∣∣rbg



Final Design

4.7 k

470

47 k

5.1 k

22 µF

vs

voCin



Multisim Simulation

20 Hz Gain

1 Khz Gain Actual |AV (f = 1 kHz)| = 9.3 < 10

Actual |AV (f = 20.7 Hz)| = 9.27 9.3.≈.



Multisim Oscilloscope Plots

vs

vo



Discussion1. We neglected re. Including the internal emitter resistance, the simulated gain becomes:

AV=−RC

REr e=− 4700

47025=−9.5

2. There is some attenuation of the signal voltage at the base. A more accurate calculation of the input attenuation:

vbg≈RB∥rbg

RB∥r rgRS= 42004250

v sig=0.988 vsigRB∥rbg=4.2 k ⇒

Multiplying the two quantities: Av=−9.5⋅0.988=−9.4

This fine-tuning of the estimate may not be all that helpful – since we will be using 5% components to build the circuit!

Close to 9.3!



Common Emitter Amplifier - Current Source Biasing

VCC

IE

RC

ro

RE

RB

Rs

vs

C1

CE

1. If NO RE & C

E, what is the ap-

prox. mid-band voltage gain?

2. If RE & C

E, what is the approx.

mid-band voltage gain?

3. What is the purpose of C1?

vo

Qamp




VCC

IE

RC

ro

RE

RB

Rs

vs

C1

CE

1. If NO RE & C

E, what is the ap-

prox. mid-band voltage gain?

2. If RE & C

E, what is the approx.

mid-band voltage gain?

3. What is the purpose of C1?

vo vo

v s=−RC

r o≪1

vo

vs=−RC

RE

No important purpose.

Qamp



vsig

RC

V CC

V EE

iE

vO

Q1

Q2

Qamp

iC

Rs

v s

RB

iBV BRref


Rref

Rs

vs

I REF=V CC−V BE Qref

Rref

IREF

I REF

I REF=V CCV EE−V BE Qref

Rref

VBE(Qref)VBE(Qref)

vO




vsig

RC

Rref V CC

V EE

iE

vO

Q1

Q2

Qamp

iC

RS

v s

RB

iBV B

I E /1

1. The current mirror sets IE (IC).

2. RB serves the purpose to provide a high impedance looking into the base and IB = and V

B = - I

B R

B.

3. VB = 0.7V + V

E sets the emitter-to-

ground voltage VE and, hence, sets V

CE

for a given IC.

4. vs is the signal source.



Bias Setting1. Since RB does not interfere with the bias, the signal source can “usually” be connected to the base without need for a blocking capacitor.

2. Choose RB “ large” compared to RS to avoid attenuating vs. But not too large!

3. Choose Rref to set IE.

RsRref

v s

RS

RB

RC

V CC

iE

vO

iC

Q1

Q2

Qamp

V EE



Bias Setting - Continued

I REF=V CCV EE−0.7

Rref

Choose:I C≈ I E≈ I REF=1mA

Rref =23.310−3

=23.3 k

Choose standard size:(RCA Lab Comp List)

Rref =22 k

V CC=I REF Rref V BE Qref −V EEIREF

+-

VBE(Qref

)

22 k OhmRref

RC

RB

For dc bias set vs = 0

Q1

Q2

Qamp



Bias Setting - CompletedWith the base through RB:

This implies that there is about an12.7 V drop to split across RC & VCE. Let's choose V

RC = 5.6 V & V

CE = 7.1V.

RC=V RC

I C=5.610−3

=5.6 k

Choose standard size:(RCA Lab Comp List)

RC=5.6 k

5.6 k Ohm

I B≈0

Neglect the base current through R

B

I b≈0

V CC=V RCV CE QampV E

Rref

RB

RC

V E=V EB Qamp≈−0.7V

V E



Gain Setting1. Connect the source to the base.

2. Provide a path for the smallsignal emitter current.

3. Choose RE for the desired gain(Av = - RC/RE).

4. CE is nearly a short circuit for f ≥ f

min

Calculate CE s.t. at f ≥ f

min.

RS≪RB

5.6 k Ohm

v s

RS

RrefRC

RE

C E

RB

vo

∣ 1j 2 f C E∣≪RE

Q1 Q

2

Qamp



Gain Setting - Continued

Choose the nearest standardsize resistors for RC and RE.

RE=RC

20=560020

≈270

Gain check:ib=

v s

RS1reRE

vo=−RC ic=−RC ib

∣Av∣=∣vo

v s∣≈ 1

RC

reRE≈5600295

=19

5.6 k OhmRs

ib

ie

Design for |AV| = 20:

270

Typical18 ≤ |AV| ≥ 22RS RC

RE

reie

ib

v s

vo

or 25.57 dB



RE and C

E

∣ 1j 2 f C E∣≪RE⇒

12 f min C E

=RE

10⇒C E=

102 f min RE

≈300F @ fmin

= 20 Hz

CE = 300 µF too large; too conservative!

Re

Ce

RE

C E

RE

C Eie

vO vo

v s v s

Q1 Q

2

Qamp Q

amp

ac circuitoverall circuit with bias



Complete the Design

If we choose next largest standard size (RCA Lab Comp List):

C E=33F => flow

= 12.5 Hz

CE = 300 µF too large!!

Less Conservative Design:

for flow

= 20 HzC E=1

2 f low RE≈30F

∣ 1j 2 f C E∣≪RE⇒

12 f min C E

=RE

10⇒C E=

102 f min RE

≈300F @ fmin

= 20 Hz

C E=1

2 f low REwhere f low≈ f low−3dB



Multisim Bode Plots

20 Hz Gain

1 kHz Gain

CE = 33 µF

Actual |AV (f = 1 kHz)| = 25.52 dB (18.88)

Spec.18 ≤ |AV| ≥ 22

Actual |AV (f = 20.5 Hz)| = 22.63 dB



ib

RB

ic

ib

dc

small ac @ midband

roDue to C

E

What if RE = 0 Ω ?

A¿

Av=vo

v s≈−RC

r e



What About Interface to the Output Load (RL)?

RL

Is the above interface to RL OK?



What About Interface to the Output Load (RL)?

RL

Is the above interface to RL OK? - No

1. Need CL to block dc bias on v

C, i.e. v

o is small signal only.

2. For ac (f ≥ fmin

)

C L

vov

C

RL' =RC∥RL Unless R

L >> R

C, R

L alters A

v.



Multi-Stage Amplifier

vO1

vo1

vo2C

in1

Cin2

Rin2

>>RC1

Stage 1 Stage 2

Av=vo1

vs

vo2

vo1=

vo2

v s=−

RC1

RE−

RC2

RE

RC1

RC2

RL >>R

C2

Documents

Common Emitter BJT Amplifier Design Current Mirror Designese319/Lecture_Notes/Lec_8_CEDesig… · Q amp Q amp ac circuit overall circuit with bias. ESE319 Introduction to Microelectronics