© 2003 Xilinx, Inc. All Rights Reserved Controlling the System

© 2003 Xilinx, Inc. All Rights Reserved

Controlling the System

Controlling the System - 6 - 2 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

After completing this module, you will be able to:

Objectives

• Describe the control mechanism available in System Generator• State the available blocks in System Generator to control data

movement• Describe how to design state machines• Distinguish between valid and invalid data


Outline

• Control Mechanisms– Clock Enables and Reset– Valid and Invalid Data

• Control Blocks– MicroBlaze (FSL)– M-Code Block– Expression Block– PicoBlaze– PowerPC/MicroBlaze (App Note)

• Simulink Tips and Tricks– Masked Subsystems– Icon Editor– Parameter Initialization– Documentation Editor


Control MechanismsEnable and Reset Ports

• Many blocks have optional Enable ports– Gated by the CE signal going to the block– When the CE signal is de-asserted the block holds its current state until

the enable signal is asserted again or the reset signal is asserted– The enable signal has to run at a multiple of the block's sample rate– The signal driving the enable port must be Boolean

• Some blocks have an optional Reset port– Gated by the CE signal going to the block– Reset port has precedence over Enable port when both are present– When the reset signal is asserted the block goes back to its initial state– The reset signal has to run at a multiple of the block's sample rate– The signal driving the reset port must be Boolean


Control Mechanisms Clock Enable Port

• SysGen infers the clock from the design sample times, and abstracts away the Clock Enables

• In multi-rate systems further Clock Enables are inferred due to the more complex hardware elaboration scheme. This is covered in next module

• This clock enables are ANDed with optional enable ports, which users can turned-ON from the block parameters


System Clock

CE

DIN

DOUT 5 0 11 8 0

7 2 1 4 7 8 3 0 3 111 6 20

Clock Enable Behavior

• CE is modeled to reflect the hardware behavior– Output changes one clock cycle after CE is asserted


Control Pin Cheat SheetBasic Elements Enable Pin Reset Pin Control Logic

Addressable Shift Register Y N None

Black Box ?? ?? ??

Concat N N None

Constant N N None

Convert N N None

Counter Y Y Load

Delay Y N None

Down Sample Y N None

Enable Y N None

Inverter Y N None

LFSR Y N None

Logical Y N None

Mux (Latency > 0) Y N None

Parallel to Serial Y N None

Relational Y N None

Register Y Y None

Reinterpret N N None

Serial to Parallel Y N None

Slice N N None

Sync N N None

Up Sample N N None

Math Enable Pin Reset Pin Control Logic

Accumulator Y Y None

AddSub (Latency > 0) Y N None

CMult (Latency > 0) Y N None

Expression (Latency > 0) Y N None

Logical (Latency > 0) Y N None

MCode N N None

Mult (Latency > 0) Y N None

Negate (Latency > 0) Y N None

Scale N N None

Shift (Latency > 0) Y N None

SineCosine Y N None

Threshold (Latency > 0) Y N None

Memory Enable Pin Reset Pin Control Logic

Dual Port RAM N N We_A, we_B, Vout

FIFO Y Y we, re

ROM Y N None

Single Port RAM Y N we

?? – Depending on application corresponding pin(s) may exist


Control Pin Cheat Sheet

Communication Enable Pin Reset Pin Control Logic

Convolution Encoder Y Y Vin, Vout

Depuncture N N None

Interleaver/Deinterlever Y Y Vin, Vout

Puncture N N None

RS Decoder N Y Start, Erase, Vin, Vout

RS Encoder N Y Start, Bypass, Vin, Vout

Viterbi Decoder Y Y Vin, Vout

DSP Enable Pin Reset Pin Control Logic

CIC N N Vin, Vout

DDS Y Y None

FDATool N N None

FFT N Y Inverse, Vin, Vout

FIR N N Vin, Vout


Control Mechanism Valid and Invalid Ports

• Issue: How to model ‘invalid data’ in the confines of a System Level environment. Required for data burst applications, one-shot FFTs, and latency output from high level cores

• Solution: Certain blocks have a ‘valid bit’ input (vin) that is a control signal to the data input. It is also accompanied by a valid out (vout) signal that signals whether the output data is valid

• Most high level blocks have ‘valid’ input and output ports


Valid Bits

• There are several conditions that result in a Xilinx block producing indeterminate data, which is represented as ‘not a number’ or NaN in Simulink

– One case is with the Dual-Port Memory block, when there is a write-write collision on a particular address. Consequently, in Simulink simulation, the corresponding data is marked as indeterminate

– A block having vin and vout ports may produce indeterminate values, for example to model pipeline flushing at the beginning of a simulation, but will have accompanying vout set to 0

– Special attention should be paid if you encounter indeterminate data in a model, because it indicates unobservable behavior in the ultimate hardware

– System Generator will catch some instances of indeterminate data as simulation errors in Simulink, when this represents a semantic problem with your model

– Be aware that although these design errors will be caught in Simulink simulation, such cases will not be detected in hardware


Valid Bits

• Blocks that have Valid bit modeling:– FIR (optional)– FFT– Reed Solomon Encoder/Decoder– Viterbi Decoder– Convolutional Encoder– Interleaver/DeInterleaver– CIC


Valid Bits Question

• Cost in hardware– The SysGen block typically has a ‘valid bit’ pipe parallel to the data path. The

length of the pipe is equal to the latency of the block– An AND gate controls the data path input

What would be the most efficient way of implementing the valid pipe?


Outline





Modeling Control Circuits

• System Generator provides many ways to model Control Circuits– Develop DSP peripherals for MicroBlaze (via FSL)– M-Code block for subset of MATLAB m-code compilation

• Gives designer more design language choice

– Expression block for bit-wise logical operations• Provides simple level control using Logical and Boolean expressions

– Xilinx PicoBlaze 8-bit soft microprocessor block• Allows designers to model more complex control functions

– Develop DSP Peripherals for 32-bit PowerPC/MicroBlaze (app note)


Xilinx Processor Family

Hard IP

Soft IP

Reference Design in VHDL(Custom Bus)

32

-bit

8-b

it

C & Assembly

Assembly& µCode

Embedded Development

Kit - EDK

Assembler

µP Core Coding Environment Target FamiliesInstEmbedded Processor

PLB

OPB

Bus


SysGen-EDK Connection


New MicroBlaze Block

• Found in Index and Control Logic Library• Exposes FSL interfaces to System Generator blocks in Simulink• A maximum of 8 input FSLs and 8 output FSLs• Reset port to allow processor

controlled reset• Simple hardware design idiom:

FSLs look like FIFOs• No simulation model


EDK Export Tool• EDK compilation target• Exports a System Generator design with a

MicroBlaze Block • Creates necessary EDK files: mpd, pao, bbd • Marshals required files into a directory

structure understood by the EDK


Accessing FSLs in software• Blocking and non-blocking reads and writes

(8 macros) e.g.– Blocking data and control reads

microblaze_bread_datafsl(val,id);

microblaze_bread_cntlfsl(val,id);

– Non-Blocking data and control writesmicroblaze_nbwrite_datafsl(val,id);

microblaze_nbwrite_cntlfsl(val,id);

• Error conditions visible in the MicroBlaze status register, MSR register– MSR[27] = FSL error (mismatch in data/value pair)– MSR[29] = data invalid (0 if read or write succeeds)


Expression Block

• Performs a bitwise logical expression• The expression is specified with operators

– And - & -- highest precedence– Or - |– Not - ~– Xor - ^ -- lowest precedence– Precedence can be changed using parenthesis

• The number of input ports is inferred from the expression – Maximum of 16 possible input ports

• The input port labels are identified from the expression, and the block is subsequently labeled accordingly

– Block Parameters• Expression : Bitwise logical expression • Align Binary Point : specifies that the block must align binary points automatically. If

not selected, all inputs must have the same binary point position


Expression Block

• Entering following expression in the block parameters Expression field will generate the resulting symbol– ~((A1 | A2) & (B1 ^ B2))


8-bit PicoBlaze Controllerwithin Simulink

For more information on the Picoblaze microprocessor, visit:http://www.xilinx.com/ipcenter/processor_central/picoblaze/index.htm

• PicoBlaze provides8-bit microprocessortype control

• Xilinx’s Home-Grown 8-bit processor

– Very compact (85 slices)– 49 instructions– Assembly language– 2 clocks/instruction– 10,000+ users


Use System Generator to Develop DSP Peripherals for OPB

OPB

Reloadable DA FIR

Peripheral

UART Lite

PowerPC/MicroBlaz

e

Host PC

(post-processing and filter design in

Matlab)

Application Note XAPP264Using SysGen to Create CoreConnectTM Peripherals

• XAPP264 shows designers how to use Simulink & System Generator to create DSP peripherals that can connect to the OPB– PowerPC – MicroBlaze

• This enables 32-bit control for XtremeDSP using:– VirtexTM-II, Virtex-II ProTM

– Spartan-3• Still need EDK to program the

processor


Quick System Resource Estimation from Simulink

• Designers can now estimate how many FPGA resources will be used directly from Simulink– Can be invoked at

any level in the system hierarchy

• No need for:– System Generation– Synthesis– Implementation


Outline





Masked Subsystems

• Simulink provides the power to “personalize” a subsystem. This is called masking

• This enables you to:– Generate custom macro blocks with a custom icon– Create a parameter dialog box for the block– Create your help for the block– Shield complexity of the internals of the block– Protect the contents of a block from ‘dirty hands’


Masking a Subsystem

• Right click on a subsystem and select “Mask Subsystem” (Ctrl+M)

• The Mask editor contains the:– Icon editor– Parameters editor– Initialization editor– Documentation editor

• To disable a mask simply click unmask on the mask editor


Icon Editor

• The Icon tab controls the appearance of the icon

• The drawing commands edit box allows the use of MATLAB syntax plotting and image commands to define your icon. Try:

• plot(peaks)• disp(‘my Icon’)• image(imread(‘xilinx.jpg’))

• Play with the other properties to view their effects


Parameters Editor

• The Parameters tab enables you to define and describe mask dialog box parameter prompts and name the variables associated with the parameters

• Users must:– Add a parameter– Give a prompt name– Assign a variable name to pass the

value to– Select the type of variable– Select if enabled or not– Select if tunable or not


Initialization Editor

• Initialization tab allows you to specify initialization command

• After this, MATLAB workspace variables are no longer visible

• Simulink executes the initialization commands when it – Loads the model – Starts the simulation– Updates the block diagram – Rotates the masked block – Redraws the block's icon (if the mask's

icon creation code depends on variables defined in the initialization code)


Documentation Editor

• There are three fields:– Mask type– Mask description– Mask Help (can be written in html). Click Help in the block mask to access the block help

Type ‘maskedsubsytem’ to view the example


Lab 7:Controlling the System

• In this lab, you are to create an address generator to control the storage of samples and coefficients for a 92 tap MAC-based FIR filter, using

– Xilinx Blockset’s predefined blocks– Xilinx Blockset’s MCode block

• Below is a block diagram of the MAC-based FIR filter

Samples 92 × 8

Coefficients92 × 12

Samplein

Sample Address

Coefficient Address

D Q CE

+

+ D Q

Capture of final result

8

12

20 27 27

AccumulatorFull Multiplier Sample Memory • Cyclic RAM buffer


Your task is to generate the logic that will drive each address port of the Dual Port Block Memory

y(0) = h(0) x(0)y(1) = h(1) x(0) + h(0) x(1)y(2) = h(2) x(0) + h(1) x(1) + h(0) x(2)y(3) = h(3) x(0) + h(2) x(1) + h(1) x(2) + h(0) x(3)etc.


• One way to implement this filter is to store the filter coefficients and samples in a dual port block RAM used as a cyclic RAM buffer– The dual port RAM will be used in a mixed mode configuration with the data

written and read from port A (RAM mode) and the coefficients read from port B (ROM mode)

yn = xn-i hii=0

N-1


The idea is as follows:


x(91) x(90) ... ...

Read address

Write address

Fast rate

Slow rate

h(0) h(1) h(2) ... ... h(89) h(90) h(91)

Read address Fast rate

Read Address sequence: 92 93 94 95 … 183

Data buffer

Coefficient array

start

start

x(0) x(1)

Stall one clock cycleat this address

x(3) x(2)


ADDR_A

0

N-1

N

2N-1

ROM

WE_B

DIN_A

A

B

ADDR_B

CYCLICCOUNTER

CYCLICCOUNTER

LOGIC

ADDR_B 92 93 94 95 … 183 92 93 94 95 96 …183 92 93 94 95 96 97

ADDR_A 0 1 2 3 …91 91 0 1 2 3 …90 90 91 0 1 2 3

DIN D1 X X X …X D2 X X X X … X D3 X X X X X

WE WE

WE_B

DIN_B

0 – N-1

N – 2N-1

WE

RAM MUST BE:READ AFTER WRITE

CE

Documents

© 2003 Xilinx, Inc. All Rights Reserved Controlling the System