© 2003 Xilinx, Inc. All Rights Reserved

Answers

DSP Design Flow

Answers - 10 - 2 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Lab 1: Wrap up

• Implementation results (including Chipscope Blocks): 304 Slices, ~112 MHz

• Important to notice:– Global clock buffer is automatically instantiated– Embedded multiplier is used by default in Virtex™-IIP devices. In this lab,

the option was turned off in order to use slice-based multipliers• Timing constraint should always be used to achieve the performance

required– XCF file must be generated manually

• Remember size to compare with the other flows

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Module 2: Answers

• Define the format of the following twos complement binary fraction and calculate the value it represents

• What format should be used to represent a signal that has:

• Fill in the table:

Using the technique shown, convert the following fractional values…

1 1 0 0 0 1 1 0 1 0 1 1Format = < Fix_12_5 >

Value = -917 = -28.65625 32

Format = < FIX _12_10 > Format = <UFIX_10_10> Format = < FIX _11_1>

Operation Full Precision Output Type <Fix_12_9> + <Fix_8_3> <Fix_15_9> <Fix_8_7> x <Ufix_8_6> <Fix_16_13>

a) Max value: +1 Min value: -1 Quantized to 12 bit data

b) Max value: 0.8 Min value: 0.2 Quantized to 10 bit data

c) Max value: 278 Min value: -138 Quantized to 11 bit data

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Lab 2: Solution

MAC using embedded multiplierSlice Count: 24 Slices, 1 embedded multiplier

Performance: ~244 MHz(2vp4 -7)

MAC using slice-based multiplierSlice Count: 69 Slices Performance: ~182 MHz(2vp4 -7)

Multiplier Latency - 2

Answers - 10 - 5 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Module 3: Answers

• How many clock cycles per input are required for a fully parallel 12-bit data, 20 tap symmetric filter?– Hardware over-sampling rate = 1

• The requirement for a filter is to run at 25 MSPS. A 100 MHz system clock is available on the board. What should the hardware over-sampling rate parameter be set to for 8-bit data?– Hardware over-sampling rate = 100/25 = 4

• How many clock cycles per input are necessary to process in serial an 11-bit data, 31 tap symmetric filter?– Hardware over-sampling rate = 11 + 1 = 12

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Lab 3: Solution

• 365 slices• Clock rate: 229 MHz • Sample rate: 229/9 = 25.4 MSPS

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Lab 4: Solution

RTL View for Rounding RTL View for Saturation and Rounding

Answers - 10 - 8 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

0 1 0 0 0 0 0 0

0 0 0 1 0

0 1 0 0 0 0 0 0

0 1 0

Module 4: What Values Do You Expect?

Signed DataTruncate and Wrap

Signed Data Output Binary point of 3

Total Number of Bits 3 Bottom of Slice offset by 5

from the LSB

Number Input

Convert

Reinterpret

Slice

Answers - 10 - 9 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Lab 5: Blocks-Based Solution

• Post-Map Resource Estimates– Slices – 15– FFs – 16– LUTs – 28

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Control Logic Waveform

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Lab 5: MCode-Based Solution

• Post-Map Resource Estimates– Slices – 16– FFs – 16– LUTs – 28

function done = term_cnt(count)if count == 183 done = true;else done = false;end

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44.1 kHz 48 kHz441 kHz

CDformat

DATformat

7056 kHz

SamplePeriod (GCD)

SamplePeriod

Gateway InBlock antiAliasFIR antiAliasFIR1 Gateway Out

Simulink System Sample Period:

Module 6 Exercise: Audio Application

• Analyze the following sampling rate change system that is commonly found in audio broadcasting studios. Determine the Simulink System Sample period:

1/44100 1/441000 1/7056000 1/48000

160/7056000 16/7056000 1/7056000 147/7056000

1/7056000

Answers - 10 - 13 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

CE

D Q

CE2

D

CE3

Q

CE

X y

CE

CK

CE

CE2

CE3

System CLK

System CE

Sample RateControl Logic

Answer: Audio Application

2 1 3

CE2 CE3

DATformat

DABformat

32 kHz96 kHz

48 kHz

Normalized Sample Times:

Answers - 10 - 14 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Answer: Audio Application

Block Output Sample Frequency

Normalized Sample Time

InReg 48 kHz 2

Up Sampler 96 kHz 2 and 1

AntiAliasFIR 96 kHz 1

Down Sampler 32 kHz 1 and 3

OutReg 32 kHz 3

Answers - 10 - 15 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Q. What would happen if a full precision adder is used in this example?

An error will occur as an infinite loop will be created

Module 6: Propagation in Loops

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Lab 6: Solution

Slice Count:(with MULT18x18)89 slicesPerformance~204 MHz

Slice Count:(Slice-based MULT)126 slicesPerformance~ 208 MHz