Xilinx Academy 4/98 1 Xilinx Software Solutions Xilinx Academy November, 1998

Xilinx Academy 4/98 1

Xilinx Software Solutions

Xilinx AcademyNovember, 1998



Alliance Series Configurations

$95*

* Promotional Pricing is Valid until Version 1.5 Ships in Q3 1998.


Xilinx Alliance Series

http://www.xilinx.com/products/alliance.htm

Powerful High Density Solutions

Integrated into Your EDA Environment


Alliance Series Flows

EDIF, VHDL, Verilog, SDF

HDLSchematic

Existing Designs Cores

StandardsBased

Includes Libraries and Interfaces for all 4 Tier One Alliance Partners

Enables multiple sources and multiple EDA vendors in the same flow

Design the way you are used to


The Value of PartnershipsThe most comprehensive “Open System”

solution Early software support for new devices New product development maximizing

architectural and synthesis capabilities§ Efficient timing constraints integration§ High performance optimization engines tuned

for new Xilinx devices§ Direct optimization & mapping of Carry logic,

complex I/O, LUTs, CE, arithmetic operator

Joint definition of next-generationdesign flows and technology


Premier EDA Partnerships Leader in HDL Design Solutions for

ASICs

Leading software design solutions for system designs

Leading CAE framework and industry standard Verilog simulator

Leading FPGA PC schematic capture design solutions

Over 50+ EDA Partnerships


Higher Densities & PerformanceRequires Powerful Software

1995 1997 1998 1999

Year

XC4000ELargest DeviceXC4025E0.5m5 Volt

XC4000EXLargest DeviceXC4036EX0.5m5 Volt 30% faster than E

XC4000XLLargest Device180,000 sys. gates0.35m3.3 Volt30% faster than EX

XC4000XVLargest Device500,000 sys. gates0.25m2.5 Volt30% Faster than XL

1996

Virtex1M+ Systems GatesSystem Solution0.25/0.18µ2.5/1.8 Volt

Den

sity

/Per

form

ance

1 Million Gatesin 1998


The Alliance Series Advantage

Only Xilinx delivers these essential capabilities

Powerful timing-driven technology & graphical Constraints Editor

Highest performance with industries leading synthesis vendors

Dramatic productivity improvements with the Core Generator

Support for industries highest density FPGA XC40250XV 500K system gates

Guarantee your design performance with min & max timing


Expanding the Leadership The latest Xilinx software delivers

Support for the industry’s 1st 1M gate FPGA DesignsThe industries fastest timing-driven compile times

50% faster compile times Max Design performance: AKAspeedtm technology

Up to 30% faster performance Higher productivity with HDL Simulators Model Technology Eval in the Box


Performance Based DesignTiming Driven Technology

Maximum Device Performance — Achieve max design performance: AKAspeedtm technology— Robust timing constraints language, SMARTspecs— 40% Higher Performance with the Floorplanner— Xilinx Core Generator — Industry’s Fastest Devices

Highest Area Utilization Available— > 95% Device Utilization

Flexibility — Freedom to choose the most cost effective device— Design changes with repeatable performance


Achieve Maximum Performance with AKAspeedtm

Technology

Optimized for Today’sHigher Performance

Higher Density Designs

Minimum delays Voltage and temperature proratingGraphical constraints editor Graphical FloorplannerIntegration with CORE Generator

Timing-driven implementation K-pathsAdvanced timing analysis algorithmsRobust timing languageIncremental DesigningCores

New Algorithms

Features

Enhancements to v1.4


Flexibility Provides a Productivity Edge

Flexibility — Freedom to choose the most cost effective device— Design changes with repeatable performance

Easy to track design change with revision control Instant software access with registration-based security Extensive Platform/OS Support

— Win95, WinNT 4.0, NEC PC98— Chinese, Korean & Japanese Windows— Solaris 2.5 & 2.6, HP-UX 10.2, IBM RS6000 AIX 4.1.5— CDE


Guides user to the best constraint methodology Eliminates need for user knowledge of syntax Reduces need for user knowledge of design nets & components

Constraint Entry Made Easier


Floorplanner

Specify physical placement to

reduce routing delays & increase performance up to 40%

Area constraints for modules provide

faster runtimes higher

performance design changes

made easier


HDL VerificationWe will take you to the leaders

Why simulate? Reduce time-to-market 25% Errors early in the design cycle (RTL)

are inexpensive to fix Bottom up and team design for large

designs require each module to be verified

It takes twice as long to isolate a bug in hardware than in simulation

Xilinx will take you to the leaders Visit our HDL Verification Website for our premier partners, articles & design

guides

http://www.xilinx.com/products/alliance/verifi.htm


BusInterface

MemoryInterface

DMAModule

CustomDesign

AppSpecificModule

Processor

Cores are essential to High Density Designs General purpose delivery

vehicle for IP Predictable & repeatable

Independent of device size Constant performance as

more cores are added Advance specification

Compatible with HDL Design Flows

High PerformanceReduce Design Time


1999 2000

Feat

ures

and

Enh

ance

men

ts

Alliance 2.1• New Device Families • Reduced Runtimes• Ease of Use• Enhanced Synthesis QOR & Flows• Modular & Team Design • Guide for Synthesis• Enhanced Core Generator Integration• Improved HDL Verification Flows• System Verification Support

•HDL + Cores + ASIC tools 1M Gates

Alliance Future• New Device Families • Reduced Runtimes• Ease of Use• Enhanced Synthesis QOR• Core Generator Enhancements• Modular & Team Design Enhancements• Guide for Synthesis

HDL + Cores + ASIC tools 2M Gates

Alliance SeriesLeading Xilinx into Year 2000



Foundation Series Configurations

$95*

$495*

* Promotional Pricing is Valid until Version 1.5 Ships in Q3 1998.

21Xilinx Academy 4/98 21

Xilinx Ready to Use Design Solutions


Ready-To-Use Design Solutions Everything you need in one

box

Highest FPGA/CPLDperformance & density

Superior HDL design solution Unequaled Value!

Graphical Design FlowWalks you through entire design processIntegrates all tools in one environment

•Schematic Capture and HDL Design Entry•Simulation•Synthesis•Optimization•Implementation


XilinxFoundation Series

Instant Productivity Superior HDL Solution Push-Button, High Performance

Design Supports All Xilinx Devices


Instant Productivity Intuitive GUIs

Powerful Design Wizards

Mixed-Level Design Environment

Push-Button Flows

Best in Class EDA tools in a Unified Design Environment

FOUNDATIONFOUNDATIONSeries Software


FPGA Express Synthesis Window

Superior HDL Design Solution

Graphical Constraint Entry

Graphical State Editor

Synopsys FPGA Express Embedded

Mixed-Language Entry and Synthesis

Graphical HDL entry

HDL Simulation*

Time TrackerTM

* Free evaluation software delivered in box. Permanent licenses sold separately by partners


State Diagram Entry


High-Performance Design, Push-Button Design Flows

Advanced Synthesis and Optimization from Synopsys

New A.K.A. speed Technology— Graphical Constraint Entry and Static

Timing Analysis Integrated CORE-Generator

Supporting the industry’s leading Programmable Logic Devices



Complete High Volume Solution Foundation Base Express

— Ready-to-Use Software Solution— Synopsys Synthesis, Push-Button Flows, and

Low Price Spartan / XL FPGAs

— No Compromises Architecture— Performance, RAM, Cores, and Low Price

XC9500 / XL CPLDs— Most Flexible JTAG ISP Devices— Fastest Speed, Best Pin-Locking, and Low

Price



Productivity EdgeDesign Wizards

Graphical VHDL and Verilog Entry

Synopsys Synthesis

Performance Driven Design (A.K.A. Speed technology)

Complete High Volume Solution

Best Programmable Logic Performance/Density/Power

VHDL / Verilog Simulation(Free Evaluation software in the box)

Mixed-Level, Mixed-Language Design

Best Timing Driven Compile Time

Only Xilinx Delivers These Essential Capabilities



Foundation Series Product RoadmapNow Shipping!

• Foundation Ease-of-Use enhancements

• Internet Access• New HDL templates

• Advanced Performance Features

• Express 2.1.3 synthesis• New Device Support:

• Virtex (production )• Japanese Localization

Nov 1998

F1.5 F1.5i / F1.5J(minor release)


• Improved Push-Button Automation

• Improved Error Navigation• Improved Version Control• CPLD Floorplanner

• Advanced Performance Features

• Improved Simulator Capacity / Performance

• Express 3.1 / Schematic Viewer

• New Device Support: • Spartan II, XC9500XV

Mid 1999

F2.1


• Unified Project Mgmt.• Express Embedded• Plug-and-Play HDL

Simulation solutions• Advanced Performance

Features (A.K.A. Speed)• Constraints Editor• Floorplanner• Min Delay, Temp/Volt

Pro-rating• New Device Support:

• Virtex (Beta), 9KXL, 4KXLA, SpartanXL device support



Summary

Xilinx Software Solutions— Fits customer’s methodology— Best performance and utilization— Rich implementation tool set— Repeatable and adaptable designs via

– Industry’s best pin-locking – Richest timing constraint language

1997 1998 1999 2000

Gates: 85KFreq.: 65MHz+

Gates: 250KFreq.: 100 MHz+

Gates: 500KFreq.: 200 MHz+


Sell BAS & BSX Now!

FND-STD$3995Schematic

HDL

Low-Density (<10K gates) All Densities

FND-BAS$495 $95!$95!X

FND-BSX$1495X$495!$495!

Software Product Configurations

FND-EXP$4995

ALI-BAS-PC$495X $95!$95!

$4,995 =$4,995 = 37% 37%

Price ReductionPrice Reduction

All Promotional Pricing has been Extended thru mid-98


Future DirectionResponding to the Changing Landscape

SchematicSingle designer

Timing Driven PAR

SynthesisSingle designer

HDL BackAnnotation

Synthesis and CoresSmall team

Tighter ties with synthesis vendors

Cores, HDL,Design reuse,Behavioral compilerLarger design teams

Module Compile

Module Guide

TIMELINE

Evolution of FPGA Tools

Evolution of FPGA Design


Future Software FlowDesign Entry is Evolving

DesignReuse Cores Synthesized

HDLBehaviorCompile

Simulation orFormal Verification

Bitstream

Large, predefined functions

Individual modules

Team based environment

Same flow as today


Future DirectionModular Design is the Key

Seamless Integration between modules

Modular Timespecs Module Based Incremental

Compile BENEFIT = Reduced

compile times BENEFIT = Higher

performance designs

Vendor ACore

Module

Vendor BCore

Team1Design

Team3Design

Team2Design

DesignReuse


1.5 is HOT1.5 Delivers What Customers are Requesting

Runtime Improvements Constraints Editor Floorplanner Automatic Pin Locking Faster Timing Analysis (Kpaths algorithm) Automatic Clock Skew Handling New Reporting of Minimum Delays Improvements to Constraint Language Still More Improvements to Reports New ‘xilinx’ Command Launches Tools on WS’s


L1

L3L2 (1.4 default)

L4 L5

ClockSpeed

Runtime

1.3 Default

L=PAR Effort Level

New Defaults Speed Runtime

Documents

Xilinx Academy 4/98 1 Xilinx Software Solutions Xilinx Academy November, 1998