Clustering Techniques for Improving Transient Current Testing

Cezar Serhal Ali Chehab Ayman Kayssi

ECE Department, American University of Beirut Beirut 1107 2020, Lebanon

{cas10, ayman, chehab}@aub.edu.lb AbstractSeveral techniques are used to detect defects in digital integrated circuits. Among these techniques is transient current testing (iDDT). The detection capability of iDDT degrades as the size and switching activity of the circuit under test (CUT) increases. In this paper we present clustering techniques that control the switching activity of one cluster in response to applied test vector-pairs. Our clustering techniques take into consideration the physical layout of the gates in the CUT. This paper shows the results of the clustering techniques when applied to ISCAS benchmark circuits and verify, using circuit simulation, the ability of the techniques in improving defect detection capabilities of iDDT-based testing. 1. Introduction

As we move further into the realm of nanotechnology, the complexity of semiconductor design and test continues to spiral dramatically. Nanometer technologies are characterized, among other things, by a tremendous increase in circuit size, minute feature sizes, high susceptibility to process defects, an increased sensitivity of a design to process variability, and new types of defects that are not adequately represented by the current fault models and cannot be easily detected using traditional testing techniques. These characteristics and challenges are highlighted in the International Technology Roadmap for Semiconductors [1].

Newly emerging defects in nanometer technologies are hard to test using traditional testing techniques [2]. Consequently, more effective techniques are being investigated and proposed by researchers, and many such techniques focus on current-based testing. Among these techniques we mention IDDQ testing [3]-[5] and dynamic current (iDDT) testing [6]-[8]. However, at nanometer technologies, the total background leakage current is rising sharply and as a result it is degrading the quality of IDDQ tests.

The Double Threshold technique [8] is one of the transient current testing methods that examine the peak value of iDDT. The Double Threshold technique

excites the CUT with a set of test vector pairs to activate every net. The response of the CUT is compared against a lower and an upper bound threshold that correspond to defect free behavior. However, as the size of the circuit increases, the transient current response of a large defective circuit is not much different from the response of the good circuit. One way to address this issue is to limit the switching activity of the circuit being tested to a certain maximum threshold by relying on a clustering technique where different clusters have separate power supplies and are tested separately.

Several clustering and partitioning algorithms have been developed to improve data storage, data mining and VLSI design such as the multilevel k-way hypergraph partitioning algorithm [9] and TPART [10]. In VLSI, clustering is mainly used for solving logical element placement problems. [11] presents a net reduction based clustering tool to achieve faster and better quality layouts. [12] presents an analytic placer that reduces wire length and spread cells. Thus, the questions we are trying to answer in our work arise: Could clustering the CUT improve transient current testing? And on what bases should the CUT be clustered? How could the placement of the logical elements be incorporated in clustering techniques?

In [13], a clustering technique was proposed in order to improve iDDT-based testing. However, the technique did not take into consideration the physical layout of the CUT and only one approach was used to perform the clustering which is not suitable for all types of circuits. Our proposed clustering technique tries to keep physically adjacent cells in the same cluster and we show that the clustering itself needs to be performed differently for different types of circuits.

The rest of this paper is organized as follows: in Section 2 we introduce the proposed clustering techniques. In Section 3 we present the clustering results and show how clustering improves iDDT-based testing. In Section 4, we propose and compare four different starting points when applying clustering algorithms. We conclude the paper in Section 5.

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2. Proposed Clustering Techniques One of the most important criteria for the

proposed clustering techniques is to limit the switching activity of every cluster in response to the test vector pairs.

2.1 Circuit Physical Structure

Aside from controlling the maximum simultaneous transistor switches, the proposed clustering algorithms aims at grouping, in the same cluster, gates that are physically close to each other in order to reduce the routing and power supply distribution complexity in the circuit. The notion of distance should be defined to take into consideration the physical structure of the CUT while clustering. Therefore we assign a coordinate for every gate based on its connections to other gates in the CUT. It should be noted that we do not need the final circuit layout and that the information in the circuit’s netlist suffices. Moreover, the data generated from clustering could be helpful in designing the final circuit layout.

Our placement algorithm works in three phases. First we divide the circuit into different levels while preserving level zero for inverters that have primary inputs. This is equivalent to assigning x-coordinates to logic gates. Typically, a gate level is computed as one more than the highest gate level connected to its inputs. Gates in level one are those with inputs coming from inverters in level zero or from primary inputs.

Next we divide each level into slots with y coordinates. For every gate in a level we calculate its nominal y coordinate as the average of the y-coordinates of the gates connected to its inputs. For level zero gates and gates in level 1 with only primary inputs, the y coordinates are calculated as the average of the index (numbering) of their primary inputs as shown in the “BENCH” format of circuit netlists. Also, when calculating the nominal y coordinate of a gate with inputs coming from other gates and primary inputs, we neglect the primary inputs to improve the alignment of gates. After the nominal y-coordinate of a gate is calculated, we place it in the closest empty slot in the current level. Finally, we compress the generated layout so that none of the rows is empty. When we apply this placement algorithm to the ISCAS’85 benchmark circuit C432, we obtain the structure shown in Figure 1, where the letters are used to indicate the types of gates and inputs as follows: P (primary input), A (AND), D (NAND), O (OR), R (NOR), X (XOR), and N (NOT).

2.2 Gate Clustering We present two strategies for forming the actual

clusters. The first strategy is the “level-by-level” clustering strategy where we search for gates to add to a cluster level by level. The second strategy is the “spiral” clustering strategy where we search for gates to be added in a spiral fashion around a center gate. We also show in Section 4 the effect of starting the clustering algorithms at different gates in the circuit.

Note that prior to the start of the algorithm, we compute the switching information for the whole circuit. For every test vector-pair, we mark the gates that switch as a result of the application of that pair. We also record for every gate which test vectors cause it to switch.

The level-by-level clustering algorithm flowchart is shown in Figure 2. The algorithm loops through all the gates in the circuit, and once it finds an un-clustered gate, it forms a new cluster centered at the gate found, it updates the transition list that switches the cluster, and it sets the current level to the level containing the center gate. The current level is searched for an un-clustered gate starting at the center gate and expanding in opposite directions. If an un-clustered gate was found, the algorithm checks whether there is an intersection between the transitions that switch the gate and those that switch the cluster, in case there were, we add the gate only if its addition does not violate the maximum number of simultaneous switches per cluster. If the gate fits in the cluster, the transition list that switches the cluster is updated and the gate is added. Otherwise, we search for another un-clustered gate in the current level. If there are no un-clustered gates in the current level, we move to the next level and repeat the process in case the spatial limit is not violated. Otherwise we move to the next un-clustered gate in the circuit to form a new cluster and repeat the process.

Concerning the spiral strategy, once a gate initiates a cluster, we start adding gates to the cluster by searching the neighboring gates within a square of diagonal diameter 2 2R centered on the first gate that initiated the cluster. The value of R is a design parameter that can be varied to obtain homogeneous clusters. The algorithm flowchart is shown in Figure 3. The algorithm in this case loops through all the gates in the circuit; once it finds an un-clustered gate, it forms a cluster and starts to add neighboring gates starting with a radius of one unit and incrementing it one unit at a time – after all the gates within a radius are traversed – until the spatial limit is violated or the maximum allowed switching activity is reached.

Figure 1. C432 physical structure

Figure 2. Level-by-level clustering algorithm

3. Clustering Results In general, the clusters in a circuit should be as

dense as possible in order to reduce the number of clusters. In addition, the gates in a cluster should be physically close to each other in order to simplify routing and power distribution. Thus, we define the following figure of merit (FOM) in order to compare the results of different clustering algorithms:

10000 (number of gates in cluster)(area of cluster) (total number of gates in circuit)

FOM

The value of 10000 is simply a scaling factor used to compensate for the small FOMs obtained for large circuits due to the large number of gates they contain.

From the FOM definition we can see that as the area of the cluster decreases and therefore the spread of gates decreases, FOM increases. Also, as the density of gates in the cluster increases, FOM increases.

Figure 3. Spiral clustering algorithm

We compare the two clustering algorithms using,

as an illustration, the ISCAS C499 circuit. For both algorithms we start at the first gate in the netlist. To properly compare the two techniques, we computed the FOMs for different values of the radius (R) ranging from 5 to 15 and for different values of switching activity per cluster (CS) ranging from 5 to 10. The results are shown in Figures 4 and 5. Every column in the tables in these two figures has 2 entries, the first one is the number of clusters obtained and the second number is the average FOM. In the tables we see that as the cluster size (CS) or radius (R) increases, the capacity and the spread of the clusters increases leading to a decrease in the number of clusters needed to cover the circuit. If we look at the average FOM, we see that it fluctuates with a tendency to increase as CS increases and decrease as R increases. Figure 6 depicts the behavior of the average FOM for the clusters of the ISCAS C499 upon clustering with radii 5, 10 and 15 and cluster size 5 to 10. From the graph we can see the significant effect the radius has on the average FOM. For instance for R=5 the radius is small enough to guarantee no fluctuations in average FOM. On the other hand for R=10 FOM increases as CS increases

till it reaches CS=3, beyond which the large radius allows the clusters to accommodate gates that are far away and do not violate CS=4 this increases the spread of clusters and consequently decreasing the average FOM. Then the average FOM rises again as adjacent gates are added to the cluster. R=15 exhibits similar behavior as R=10.

Figure 7 plots the average FOMs of the spiral and level-by-level algorithms for CS 9 and 10. We can observe that most of the FOMs for the spiral algorithm are larger than those for the level-by-level algorithm for the same cluster size. Thus, the spiral algorithm yields more compact clusters.

To illustrate the effect of clustering on testability of the circuit, we consider the C432 circuit. A single defect introduced in the circuit does not produce any noticeable change in the transient current waveform as simulated in SPICE, and the defect goes undetected. However, after running the spiral clustering algorithm with a maximum cluster switching activity of CS = 8 and a radius limit R = 10 (resulting in 9 clusters), SPICE simulations on the good and defective clusters show a difference in the peak transient current values of 40 uA or 22%. We repeat the same procedure and

run the spiral algorithm but limit CS to 7 (resulting in 10 smaller clusters). This time we obtain a difference in the peak values of iDDT between the good and defective clusters of 100 uA or 35%. Hence we conclude that fault detection becomes much easier after clustering, and is enhanced as we reduce the switching activity in a cluster. Reducing the switching activity to very small values, however, results in a large number of small clusters and in smaller FOMs. 4. Clustering with Different Starting Gates

The clustering technique can be applied to a circuit starting with different gates as a starting point. We have experimented with clustering by starting from the first gate in the netlist, from the last gate, from the gate that has the maximum switching activity (i.e. the gate that is switched by the largest number of test vector pairs), or from the gate with the minimum switching activity. We applied the spiral clustering to ISCAS85 circuits C432, C499, C880, and C1355 starting at these 4 different gate positions. For each run we computed the number of clusters and the average FOM for different radii and different values for the maximum allowed switching activity per cluster. The results show that there is no consistent single starting gate that yields the best FOM for all types of circuits.

Instead, for every circuit, there is a certain starting gate that produces the best FOM. We conclude that the best starting gate depends on the circuit structure, the radius and the switching activity. We provide a sample of the results in Figure 8 where we show plots of FOM versus the cluster radius while fixing the switching activity at 7 for the C432 circuit.

5. Conclusions

In this paper, we presented a novel approach to iDDT-based testing that improves its defect detection capability and extends its applicability to large circuits. The proposed clustering techniques generate dense clusters by taking into consideration the physical proximity of gates. The first algorithm employs a level-by-level technique, while the second uses a spiral technique. The results show that the spiral technique provides denser clusters and therefore better results. Also we found that there is no consistent best starting point for all circuits and that it depends on the circuit structure, radius, and switching activity. To show the importance of clustering, we performed SPICE simulations on good and defective clusters with different switching activities and showed that defect detection using iDDT-based testing becomes easier as the switching activity in a cluster is reduced.

Figure 4. Spiral clustering on C499 starting at the first gate

Figure 5. Level-by-level clustering on C499 starting at the first gate

Figure 6. FOM versus cluster size for spirally clustering C499 with radii 5, 10 and 15

Figure 7. FOM versus cluster radius for C499 for

clustering with cluster size 9 and 10

Figure 8. FOM versus cluster radius for C432 at a switching activity CS = 7

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