Application of multidimensional estimation algorithms in cyclic A/D converters

Konrad Jędrzejewski*

Institute of Electronic Systems, Faculty of Electronics and Information Technology, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warsaw, Poland

ABSTRACT

The paper presents a new approach to reduction of influence of disturbances on performance of cyclic analog-to-digital converters (ADC). The approach is based on application of multidimensional estimation algorithms for simultaneous estimation of both input sample value and parameters of disturbances. Implementation of these algorithms is possible in a new class of adaptive cyclic ADCs whose digital parts permit to calculate iteratively output codes in form of binary words using simple mathematical operations. Estimation of parameters of disturbances enables their compensation and elimination of their influence on the conversion performance. Results of selected simulation experiments related to analysis of the efficiency of the proposed method in reduction of disturbances influence on final performance of adaptive cyclic ADCs are also presented and discussed in the paper.

Keywords: cyclic A/D converters, adaptive estimation algorithms, optimization.

1. INTRODUCTION

In this paper, a new approach to reduction of influence of internal or external disturbances of different kinds (interferences, drifts, systematic errors) on performance of cyclic analog-to-digital converters (ADC) is presented. The approach is based on application of the multidimensional adaptive (iterative) estimation algorithms proposed in [1] in cyclic ADCs. Implementation of these algorithms is possible in a new class of adaptive (also called intelligent) cyclic ADCs whose basic concepts and particularities of operation were presented in [2]-[4] and other works. Previous investigations on adaptive cyclic ADCs focuses on the scalar version of converters in which the simplest one-dimensional version of the estimation algorithm was employed only for estimation of an input sample. The main feature distinguishing the adaptive cyclic ADCs from other cyclic ADCs is calculation, in each cycle of conversion, subsequent codes (estimates) of the input sample as binary words of the fixed length compN , e.g. 16,20,24compN = or more bits, which depends on required performance of the converter. This creates a possibility to compute the codes using the adaptive estimation algorithms. The codes computing algorithms used in the adaptive cyclic ADCs result from the analytical approach [1] to optimization of adaptive estimation algorithms. The results of earlier investigations on the scalar version of the adaptive cyclic ADC were verified using its ASIC prototype realized in CMOS 0.35 μm technology [5], which confirms a possibility of practical realization of adaptive cyclic ADC. Principles of adaptive cyclic ADC operation for one-dimensional (scalar) version are shortly presented in section 2. The next section presents a new approach of A/D conversion based on application of multidimensional versions of the adaptive estimation algorithms. Since cyclic ADC are characterized by a relatively long conversion time of one sample (several cycles per one input sample), errors caused by internal and external disturbances, related to changes of the value of a converted sample during its processing, may worsen dramatically the conversion quality. On the other hand, development of contemporary nanometer CMOS manufacturing processes and production of high-performance digital systems with low power consumption and small sizes of characteristic dimensions of transistors resulted in a significant increase of influence of many disturbances on the quality of ADCs. This increase is connected with larger leakages in nanometer-scale transistors, larger impact of technological dispersions, low supply voltage and in consequence small quantization

*konrad.jedrzejewski@ise.pw.edu.pl; phone +48222345883; fax +48228252300; pw.edu.pl

Photonics Applications in Astronomy, Communications, Industry, and High-Energy PhysicsExperiments 2011, edited by Ryszard S. Romaniuk, Proc. of SPIE Vol. 8008, 80080G

© 2011 SPIE · CCC code: 0277-786/11/$18 · doi: 10.1117/12.905428

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VDC

C°qG

uq co

DYC

intervals, interferences coming from digital blocks placed in the same chip as ADCs (especially in so called Systems on Chip - SoC). Application of the multidimensional estimation algorithm in adaptive cyclic ADCs, which is proposed in this paper, allows concurrent estimation of both the input sample value and parameters of disturbances (interferences, drifts). This enables compensation of disturbances and reduction of their influence on final ADC performance. In section 4, results of simulation experiments which illustrate advantages of application of the multidimensional algorithm in adaptive cyclic ADC are presented and discussed.

2. ADAPTIVE CYCLIC ADC OPERATION PRINCIPLES

This section presents operation principles of adaptive cyclic A/D converters in the case of employing one-dimensional (scalar) estimation algorithm used only for estimation of an input sample value (see also [2]-[4]). A general block diagram of adaptive cyclic ADC is presented in Figure 1. Changes to be introduced in the adaptive cyclic ADC, necessary for the transition to employing the multidimensional version of estimation algorithm, which allow to eliminate disturbances, relate only to the application of multidimensional algorithm in the digital part of the converter and appropriate changes of values of signals controlling the analog part of the converter during sample conversion. The considered adaptive cyclic ADC operates iteratively using adaptive signal processing (estimation) algorithm to computing codes of input signal samples. In each cycle, subsequent codes (estimates) of the input sample are computed as binary words of the fixed length compN bits.

V

, 1k̂ kV −

kC

ke ky%

k̂V

k kC e

−

( )V t

, 1ˆ DACk kV −

Figure 1. General block diagram of adaptive cyclic A/D converter.

The conversion of an input sample in adaptive cyclic ADC is as follows. The analog input voltage ( )V t is sampled in the sample-and-hold (S/H) block and a voltage ( )V nT V= is held during the sampling interval T permitting to complete K cycles of conversion. In each k-th cycle ( 1,2,...,k K= ) of conversion the voltage value V at the input of an analog subtractor Σ should be constant. However, in many situations this value changes during the conversion process. The second (negative) input of the subtractor Σ is connected to the output of the internal D/A converter (DACIn). DACIn produces an analog voltage , 1

ˆ DACk kV − from the binary DACN -bit code ( DAC compN N< ) of the estimate (prediction) , 1k̂ kV −

calculated in the previous stage. The subtractor Σ forms a residual signal , 1ˆ DAC

k k k ke V V ν−= − + , which is routed to the input of the controlled amplifier A with a gain coefficient kC . The amplified signal k kC e is routed to the input of the internal coarse A/D sub-converter (ADCIn) with the resolution NADC usually taking values from 1 to 6 bits. The sampling rate of ADCIn is K times greater than the sampling rate of AC ADC. The adequate model of ADCN -bit code ky% formed by ADCIn, which takes explicitly into consideration the possible overloading of the converter caused by the limited input range [ , ]D D− of ADCIn, is as follows:

for

, sign( ) for

k k k kk k

k k k

C e C e Dy

D e C e Dξ

≤⎧ ⎫⎪ ⎪= +⎨ ⎬>⎪ ⎪⎩ ⎭% (1)

where kξ is a noise associated primarily with quantization of the signal k kC e in ADCIn. Next, the ADCN -bit code ky% is routed to the digital part of the converter which computes the estimate (code) k̂V of the input sample on the basis of its

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value calculated in the previous stage 1k̂V − and the output code of ADCIn according to the following relationship:

1ˆ ˆ ,k k k kV V L y−= + % (2)

where kL is the digital coefficient connected with the gain coefficient kC of the analog amplifier A. The described above process is repeated in each conversion cycle.

Performance of the conversion process in adaptive cyclic ADC is dependent on the values of the gains kC and digital coefficients kL in the digital part, as well as on the compensation signal , 1k̂ kV − [3]. Derivation of the optimal estimation algorithm consists in finding, for each cycle k, the values of kC , kL , and , 1k̂ kV − , which minimize the mean square error (MSE) of estimates k̂V (conversion errors) 2ˆ[( ) ]k kP E V V= −

and simultaneously maximize the effective number of bits

(ENOB) of the converter [3]. It can be shown that the greater gains kC of amplifier, the lower MSE of estimates k̂V . However, enlargement of the gains kC is limited by the limited input range of the internal sub-converter [−D, D] and the values of kC should be set to the maximal acceptable values excluding potential overloading. Using the approach proposed in [1], under the assumption of Gaussian distribution of signals and noises, we can derive formulas for optimal values of the gains kC , maximal under a given acceptable probability of overloading μ , as well as for corresponding values of the coefficients kL . The requirement for the acceptable probability μ of overloading (condition of statistically fitted observation [1]) can be formulated as follows:

11Pr{ | } 1 .k

k kC e D y μ−≤ ≥ −% (3)

It means that for each kC and , 1k̂ kV − satisfying (3), the probability of overloading does not exceed a given small number μ at each cycle of conversion. Value of μ is chosen according to requirements to the quality of conversion. It determines the permissible percentage of saturated and distorted output codes. Solution of the appropriate optimization task using the approach presented in [1] gives the following expressions for optimal values of the gains kC and coefficients kL in the case of one-dimensional algorithm:

12 2 22

11

, 1 ,k k kk k k

k kk

P C PDC L CP CP ξ νν

σ σα σ−

−−

⎛ ⎞= = − =⎜ ⎟ ++ ⎝ ⎠

(4)

where the values of MSE of conversion are calculated according to the relationship:

2 2 2

12 2 2

1

( ).

( )k k

kk k

C PP

C Pξ ν

ξ ν

σ σσ σ

−

−

+=

+ + (5)

Additionally, the optimal compensation is equal to the value of the input sample estimate from the previous cycle: , 1 1

ˆ ˆk k kV V− −= . Saturation factor α in (4) is determined by the permissible probability μ of overloading and in Gaussian

case satisfies the equation ( ) (1 ) / 2α μΦ = − , where ( )αΦ is the tabulated Gaussian error function. Variables 2νσ and 2

ξσ in relationships (4) and (5) represent the variances of noises kν at the output of the subtractor Σ (caused, among others, by the finite resolution of DACIn) and kξ at the output of ADCIn (caused, first of all, by quantization), respectively.

Application of the algorithm (3-5) and its modifications [6], [7] in adaptive cyclic ADC enables obtaining ENOB greater than in conventional cyclic ADCs with similar analog parts (components) under comparable probability of overloading [2]-[4]. This is a consequence of introducing long-bit calculations to adaptive cyclic ADC that permits to remove inevitable in conventional cyclic A/D converters constraints on the gain coefficients. In conventional cyclic A/D converters, they should have only the values equal to integer powers of two. Impossibility to set the gains to each theoretically required value restricts possibilities to utilize entirely resources of the analog components of the converter for reduction of influence of technological errors and noises. In known cyclic A/D converters, to avoid overloading in each cycle, designers have to decrease artificially the gains kC and use so-called redundant bits in sub-codes and the problem is solved by resignation from “probably erroneous” bits. This results in incomplete utilization of the resources of converter components and decreases its final resolution and ENOB. In adaptive cyclic ADCs, potential overloading is

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excluded by setting, in each cycle, the amplifier gains kC and coefficients kL to the optimal values determined analytically, guaranteeing the given (acceptable) probability of overloading. One of the modifications mentioned above and used also in this paper to improve the quality of conversion of adaptive cyclic ADC is related to the finite resolution of the internal D/A converter DACIn and consists in taking instead of the value ky% in (2) its corrected value

, 1ˆcorr DAC

k k k k ky y C V −= − Δ% % , where , 1 , 1 , 1ˆ ˆ ˆDAC DACk k k k k kV V V− − −Δ = − is a difference between the calculated compN -bit long digital

estimate k̂V and its DACN -bit long equivalent at the input of DACIn [6]. At the end of this section, it is worth noticing that implementation of adaptive estimation algorithm in cyclic A/D converter requires no change in architecture of analogue part of known cyclic A/D converter, and only digital part of the converter is to be modified.

3. MULTIDIMENSIONAL ESTIMATION ALGORITHM OF A/D CONVERSION

In the further part of the paper, we assume that during the sample conversion the input sample value V at the input of the amplifier A is disturbed by an additive disturbance ki and the disturbed input sample values kV in the subsequent cycles of conversion ( 1,2,...,k K= ) can be modeled in the form of the regression type model:

( ) ( ) ( ) ( )

2 1

,L L

l l l l Tk k k k k

l l

V V i V X Xθ θ= =

= + = + = =∑ ∑ θ X (6)

where V is the value of the converted input sample, ki is the value of the disturbance at k-th cycle, (2) ( )[ , ,..., ]L TV θ θ=θ is a vector of unknown amplitudes of known components (2) ( )[1, ,..., ]L T

k k kX X=X . The first element in the vector θ is the input sample value (1) Vθ = and the corresponding known component is (1) 1kX = , for k = 1, 2, …, K. Other products

( ) ( )l lkXθ relate to different disturbances which can be modeled as a product of the unknown amplitude to be estimated

and the deterministic component with known form. Simple examples of the model (6) usage are presented below:

1. Model of a voltage at the output of S/H block which may drift over a conversion time (in a hold mode) due to imperfections in a hold capacitor, switch or S/H output amplifier [8]:

,k kV V dβ= + (7)

where β is an unknown rate (amplitude) of the drift-like component, which has the known form kd e.g. 1kd k= − (linear drift) or ( 1)1 k

kd e γ− −= − (exponential drift). Then the vectors θ and kX take the following forms: [ , ]TV β=θ – vector of unknown parameters to be estimated, [1, ]T

k kd=X – two known deterministic components.

2. Model of an input sample values kV in the case of presence of harmonic interferences [9]:

(1) (2)0 0 0sin(2 ) sin(2 ) cos(2 ),kV V A f k V A f k A f kπ ϕ π π= + + = + + (8)

where A and φ are the amplitude and phase of the harmonic interference, f0 is normalized frequency assumed to be known, (1) cosA A ϕ= , (2) sinA A ϕ= – amplitudes of I/Q components of harmonic interference. In this case

(1) (2)[ , , ]TV A A=θ and 0 0[1,sin(2 ),cos(2 )]Tk f k f kπ π=X . Model (8) can describe many interferences acting on the

internal analog circuits of ADC coming from supply circuits, electric or electronic devices operating in their surrounding, as well as from external electromagnetic fields.

The optimal method of estimation of the input sample V in case of the disturbance defined by the model (5) is equivalent to the optimal method of estimation of the multidimensional vector (2) ( )[ , ,..., ]L TV θ θ=θ , where (2) ( ),..., Lθ θ are amplitudes of disturbance components (2) ( ),..., Lθ θ . In the multidimensional case, the residual signal ke has the form

, 1ˆ DAC

k k k k ke V V ν−= − + , where , 1ˆ DACk kV − is the prediction of the value of the voltage kV at the input of the subtractor Σ. The

prediction , 1ˆ DACk kV − in the k-th cycle is calculated on the basis of estimates (2) (3) ( )

1 1 1 1 1ˆ ˆ ˆ ˆˆ[ , , ,..., ]L T

k k k k kV θ θ θ− − − − −=θ computed in the previous (k – 1)-th cycle and is routed to the negative input of the subtractor Σ:

(2) (2) ( ) ( ), 1 1 1 1 1

ˆ ˆ ˆ ˆˆ ... .T L Lk k k k k k k k kV V X Xθ θ− − − − −= = + + +θ X (9)

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In the case of the multidimensional estimation algorithm, relationship (2) is substituted by the following expression for updating the vector of estimates (2) (3) ( )ˆ ˆ ˆ ˆˆ[ , , ,..., ]L T

k k k k kV θ θ θ=θ :

1ˆ ˆ ,k k k ky−= + %θ θ L (10)

where (1) (2) (3) ( )[ , , ,..., ]L Tk k k k kL L L L=L is the vector of coefficients used in the digital part of adaptive cyclic ADC.

Optimal values of gains kC and vector (1) (2) (3) ( )[ , , ,..., ]L Tk k k k kL L L L=L are obtained using the approach proposed in [1] as

the values minimizing for each 1,2,...,k K= values of MSE of estimation 2ˆ[( ) ]k k kS E V V= − Tk k k= X P X under given

probability of overloading μ . Matrix ˆ ˆ[( )( ) ]Tk k kE= − −P θ θ θ θ describes the covariance matrix of the estimates ˆ .kθ

Solution of the optimization task gives the multi-dimensional version of the algorithm of optimal signal parameters estimation [1]:

12 2 22

11

, ,( )

k k kk k TT

k k k kk k k

CDCCξ νν

σ σα σ−

−−

= =+ ++

P XLX P XX P X

(11)

2

1 11 2 2 2

1

.( )

Tk k k k k

k k Tk k k k

CCξ νσ σ

− −−

−

= −+ +

P X X PP PX P X

(12)

Initial conditions for the algorithm (9-12) are usually as follows: 0 [0,0,...,0]T=θ , ( 2) ( )2 2 2

0 ( , ,..., )LVdiagθ θ

σ σ σ=P , where ( )

2 2, lV θσ σ are known (a priori) variances of the converted sample value and disturbances parameters, respectively.

The multidimensional algorithm (9-12) looks a little bit complicated but its implementation in the digital part of the adaptive cyclic ADC resolves itself into implementation of the formula for the prediction of the input voltage (9) and L operations for estimates (2) (3) ( )ˆ ˆ ˆ ˆˆ[ , , ,..., ]L T

k k k k kV θ θ θ=θ updating:

(1) (2) (2) (2) ( ) ( ) ( )1 1

ˆ ˆ ˆ ˆˆ ˆ , , ..., .L L Lk k k k k k k k k k k kV V L y L y L yθ θ θ θ− −= + = + = +% % % (13)

Calculations for optimal gains and coefficients (11-12) can be performed off-line before their implementation in the converter.

Values of gains and coefficients (11) minimize MSE of conversion under the assumption of Gaussian distribution of signals and noises, while quantization noise ξk of internal A/D converter ADCIn is non-Gaussian, as well as other nonlinearities exist in the adaptive cyclic ADC. For this reason, application of the algorithm (9-12) to adaptive cyclic ADC makes it not completely but sub-optimal. The latter means a possibility of further improvement of adaptive cyclic ADC using corrections of the gains and coefficients (11) similar as in the case of scalar algorithm, which was described in [6], [7]. It is worth emphasizing that application of the multidimensional algorithm (9-12) requires no change in the architecture of the scalar version of the adaptive cyclic ADC but only insignificantly extends the digital part of the converter.

4. RESULTS OF SIMULATION EXPERIMENTS

In order to study particularities of the adaptive cyclic ADC employing multidimensional algorithm, both ADC with multidimensional version of algorithm and one-dimensional (scalar) algorithm were modeled in MATLAB and their work was simulated for the same input signals, noises and disturbances.

The following model of the changes of an input sample value during K cycles of conversion with disturbances was taken into consideration in simulation experiments:

(1) (2)0 0 0( 1) sin(2 ) ( 1) sin(2 ) cos(2 ).kV V k A f k V k A f k A f kβ π ϕ β π π= + − + + = + − + + (14)

This model includes both a linear drift and one harmonic interference. Architecture and values of basic parameters of the analogue parts in both versions of ADC, assumed in simulations, were the same as in the laboratory prototype of the

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scalar adaptive cyclic ADC designed in CMOS technology [5]: 1 [V]D = , 4ADCN = , 12DACN = , and values of other parameters were as follows: 3α = , 2 2 /12V FSRσ = , 0 0.1f = , 2 / 3ADCNDξσ

−= ⋅ , 2 / 3DACNDνσ−= ⋅ .

Figure 2. Values of input voltage with disturbances versus number of cycles for the input sample value 0.2 [V]V = , drift rate

0.1 [mV/cycle]β = − , amplitude of harmonic interference 0.5 [mV]A = .

a) b)

c) d)

Figure 3. Estimates of input sample value (a) and disturbances amplitudes (b – drift), (c – harmonic interference), and estimates of of

the total sample value with disturbances versus number of cycles for 0.2 [V]V = , 0.1 [mV/cycle]β = − , 0.5 [mV]A = .

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In the first series of experiments, single runs of estimates for subsequent cycles of conversion were analyzed. The following values of parameters of the signal (14) were assumed: 0.2 [V]V = , 0.1 [mV/cycle]β = − , 0.5 [mV]A = ,

/ 4ϕ π= , 1 [mV]βσ = , 1 [mV]Aσ = . Figure 2 presents changes of the values of input sample disturbed according to (14) for these parameters versus number of cycle of conversion. The results of simulations are presented in Figure 3 where blue lines correspond to application of the scalar (one-dimensional) algorithm, and red lines – to the multidimensional algorithm. Figure 3a shows typical runs of estimates k̂V of the input sample V for the one-dimensional and multidimensional algorithms used in the adaptive cyclic ADC. The trajectory of estimates of the drift rate β and the amplitude A of sinusoidal interference obtained by the multi-dimensional algorithm are presented in Figures 3b and 3c, respectively. Figure 3d shows typical runs of estimates ˆ

kV of the disturbed input voltage kV in subsequent cycles of conversion for both algorithms. Plots in Figure 3d show the capability of the multidimensional algorithm to track changing input voltage, which is impossible in the case of application of the one-dimensional algorithm.

In the next series of simulations, changes of empirical values of Effective Number of Bits (ENOB) in output codes of adaptive cyclic ADC in subsequent cycles of conversion for both versions of algorithm were investigated and compared. The empirical values of ENOB in output codes were computed according to the definition given in [10]:

( ) ( ) 22

1

1 1ˆˆ ˆlog , [ ] ,ˆ2 12

Mm m

k k kmk

FSRN S V VMS =

⎛ ⎞= = −⎜ ⎟⎜ ⎟

⎝ ⎠∑ (15)

where 2FSR D= is Full Scale Range of the converter and M is a number of samples converted in a given experiment. The particular experiments were carried out for sequences of 10000M = uniformly distributed in the input range samples ( )mV ( 1,..., )m M= converted in the presence of disturbances described by model (14). For every input sample, random values of amplitudes of drift β and I/Q harmonic components (1) (2),A A were generated independently with Gaussian distributions and standard deviations βσ and Aσ , respectively. The simulation results obtained for two pairs of standard deviations 0.1 [mV]βσ = , 0.1 [mV]Aσ = and 1 [mV]βσ = , 1 [mV]Aσ = are shown in Figure 4 a and b in the form of runs of ENOB depending on a cycle number. Red plots in both figures show that values of ENOB for adaptive cyclic ADC with the multidimensional algorithm continue the further increase after 5-th cycle, because of the proper estimation of disturbances parameters and their compensation, while ADC with the one-dimensional algorithm, blue lines, is not able to work properly for such disturbances.

a) b)

Figure 4. ENOB versus number of cycle for ADC with one-dimensional (blue lines) and multidimensional (red lines) algorithms for

(a) 0.1 [mV]βσ = , 0.1 [mV]Aσ = and (b) 1 [mV]βσ = , 1 [mV]Aσ = .

The next simulation experiments were more general. The behaviour of empirical values of ENOB as a function of a cycle number were invesigated for different values of standard deviations of drift βσ and harmonic components Aσ amplitudes. Figures 5 and 6 present results of these simulations, Figure 5 for a fixed value of 1 [mV]Aσ = and Figure 6

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for a fixed value of 0.1 [mV]βσ = . Figures 5a and 6a relate to application of one-dimensional algorithm, and Figures 5b and 6b - to application of multidimensional algorithm. Plots on both Figures 5a and 6a show that even small values of disturbances cause a degradation in the effective number of bits (ENOB) of adaptive cyclic ADC employing one-dimensional algorithm, while Figures 5b and 6b show that adaptive cyclic ADC with multidimensional estimation algorithm can cope with these disturbances and work satisfactorily in the wide range of values of disturbances amplitudes. The obtained results confirm a significant advantage of application of the multidimensional algorithm in adaptive cyclic ADC to conversion of input signals in the presence of disturbances.

a) b)

Figure 5. ENOB versus number of cycles for different standard deviations βσ of the drift rate and 1 [mV]Aσ = for one-dimensional

(a) and multidimensional (b) algorithms.

a) b)

Figure 6. ENOB versus number of cycles for different standard deviations Aσ of the harmonic interference amplitudes and

0.1 [mV]βσ = for one-dimensional (a) and multidimensional (b) algorithms.

5. CONCLUSIONS

The results of the paper show a possibility to design adaptive cyclic ADCs robustified to internal and external disturbances of different types. The new method of application of multidimensional estimation algorithms in adaptive cyclic ADCs enables estimation of parameters of disturbances and their compensation during the conversion of an input sample. Application of the multidimensional estimation algorithms requires no change in the architecture of the

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conventional adaptive cyclic ADC but only insignificantly extends its digital part, which practically does not influence the production costs of the converters. Simultaneous estimation of the sample value and disturbances parameters causes an increase of number of cycles needed to obtain assumed ENOB, and in consequence diminishes a sampling rate of the converter. This is the cost paid for the ability of the correct conversion in the presence of disturbances. The developed simulation tools allow assessment of a number of cycles needed to obtain an assumed value of ENOB of the converter working in the presence of disturbances.

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