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1IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
Signal Cancellation Techniques for Testing High-end Digital-to-Analog Converters
Dr. Fang XU
Teradyne, Inc
2IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
Abstract
Constant improvement in converter performance results in requirement of higher precision instrument at increasing sampling speed. Therefore, building digitizer directly using existing cutting edge ADC technology will not satisfy current and future DAC testing needs. Development of new test techniques could help to fill this technology gap. This paper explores signal cancellation technique and proposes a robust algorithm to optimize signal cancellation.
4IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
Testing tomorrow’s device with yesterday’s device
Year
Performance
State o
f art d
evice
perform
ance
State o
f art d
evice
used to
build in
strumen
t
Built from old device
Want to test future device
Technology improvement
Performance gap
Instrument architecture will fill the gap
A change for testing since this profession existed
5IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
Signal Cancellation Principle
Signal Under
Test
cancellation signal
Device noise and distortion
Dynamic rangebefore cancellation =
Dynamic rangeafter cancellation =
6IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
Signal Cancellation Challenge
Phase uncertainty
Signal Under
Test
Cancellation Signal
Device noise and distortion
Amplitude
uncertainty
Instrument architecture must offer accurate amplitude and phase control and repeatability for maximum cancellation
CSSUTR +=
Signal cancellation =
),cos(2 R22
CSSUTCSSUTCSSUT •−+=
Amplitude Phase
+= )),cos(-(12 10Log 20
2
2
CSSUTCS
SUT
CS
SUT
CS
RLog
7IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
Signal Cancellation Glossary
Glossary:SUT: Signal Under TestCS: cancellation signal, Signal of well defined characteristics used to remove the biggest part of energy from the SUTSRC: Initial signal to create CSG: Complex gain of the instrument to generate CS. It could be measured and characterized
Residue: Remaining signal after SUT and CS are combined
Signal Under
Test
Cancellation SignalR
esid
ual
SRCGCS •=
CSSUTR +=All signals must be treated as vectors
DUT
SRC G
Residue
SUT
CS
8IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
Signal Cancellation Algorithm
SUTRCS −=
00
1
RSUT
SUT
Source
Source
−=
SUTRSRCG −=• 00
For the first iteration, we have:
At the next iteration, we want the residual be as small as possible:
SUTSRCG −=• 1
Thus, we get:
From the previous slide:1. Capture SUT: Before turn on the
cancellation source, capture DUT
signal only through the power
combiner.
2. Turn on the cancellation source
with a first guess Source0,
Capture R0
3. Change the cancellation
waveform to Source1 according
to formula.
4. Capture R1
* Step 1 and 2 could be in any order
CSSUTR +=
9IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
Signal Cancellation Test Setup
DUT
BPF
50dB10bit
digitizer
TP TP
10IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
DUT Output Signal (SUT)
DUT
BPF
50dB
TP TP
10bitdigitizer
11IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
After Signal Cancellation
DUT
TP TP
10bitdigitizer
BPF
50dB
12IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
Amplified Residual Signal
DUT
TP TP
10bitdigitizer
50dB
BPF
13IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
Digitized Residual Signal
DUT
TP TP
10bitdigitizer
50dB
BPF
14IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
Cancellation Result
40dB
Cancellation of 40dBTHD sensitivity improves 10dBSFDR sensitivity improves 15dBSNR sensitivity improves 18dB
15IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
General Signal Cancellation
tTime domain arbitrary waveform
Fourier transform
SUT(t)
SUT(f)
We can apply the same signal cancellation algorithm on each component
16IMTC2007 Warsaw, Poland Dr. Fang Xu Paper 7027
High-end DAC Tested at 1kHz
SFDR > 124dB
