VLSI Arithmetic - University of California, Davisvojin/CLASSES/EPFL/Lectures/VLSI... · Lecture 5....

VLSI ArithmeticLecture 6

Prof. Vojin G. OklobdzijaUniversity of California

http://www.ece.ucdavis.edu/acsel

Review

Lecture 5

Prefix Addersand

Parallel Prefix Adders

Oklobdzija 2004 Computer Arithmetic 4

from: Ercegovac-Lang

Prefix Adders

(g0, p0)

Following recurrence operation is defined:

(g, p)o(g’,p’)=(g+pg’, pp’)such that:

Gi, Pi =(gi, pi)o(Gi-1, Pi-1 )

1 ≤ i ≤ n

ci+1 = Gifor i=0, 1, ….. n

c1 = g0+ p0 cin(g-1, p-1)=(cin,cin)

This operation is associative, but not commutativeIt can also span a range of bits (overlapping and adjacent)

Parallel Prefix Adders: S. Knowles 1999

operation is associative: h>i≥j≥k

operation is idempotent: h>i≥j≥k

produces carry: cin=0

Parallel Prefix Adders: variety of possibilitiesfrom: Ercegovac-Lang

Kogge-Stone Adder

Brent-Kung Adder

Hybrid BK-KS Adder

Pyramid Adder:M. Lehman, “A Comparative Study of Propagation Speed-up Circuits in Binary Arithmetic

Units”, IFIP Congress, Munich, Germany, 1962.

Parallel Prefix Adders: Ladner-Fisher

Exploits associativity, but not idempotency. Produces minimal logical depth

Two wires at each level. Uniform, fan-in of two.Large fan-out (of 16; n/2); Large capacitive loading combined with the long wires (in the last stages)

Parallel Prefix Adders: Ladner-Fisher(16,8,4,2,1)

Parallel Prefix Adders: Kogge-StoneExploits idempotencyto limit the fan-out to 1. Dramatic increase in wires. The wire span remains the same as in Ladner-Fisher.

Buffers needed in both cases: K-S, L-F

Parallel Prefix Adders: Brent-Kung

• Set the fan-out to one• Avoids explosion of wires (as in K-S)• Makes no sense in CMOS:

– fan-out = 1 limit is arbitrary and extreme– much of the capacitive load is due to wire

(anyway)• It is more efficient to insert buffers in L-F

than to use B-K scheme

Two Parallel Prefix Adder Structures

Kogge-Stone Han-Carlson

• log(bits) carry stages• Extra Wiring

• log(bits) + 1 carry stages• Reduced Wiring and Gates

Parallel Prefix Adders: Han-Carlson

• Is a hybrid synthesis of L-F and K-S• Trades increase in logic depth for a

reduction in fan-out:– effectively a higher-radix variant of K-S.– others do it similarly by serializing the prefix

computation at the higher fan-out nodes.• Others, similarly trade the logical depth for

reduction of fan-out and wire.

Parallel Prefix Adders: variety of possibilitiesfrom: Knowles

bounded by L-F and K-S at ends

Parallel Prefix Adders: variety of possibilitiesKnowles 1999

Following rules are used:

• Lateral wires at the jth level span 2j bits• Lateral fan-out at jth level is power of 2 up

• Lateral fan-out at the jth level cannot exceed that a the (j+1)th level.

• The number of minimal depth graphs of this type is given in:

• at 4-bits there is only K-S and L-F, afterwards there are several new possibilities.

Parallel Prefix Adders: variety of possibilities

example of a new 32-bit adder [4,4,2,2,1]Knowles 1999

Parallel Prefix Adders: variety of possibilities

Example of a new 32-bit adder [4,4,2,2,1]

Knowles 1999

• Delay is given in terms of FO4 inverter delay: w.c.(nominal case is 40-50% faster)

• K-S is the fastest• K-S adders are wire limited (requiring 80% more area)• The difference is less than 15% between examined schemes

Conclusion• Irregular, hybrid schmes

are possible• The speed-up of 15% is

achieved at the cost of large wiring, hence area and power

• Circuits close in speed to K-S are available at significantly lower wiring cost

Possibilities for Further Research• The logical depth is important (Knowles was

right)• The fan-out is less important than fan-in

(Knowles was wrong):– It is possible to examine a variety of topologies with

restricted and varied fan-in.• Driving strength and Logical Effort rules were

overlooked and at least neglected:– It is possible to create number of topologies taking LE

rules into account.– It is further possible to combine the rules with

compound domino implementation taking advantage of two different rules governing “dynamic” and “static”.

• It is still possible to produce a better adder !

Other Types of Adders

Conditional Sum Adder

J. Sklansky, “Conditional-Sum Addition Logic”, IRE Transactions on Electronic

Computers, EC-9, p.226-231, 1960.

ConditionalSum Adder

Carry-Select Adder

O. J. Bedrij, “Carry-Select Adder”, IRE Transactions on Electronic Computers, June

1962, p.340-34

Carry-Select Sum Adder

4-bit RCA

CinCin

4-bit RCA Cin

a7:4 b7:4

2:1 Mux01

8-bit CSLA Cin

a15:8 b15:8

2:1 Mux01

C115:8

C015:8

S15:8C16

Fig. 11: 16-bit Carry-Select Adder

Carry-Select Adder

Addition under assumption of Cin=0 and Cin =1.

Carry Select Adder:combining two 32-b VBAs in select mode

Delay =∆VBA32+ ∆MUX

Carry-Select Adder

O.J. Bedrij, IBM Poughkeepsie, 1962

VLSI Arithmetic - University of California, Davisvojin/CLASSES/EPFL/Lectures/VLSI... · Lecture 5....

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