(..) Computer Arithmetic--Principles, Architectures & VLSI Design

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  • ZurichTechnische HochschuleEidgenossische

    Swiss Federal Institute of Technology ZurichPolitecnico federale di ZurigoEcole polytechnique federale de Zurich

    Institut fur Integrierte Systeme Integrated Systems Laboratory

    Lecture notes on

    Computer Arithmetic:Principles, Architectures,

    and VLSI Design

    June 25, 1998

    Reto Zimmermann

    Integrated Systems LaboratorySwiss Federal Institute of Technology (ETH)

    CH-8092 Zurich, Switzerlandzimmermann@iis.ee.ethz.ch

    Copyright c 1998 by Integrated Systems Laboratory, ETH Zurichhttp://www.iis.ee.ethz.ch/ zimmi/publications/comp arith notes.ps.gz

  • Contents

    Contents

    1 Introduction and Conventions 41.1 Outline 41.2 Motivation 41.3 Conventions 51.4 Recursive Function Evaluation 6

    2 Arithmetic Operations 82.1 Overview 82.2 Implementation Techniques 9

    3 Number Representations 103.1 Binary Number Systems (BNS) 103.2 Gray Numbers 133.3 Redundant Number Systems 143.4 Residue Number Systems (RNS) 163.5 Floating-Point Numbers 183.6 Logarithmic Number System 193.7 Antitetrational Number System 193.8 Composite Arithmetic 203.9 Round-Off Schemes 21

    4 Addition 224.1 Overview 224.2 1-Bit Adders, (m, k)-Counters 23

    Computer Arithmetic: Principles, Architectures, and VLSI Design 1

    Contents

    4.3 Carry-Propagate Adders (CPA) 264.4 Carry-Save Adder (CSA) 454.5 Multi-Operand Adders 464.6 Sequential Adders 52

    5 Simple / Addition-Based Operations 535.1 Complement and Subtraction 535.2 Increment / Decrement 545.3 Counting 585.4 Comparison, Coding, Detection 605.5 Shift, Extension, Saturation 645.6 Addition Flags 665.7 Arithmetic Logic Unit (ALU) 68

    6 Multiplication 696.1 Multiplication Basics 696.2 Unsigned Array Multiplier 716.3 Signed Array Multipliers 726.4 Booth Recoding 736.5 Wallace Tree Addition 756.6 Multiplier Implementations 756.7 Composition from Smaller Multipliers 766.8 Squaring 76

    7 Division / Square Root Extraction 777.1 Division Basics 77

    Computer Arithmetic: Principles, Architectures, and VLSI Design 2

    Contents

    7.2 Restoring Division 787.3 Non-Restoring Division 787.4 Signed Division 797.5 SRT Division 807.6 High-Radix Division 817.7 Division by Multiplication 817.8 Remainder / Modulus 827.9 Divider Implementations 837.10 Square Root Extraction 84

    8 Elementary Functions 858.1 Algorithms 858.2 Integer Exponentiation 868.3 Integer Logarithm 87

    9 VLSI Design Aspects 889.1 Design Levels 889.2 Synthesis 909.3 VHDL 919.4 Performance 939.5 Testability 95Bibliography 96

    Computer Arithmetic: Principles, Architectures, and VLSI Design 3

  • 1 Introduction and Conventions 1.2 Motivation

    1 Introduction and Conventions

    1.1 Outline

    Basic principles of computer arithmetic [1, 2, 3, 4, 5, 6, 7] Circuit architectures and implementations of main

    arithmetic operations Aspects regarding VLSI design of arithmetic units

    1.2 Motivation

    Arithmetic units are, among others, core of every datapath and addressing unit

    Data path is core of :

    microprocessors (CPU) signal processors (DSP) data-processing application specific ICs (ASIC) and

    programmable ICs (e.g. FPGA) Standard arithmetic units available from libraries Design of arithmetic units necessary for :

    non-standard operations high-performance components library development

    Computer Arithmetic: Principles, Architectures, and VLSI Design 4

    1 Introduction and Conventions 1.3 Conventions

    1.3 Conventions

    Naming conventions

    Signal buses : A (1-D), Ai

    (2-D), ai:k (subbus, 1-D)

    Signals : a, ai

    (1-D), aik

    (2-D), Ai:k (group signal)

    Circuit complexity measures : A (area), T (cycle time,delay), AT (area-time product), L (latency, # cycles)

    Arithmetic operators : , , , , log ( log2 )Logic operators : (or), (and), (xor), (xnor), (not)

    Circuit complexity measures

    Unit-gate model ( gate-equivalents (GE) model) : Inverter, buffer : A 0 T 0 (i.e. ignored) Simple monotonic 2-input gates (AND, NAND, OR,

    NOR) : A 1 T 1 Simple non-monotonic 2-input gates (XOR, XNOR) :A 2 T 2

    Complex gates : composed from simple gates Simple m-input gates : A m 1 T dlogme Wiring not considered (acceptable for comparison

    purposes, local wiring, multilevel metallization) Only estimations given for complex circuits

    Computer Arithmetic: Principles, Architectures, and VLSI Design 5

    1 Introduction and Conventions 1.4 Recursive Function Evaluation

    1.4 Recursive Function Evaluation

    Given : inputs ai

    , outputs zi

    , function f (graph sym. : )

    Non-recursive functions (n.) Output z

    i

    is a function of input ai

    (or ajm:j m const.)

    z

    i

    fa

    i

    x ; i 0 n 1

    parallel structure :

    A On T O1funn.epsi

    19 17 mm1

    a0a1a2a3

    z0z1z2z3

    Recursive functions (r.) Output z

    i

    is a function of all inputs ak

    k i

    a) with single output z zn

    (r.s.) :

    t

    i

    fa

    i

    t

    i1 ; i 0 n 1t

    1 01 z tn1

    1. f is non-associative (r.s.n.) serial structure :

    A On T On

    funrsn.epsi19 24 mm

    123

    a0a1a2a3

    z

    Computer Arithmetic: Principles, Architectures, and VLSI Design 6

    1 Introduction and Conventions 1.4 Recursive Function Evaluation

    2. f is associative (r.s.a.) serial or single-tree structure :

    A On T Ologn

    funrsa.epsi19 20 mm

    12

    a0a1a2a3

    z

    b) with multiple outputs zi

    (r.m.) ( prefix problem) :

    z

    i

    fa

    i

    z

    i1 ; i 0 n 1 z1 01

    1. f is non-associative (r.m.n.) serial structure :

    A On T On

    funrmn.epsi19 25 mm

    123

    a0a1a2a3

    z0z1z2z3

    2. f is associative (r.m.a.) serial or multi-tree structure :

    A On

    2 T Ologn

    funrma1.epsi19 43 mm

    12

    a0a1a2a3

    z0

    z1

    z2

    z3

    or shared-tree structure :

    A On logn T Olognfunrma2.epsi19 21 mm

    12

    a0a1a2a3

    z0z1z2z3

    Computer Arithmetic: Principles, Architectures, and VLSI Design 7

  • 2 Arithmetic Operations 2.1 Overview

    2 Arithmetic Operations

    2.1 Overview

    arithops.epsi98 83 mm

    = , < +1 , 1 + , +/

    exp (x)

    trig (x)

    sqrt (x)

    log (x)

    >

    + ,

    fixed-point floating-pointbased on operationrelated operation

    hyp (x)

    com

    plex

    ity

    (same as onthe left for

    floating-pointnumbers)

    1 shift/extension 7 division2 comparison 8 square root extraction3 increment/decrement 9 exponential function4 complement 10 logarithm function5 addition/subtraction 11 trigonometric functions6 multiplication 12 hyperbolic functions

    Computer Arithmetic: Principles, Architectures, and VLSI Design 8

    2 Arithmetic Operations 2.2 Implementation Techniques

    2.2 Implementation Techniques

    Direct implementation of dedicated units :

    always : 1 5 in most cases : 6 sometimes : 7, 8

    Sequential implementation using simpler units andseveral clock cycles ( decomposition) : sometimes : 6 in most cases : 7, 8, 9

    Table look-up techniques using ROMs :

    universal : simple application to all operations efficient only for single-operand operations of high

    complexity (8 12) and small word length (note: ROMsize 2n n)

    Approximation techniques using simpler units : 712

    taylor series expansion polynomial and rational approximations convergence of recursive equation systems CORDIC (COordinate Rotation DIgital Computer)

    Computer Arithmetic: Principles, Architectures, and VLSI Design 9

    3 Number Representations 3.1 Binary Number Systems (BNS)

    3 Number Representations

    3.1 Binary Number Systems (BNS)

    Radix-2, binary number system (BNS) : irredundant,weighted, positional, monotonic [1, 2]

    n-bit number is ordered s

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