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  • ZurichTechnische HochschuleEidgenossische

    Swiss Federal Institute of Technology ZurichPolitecnico federale di ZurigoEcole polytechnique federale de Zurich

    Institut fur Integrierte Systeme Integrated Systems Laboratory

    Lecture notes on

    Computer Arithmetic:Principles, Architectures,

    and VLSI Design

    March 16, 1999

    Reto Zimmermann

    Integrated Systems LaboratorySwiss Federal Institute of Technology (ETH)

    CH-8092 Zurich, Switzerlandzimmermann@iis.ee.ethz.ch

    Copyright c

    1999 by Integrated Systems Laboratory, ETH Zurichhttp://www.iis.ee.ethz.ch/ zimmi/publications/comp arith notes.ps.gz

  • Contents

    Contents

    1 Introduction and Conventions 4

    1.1 Outline 4

    1.2 Motivation 4

    1.3 Conventions 5

    1.4 Recursive Function Evaluation 6

    2 Arithmetic Operations 8

    2.1 Overview 8

    2.2 Implementation Techniques 9

    3 Number Representations 10

    3.1 Binary Number Systems (BNS) 10

    3.2 Gray Numbers 13

    3.3 Redundant Number Systems 14

    3.4 Residue Number Systems (RNS) 16

    3.5 Floating-Point Numbers 18

    3.6 Logarithmic Number System 19

    3.7 Antitetrational Number System 19

    3.8 Composite Arithmetic 20

    3.9 Round-Off Schemes 21

    4 Addition 22

    4.1 Overview 22

    4.2 1-Bit Adders, (m, k)-Counters 23

    Computer Arithmetic: Principles, Architectures, and VLSI Design 1

    Contents

    4.3 Carry-Propagate Adders (CPA) 26

    4.4 Carry-Save Adder (CSA) 45

    4.5 Multi-Operand Adders 46

    4.6 Sequential Adders 52

    5 Simple / Addition-Based Operations 53

    5.1 Complement and Subtraction 53

    5.2 Increment / Decrement 54

    5.3 Counting 58

    5.4 Comparison, Coding, Detection 60

    5.5 Shift, Extension, Saturation 64

    5.6 Addition Flags 66

    5.7 Arithmetic Logic Unit (ALU) 68

    6 Multiplication 69

    6.1 Multiplication Basics 69

    6.2 Unsigned Array Multiplier 71

    6.3 Signed Array Multipliers 72

    6.4 Booth Recoding 73

    6.5 Wallace Tree Addition 75

    6.6 Multiplier Implementations 75

    6.7 Composition from Smaller Multipliers 76

    6.8 Squaring 76

    7 Division / Square Root Extraction 77

    7.1 Division Basics 77

    Computer Arithmetic: Principles, Architectures, and VLSI Design 2

    Contents

    7.2 Restoring Division 78

    7.3 Non-Restoring Division 78

    7.4 Signed Division 79

    7.5 SRT Division 80

    7.6 High-Radix Division 81

    7.7 Division by Multiplication 81

    7.8 Remainder / Modulus 82

    7.9 Divider Implementations 83

    7.10 Square Root Extraction 84

    8 Elementary Functions 85

    8.1 Algorithms 85

    8.2 Integer Exponentiation 86

    8.3 Integer Logarithm 87

    9 VLSI Design Aspects 88

    9.1 Design Levels 88

    9.2 Synthesis 90

    9.3 VHDL 91

    9.4 Performance 93

    9.5 Testability 95

    Bibliography 96

    Computer Arithmetic: Principles, Architectures, and VLSI Design 3

  • 1 Introduction and Conventions 1.2 Motivation

    1 Introduction and Conventions

    1.1 Outline

    Basic principles of computer arithmetic [1, 2, 3, 4, 5, 6, 7]Circuit architectures and implementations of main

    arithmetic operationsAspects regarding VLSI design of arithmetic units

    1.2 Motivation

    Arithmetic units are, among others, core of every datapath and addressing unitData path is core of :microprocessors (CPU)signal processors (DSP)data-processing application specific ICs (ASIC) and

    programmable ICs (e.g. FPGA)

    Standard arithmetic units available from librariesDesign of arithmetic units necessary for :non-standard operationshigh-performance componentslibrary development

    Computer Arithmetic: Principles, Architectures, and VLSI Design 4

    1 Introduction and Conventions 1.3 Conventions

    1.3 Conventions

    Naming conventions

    Signal buses :

    (1-D), (2-D), :(subbus, 1-D)

    Signals : , (1-D), (2-D),:(group signal)Circuit complexity measures :

    (area),(cycle time,

    delay),(area-time product),(latency, # cycles)

    Arithmetic operators : , , , , log (log2 )Logic operators : (or), (and),(xor),(xnor), (not)

    Circuit complexity measures

    Unit-gate model (gate-equivalents (GE) model) :Inverter, buffer : 0 0 (i.e. ignored)Simple monotonic 2-input gates (AND, NAND, OR,

    NOR) :1 1

    Simple non-monotonic 2-input gates (XOR, XNOR) :2 2Complex gates : composed from simple gatesSimple-input gates : 1 logWiring not considered (acceptable for comparison

    purposes, local wiring, multilevel metallization)Only estimations given for complex circuits

    Computer Arithmetic: Principles, Architectures, and VLSI Design 5

    1 Introduction and Conventions 1.4 Recursive Function Evaluation

    1.4 Recursive Function Evaluation

    Given : inputs , outputs , function (graph sym. : )

    Non-recursive functions (n.)Output is a function of input (or : const.)

    ; 0 1parallel structure :! !1

    funn.epsi19"17 mm1

    a0a1a2a3

    z0z1z2z3

    Recursive functions (r.)Output is a function of all inputs #$

    a) with single output %&1 (r.s.) :''&1

    ; 0 1'&1 01 '%&1

    1. is non-associative (r.s.n.)serial structure :! !

    funrsn.epsi19"24 mm

    1

    2

    3

    a0a1a2a3

    z

    Computer Arithmetic: Principles, Architectures, and VLSI Design 6

    1 Introduction and Conventions 1.4 Recursive Function Evaluation

    2. is associative (r.s.a.)serial or single-tree structure :! !log

    funrsa.epsi19"20 mm12

    a0a1a2a3

    z

    b) with multiple outputs (r.m.) (prefix problem) :

    &1

    ; 0 1 &1 01

    1. is non-associative (r.m.n.)serial structure :! !

    funrmn.epsi19"25 mm

    1

    2

    3

    a0a1a2a3

    z0z1z2z3

    2. is associative (r.m.a.)serial or multi-tree structure :! 2!log

    funrma1.epsi19"43 mm

    1

    2

    a0a1a2a3

    z0

    z1

    z2

    z3

    or shared-tree structure :! log !log

    funrma2.epsi19"21 mm12

    a0a1a2a3

    z0z1z2z3

    Computer Arithmetic: Principles, Architectures, and VLSI Design 7

  • 2 Arithmetic Operations 2.1 Overview

    2 Arithmetic Operations

    2.1 Overview

    arithops.epsi98"83 mm

    = , < +1 , 1 + , +/

    exp (x)

    trig (x)

    sqrt (x)

    log (x)

    >

    + ,

    fixed-point floating-pointbased on operation

    related operation

    hyp (x)

    co

    mp

    lexity

    (same as onthe left for

    floating-pointnumbers)

    1 shift/extension 7 division2 comparison 8 square root extraction3 increment/decrement 9 exponential function4 complement 10 logarithm function5 addition/subtraction 11 trigonometric functions6 multiplication 12 hyperbolic functions

    Computer Arithmetic: Principles, Architectures, and VLSI Design 8

    2 Arithmetic Operations 2.2 Implementation Techniques

    2.2 Implementation Techniques

    Direct implementation of dedicated units :

    always : 1 5in most cases : 6sometimes : 7, 8

    Sequential implementation using simpler units andseveral clock cycles (decomposition) :sometimes : 6in most cases : 7, 8, 9

    Table look-up techniques using ROMs :

    universal : simple application to all operationsefficient only for single-operand operations of high

    complexity (8 12) and small word length (note: ROMsize2% )

    Approximation techniques using simpler units : 712

    taylor series expansionpolynomial and rational approximationsconvergence of recursive equation systemsCORDIC (COordinate Rotation DIgital Computer)

    Computer Arithmetic: Principles, Architectures, and VLSI Design 9

    3 Number Representations 3.1 Binary Number Systems (BNS)

    3 Number Representations

    3.1 Binary Number Systems (BNS)

    Radix-2, binary number system (BNS) : irredundant,weighted, positional, monotonic [1, 2] -bit number is ordered sequence of bits (binary digits) :%&1%&20

    2 01

    Simple and efficient implementation in digital circuitsMSB/LSB (most-/least-significant bit) : %&1 / 0Represents an integer or fixed-point number, exactFixed-point numbers : &10 -bit integer

    &1&% -bit fraction

    Unsigned : positive or natural numbers

    Value :%&12%&1 120

    %&102

    Range : 0 2%1Twos (2s) complement : standard representation of

    signed or integer numbers

    Value :%&12%&1

    %&202

    Range : 2%&1 2%&1 1Computer Arithmetic: Principles, Architectures, and VLSI Design 10

    3 Number Representations 3.1 Binary Number Systems (BNS)

    Complement : 2%1 ,where

    %&1%&20

    Sign : %&1Properties : asymmetric range, compatible with

    unsigned numbers in many arithmetic operations(i.e. same treatment of positive and negative numbers)

    Ones (1s) complement : similar to 2s complement

    Value :%&1

    2%&1 1

    %&202

    Range : 2%&1 1 2%&1 1Complement : 2%1

    Sign : %&1Properties : double representation of zero, symmetric

    range, modulo2%1number system

    Sign-magnitude : alternative representation of signednumbers

    Value :11

    %&202

    Range : 2%&1 1 2%&1 1Complement : %&1%&20

    Sign : %&1Computer Arithmetic: Principles, Architectures, and VLSI Design 11

  • 3 Number Representations 3.1 Binary Number Systems (BNS)

    Properties : double representation of zero, symmetricrange, different treatment of positive and negativenumbers in arithmetic operations, no MSB toggles atsign changes around 0 (low power)

    Graphical representation

    numrep.epsi95"73 mm2n10

    unsigned

    2s complement

    1s complement

    sign-magnitude

    2n2 n1

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