MICAS Department of Electrical Engineering (ESAT) February 6th, 2007 Junfeng Zhou Promotor: Prof....

MICASDepartment of Electrical Engineering (ESAT)

February 6th, 2007

Junfeng Zhou

Promotor: Prof. Wim Dehaene

KULeuven ESAT-MICAS

Update of the “Digital EMC project”

MICASDepartment of Electrical Engineering (ESAT)

Part I: AMIS problems on RD2E PCB and Chip

Part II: di/dt measurement

Part III: Improved EMI-Suppressing regulator structure

Part IV: Future work

Outline

MICASDepartment of Electrical Engineering (ESAT)

Part I. AMIS problem 1 – USB module

USB module(with shielding box)

Oscillator inside the USB module

MICASDepartment of Electrical Engineering (ESAT)

AMIS problem 2 – Internal Oscillator

Internal Oscillator

Emission

VDD<1>

VSS

Cause trouble for 1 Ohm method,

Less problematic for di/dt measurement

MICASDepartment of Electrical Engineering (ESAT)

Part II. di/dt measurements

Low Drop-out /Serial Regulator

AMIS digital loadEMI-Suppressing

Regulator (MICAS)

GND

VCCVDD<1..10>

VDD2 = 3.3 V

VCCC =12 V

ii33

ii55 and V and V22

i1

ii44 and V and V11

PC

configurationbits

VCC = 4.5 V ~ 8 V

i2

Setup 1

Setup 2

Setup 3

MICASDepartment of Electrical Engineering (ESAT)

Focus on setup-1 – Some preliminary results

Internal Oscillator

Digital Load(Shift register Shift register output bufferoutput buffer)

GND

VDD2 = 3.3 V

i1

VDD3(separate power supply)

clk

EMI

MICASDepartment of Electrical Engineering (ESAT)

1. The impact of internal oscillator on CurrentCurrent SpectrumSpectrum of VDD2

QP<1>=QP<48>=QP<49>=QP<51>=‘1’Note: internal oscillator Note: internal oscillator disabledisable,, di/dt on VDD2,di/dt on VDD2,

Fig. 1 Fig. 2

QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’, Note: internal oscillator Note: internal oscillator enableenable,, di/dt on VDD2,di/dt on VDD2,

Conclusion: Internal clock may cause some problems

MICASDepartment of Electrical Engineering (ESAT)

2. Comparison of internal and external clock on CurrentCurrent SpectrumSpectrum of VDD2

Fig. 2 Fig. 3 QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’, Note: internal oscillator Note: internal oscillator enableenable,, di/dt on VDD2,di/dt on VDD2,

QP<1>=QP<48>=QP<51>=‘1’, QP<49>=‘0’, QP<50>=‘0’, Note: external clock Note: external clock enableenable,, di/dt on VDD2,di/dt on VDD2, internal oscillator is powered down internal oscillator is powered down Conclusion: Much worse with external clk

MICASDepartment of Electrical Engineering (ESAT)

3. The impact of oscillator inside USB module on CurrentCurrent SpectrumSpectrum of VDD2(no switching activity)

Fig. 4Fig. 2

No big difference

QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’, Note: di/dt on VDD2,Note: di/dt on VDD2, USB module is powered down USB module is powered down and the latch is enabledand the latch is enabled

QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’, Note: internal oscillator Note: internal oscillator enableenable,, di/dt on VDD2,di/dt on VDD2,

MICASDepartment of Electrical Engineering (ESAT)

4. The impact of internal oscillator in USB module on CurrentCurrent SpectrumSpectrum of VDD2(working condition)

Fig. 6Fig. 5

QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’ QP<53>=‘1’, Note:Note: di/dt on VDD2,di/dt on VDD2,

QP<1>=QP<48>=QP<49>=‘1’, QP<51>=‘0’ QP<53>=‘1’, Note: di/dt on VDD2,Note: di/dt on VDD2, USB module is powered down USB module is powered down and the latch is enabled and the latch is enabled

No big difference

MICASDepartment of Electrical Engineering (ESAT)

5. The impact of load on CurrentCurrent SpectrumSpectrum of VDD2

1 DFF chain 2 DFF chains

3 DFF chains

4 DFF chains

5 DFF chains

only clock present

• 4.02 MHz clk from internal oscillator, • Data input from on-chip 21-bit Random Generator.

MICASDepartment of Electrical Engineering (ESAT)

6. The impact of load on CurrentCurrent TransientTransient of VDD2

1 DFF chain 2 DFF chains 3 DFF chains

4 DFF chains 5 DFF chains

Pk-Pk: 23.8mV Pk-Pk: 45mV Pk-Pk: 66.3mV

Pk-Pk: 86.9mV Pk-Pk: 108.1mV

MICASDepartment of Electrical Engineering (ESAT)

7. The impact of load on di/dtdi/dt TransientTransient of VDD2

In general, as more DFF chains In general, as more DFF chains are on, the di/dt peak increases are on, the di/dt peak increases proportionally. proportionally.

MICASDepartment of Electrical Engineering (ESAT)

Conclusions

On-chip internal oscillator won’t hurt much, which is common for all measurements.

Oscillator inside USB module is not a problem at all, shielding box can do most of the job.

Setup for massive measurements is in preparation Automatic setup shall be ok by this week, Agreement on data to be measured ?

MICASDepartment of Electrical Engineering (ESAT)

• z1 cancel off the p1 • Make the p2 cut-off frequency• This zero is intrinsic for this feedback

topology

sacrifices dynamic sacrifices dynamic noise performancenoise performance

Part III: EMI-Suppressing Regulator possible improvement

Frequency

H(s)-dB

z1 p1p2

peakingPrevious structure problem: di/dt TF: pole-zero tracking !!

MICASDepartment of Electrical Engineering (ESAT)

Cascode compensation (Ahuja, JSSC 12/1983)

1

2• The feed forward path is removed,

• Miller effect still available,

• A2 Cc instead of (1+ A2 Cc ) for miller cap,

• Improved PSRR performance,Improved PSRR performance,

MICASDepartment of Electrical Engineering (ESAT)

Ahuja inspired...

• However, our di/dt TF is other way around !!!

• According to maple simulation, things are getting even worse because the -3dB frequency is shifted to even high frequency.

• The reason is that there is voltage gain from V3 to Vctrl, i.e.:

Vctrl /V3=gm2*Rota

If gm2*Rota <<

1 ??

This trick doesn’t help

!!! One degree of freedom is added !!!

Kill the Vctrl/V3 gain !

MICASDepartment of Electrical Engineering (ESAT)

Some formulas

tan

m

k

G

C

2m

C

g

C

2

2( )m m

C m m

g G

C g G

• p1 :

• p2 :

• z1 :

m

C

G

C

1

tan

m

k

g

C

m

C

G

C

• p1 :

• p2 :

• z1 :

NowNow

PreviousPrevious

(Assume:Assume: )1OTA mG g

MICASDepartment of Electrical Engineering (ESAT)

Maple calculation of the new structure

-3dB

100 kHz

• -3dB frequency moves down to below 40 -3dB frequency moves down to below 40 kHz,kHz,

• At 100 kHz, there is already decent di/dt At 100 kHz, there is already decent di/dt suppression.suppression.

Maple calculation is ready

To Be Done: • Spice simulation to verify Maple calculation ?• Re-design EMI-Suppressing Regulator based on this new structure ?

MICASDepartment of Electrical Engineering (ESAT)

Part IV: Future Work

Continue the digital load measurements,

More analysis for new structure: Stability and Transient, Spice simulation.

MICASDepartment of Electrical Engineering (ESAT)

Questions

Thank you for your attention